VLSI D i VLSI Design

mittenturkeyElectronics - Devices

Nov 26, 2013 (3 years and 9 months ago)

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VLSIDi
VLSI

D
es
ig
n
(
Circuit Techni
q
ue
)
(q)
Assoc.Prof. Dr. Somsak Choomchuay
kchsomsa
@
kmitl.ac.th
@
January, 2011
Department of Electronics
Faculty of Engineering
KingMongkut

sInstituteofTechnologyLadkrabang
King

Mongkut
s

Institute

of

Technology

Ladkrabang

(KMITL)
Bangkok 10520, Thailand
1
VLSI Design-Circuit technique
T
echnolo
g
y Consideration

Bipolar Technology
-Good in speed & Drive capability

﵏ャァ

﵏

﹯ﱯ
ッ葉キョﵰョ

s

s

ﵡﭥ

VLSI Design-Circuit technique
Bipolar Technolo
g
y
•Development
RTL(Resistor
TransistorLogic
-
RTL

(Resistor
-
Transistor

Logic
-DTL (Diode-Transistor Logic)
-
T
TL
(
Tr
a
n
s
i
stor
-
T
r
a
n
s
i
sto
r L
og
i
c)
(assto
asstoogc)
-ECL (Emitter Coupled Logic)
-IIL (Integrate Injection Logic)
•Current mode Operation
•Good speed but not low power
3
VLSI Design-Circuit technique
MOS Technolo
g
y
•Development
PMOS(Negativesupply)
-
PMOS

(Negative

supply)
-NMOS (Positive supply)
-
C
M
OS

(
P
os
i
t
iv
e,

dua
l
,

supp
l
y,
V
e
r
y
l
o
w
po
w
e
r
)
COS(oste,dua,suppy,eyopoe)
4
VLSI Design-Circuit technique
T
imin
g
definition
5
VLSI Design-Circuit technique
T
imin
g
definition
6
VLSI Design-Circuit technique
Inverter Gate
VDD
V
O
V
P
1>
β
β
n
pn
β
=
β
V
O
UT
V
IN
β
p
1<
β
β
p
n
GND
N
p
GND
7
VLSI Design-Circuit technique
Inverter Gate
GSnIN
VV
<
||
GS
p
I
N
DD
VVV>

1
!
E
n
pn
β
=
β
p
1
>
β
p
1
<
β
β
n
IHMIL
VVV
<
<
佈M佌
VVV
<
<
β
p
䥎GSn
噖>
DDINGS
p
VVV||−<
8
VLSI Design-Circuit technique
VDD
Inverter Gate
VOUT
VIN
P
GND
N
DSpDSn
II
=
1
>
β
n
pn
β
=
β
22
|)|(
2
)(
2
TpMDD
p
TnM
n
VVVVV−−
β
=−
β
1
!
E
p
1<
β
β
p
n
n
TnTpDD
VVV
β
β
+−||
β
p
p
n
p
M
V
β
β
+
β
=
1




W
W
9






=






μ=β
L
W
KP
L
W
C
OX
VLSI Design-Circuit technique
VDD
Inverter Gate
VOUT
VIN
P
GND
N
DD
V
V
=
1
>
β
n
pn
β
=
β
p
n
呮呰䑄
M
VVV
V
β
β
β
+−
=
||
2
M
V
=
1
>
β
p
1<
β
β
p
n
p
n
M
β
β
+1
(
)
2
1


V
V

β
β
p
W


(
)
()
2
2
1
2
|
|
TnDD
T
p
DD
p
n
VV
V
V


=
β
β
||
TpTn
VV
=




τ
τ
n
n
p
n
τ

L
τ











=
β
β
32−≈
μ
μ
=
p
n
p
n
KP
KP
10






=






μ=β
L
W
KP
L
W
C
OX
p
p
p
L
KP






β
μ
p
p
VLSI Design-Circuit technique
VDD
Inverter Gate
VOUT
VIN
P
GND
N
For symmetrical transfer
W
L
⎛⎞
⎜⎟
⎝⎠
p
n
L
W
L
32
11
⎜⎟
⎝⎠
=→
⎛⎞
⎜⎟
⎝⎠
For minimum feature size
n
L
⎝⎠
W
⎛⎞
p
W
L
W
1
1
⎛⎞
⎜⎟
⎝⎠
=
⎛⎞
⎜⎟
11
n
L
⎜⎟
⎝⎠
VLSI Design-Circuit technique
VDD
Inverter Gate
VOUT
VIN
P
GND
N
For symmetrical transfer
W
L
⎛⎞
⎜⎟
⎝⎠
p
n
L
W
L
32
11
⎜⎟
⎝⎠
=→
⎛⎞
⎜⎟
⎝⎠
For minimum feature size
n
L
⎝⎠
W
⎛⎞
p
W
L
W
1
1
⎛⎞
⎜⎟
⎝⎠
=
⎛⎞
⎜⎟
12
n
L
⎜⎟
⎝⎠
VLSI Design-Circuit technique
VDD
Inverter Gate
VOUT
VIN
P
GND
N
Switching Characteristics
Linear Region
(
)
n
V
V
R
β

1
(
)
TnDDn
n
V
V

β
(
)
1
p
R

(
)
||
TpDDp
p
VV

β
)
(
)
(
1
j
D
jA
D
jA
OX
DBDGDn
X
P
C
A
C
WL
C
CCC
+
+
=
+
=
)
(
)
(
2
j
D
jA
sw
D
jA
OX
X
P
C
A
C
WL
C
+
+
=



C
C
C
+
=
Dp
Dn
out
C
C
C
?

13
Gp
Gn
in
Dp
Dn
out
VLSI Design-Circuit technique
VDD
Inverter Gate
VOUT
VIN
P
GND
N
Rise time & Fall time
100
%
Vout
100
%
90%
)1(
/
1p
t
DDout
eVV
τ−
−=
10%
Time
Tr
t1
t2
ppLHr
ttttτ
=
τ
=
=

=
2.2)9ln(
12
n
t
DD
out
e
V
V
τ−
=
/
1
DD
out
nnHLf
ttttτ
=
τ
=
=

=
2.2)9ln(
12
14
VLSI Design-Circuit technique
VDD
Inverter Gate
VOUT
VIN
P
GND
N
Rise time & Fall time
%
Vout
100
%
90%
ppLHr
tttt
τ
=
τ=
=

=
2.2)9ln(
12

ForSymmetricalWaveform
10%
Time
Tr
t1
t2

For

Symmetrical

Waveform
r
f
tt
=
p
n

=

f
t
t
t
t
τ
=
τ
=
=

=
2
2
)
9
ln(
1
2
p
n
n
p
L
W
LW
μ
μ
=
)/(
)/(
nn
HL
f
t
t
t
t
τ
=
τ
=
=
=
2
.
2
)
9
ln(
1
2
p
Maximum frequency
f
1
15
r
f
f
tt
max
1
=
+
VLSI Design-Circuit technique
CMOS
Power & Energy Contribution
Power is drawn from a voltage source attached to the V
DD
p
in
(
s
)
of a chi
p
.
p()p
Instantaneous Power:
()()
DDDD
PtitV
=



DDDD
PtitV
()()
TT
EPtdtitVdt
==
∫∫

Energy:

AveragePower:
00
()()
DDDD
EPtdtitVdt
==
∫∫
1
()
T
E
PitVdt
==


Average

Power:
avg
0
()
DDDD
PitVdt
TT
==

16
VLSI Design-Circuit technique
CMOS
Power & Energy Contribution
Dynamic Power Consumption

chargeanddischargecapacitors

charge

and

discharge

capacitors
Short Circuit Current
short-circuit current path between supply rails during
switching
Leakage

Leakingdiodesandtransistor

Leaking

diodes

and

transistor
17
VLSI Design-Circuit technique
CMOS
Power & Energy Contribution
Dynamic Power Consumption
charge and discharge capacitors
Dynamic power is required to charge and discharge load
capacitances when transistors switch.
One cycle involves a rising and falling output.
On rising output, charge Q = CΔV = C
L
VDD
is required.

ョﱬ葉拾ﵰ﹄



ﱬ葉

オ





ﵰ





18
VLSI Design-Circuit technique
CMOS
Power & Energy Contribution
Example
: A typical CMOS inverter in DSM clocked at f =
250
MH
Z
hasC
L
=
50
fFanduseV
DD
=
1
8
V
250

MH
Z
has

C
L

50

fF

and

use

V
DD

1
.
8
V
P = αCV2f = (50fF)(1.8)2(250MHZ) = 40.5 µW
Example:
20 M logic transistors chip, average width: 12λ
VDD
=
1
2
Vuse
0
1
µ
mprocessCg
=
2
fF/mm
VDD
1
.
2

V
,
use

0
.
1

µ
m

process

Cg

2

fF/mm
,
activity factor = 0.1
L
Cm
f
FmnF
6
(
2010
)(
12
)(
0.05
/)(
2
/)
24
=
×λ
μ
λ
μ
=
L
dynamic
Z
f
PnFff
. mW/MH
29
()()(/)(/)
(0.1)(24)(1.2)3.4510
345

μμ
==×
=
19
VLSI Design-Circuit technique
CMOS
Complementary Structure
VDD
A
p
p
B
Y
n
Parallel form & Serial form
GND
n
VDD
p
AB
Y
p
20
GND
n
n
VLSI Design-Circuit technique
CMOS
Switching Criteria design
VDD
A
VDD
C
3
A
B
p
p
C
p
=
3
B
C
p=
3
P
Y
n=3
N
A
A
p
=
3
P
p
=
3
P
NOR, 3 I/P
B
n=3
N
B
Y
p
3
P
C
A
NAND, 3 I/P
GND
n=3
N
C
GND
B
n
n
C
A
21
VLSI Design-Circuit technique
CMOS
MOS Switch
Vin
Vin
V
n-Switch
V
t
φ
VDD-VGSn
VGSn
φ
V
潵t
C
L
V

t
φ
nMOS can conduct current when control = “1”
However, o/p drop
Tninout
VVV

=
nMOS is good for transferring logic “0”
22
VLSI Design-Circuit technique
CMOS
MOS Switch
Vin
V
out
Vin
p-Switch
Vout
φ
+VGS
p
out
VGSp
φ
CL
pMOS can conduct current when control = “0”
p
However, o/p drop
outTp
VV
=
nMOS is good for transferring logic “1”
23
VLSI Design-Circuit technique
CMOS
MOS Switch
Practical Switch / Transmission gate
φ
φ
INOUT
INOUT
φ
INOUT
φ
φ
φ
φ




=
=
OF
F
p
MOS
OFFnMOS




=
=
φ
φ
0
1
O
N
p
MOS
ONnMOS





==
==
=
φ
=
φ
ZVV
ZVV
p
utin
utin
0
0
,1
,0
1,0





==
==
=
φ
=
φ
1,1
0,0
0
,
1
0
0
utin
utin
VV
VV
p
24
VLSI Design-Circuit technique
CMOS
Logic Styles

Static CMOS Logic
(complement, AOI)

Dynamic CMOS Logic
Domino Logic
np-CMOS(Zipper)

Alternative Logic Styles

RatioedLogic
Ratioed

Logic
Pass Transistor Logic
DifftilCdVltSiLi
25

Diff
eren
ti
a
l

C
asco
d
e
V
o
lt
age
S
w
i
ng
L
og
i
c
VLSI Design-Circuit technique
CMOS
Logic Styles
In staticcircuits at every point in time (except when switching)
theoutputisconnectedtoeitherGNDorV
viaalow
the

output

is

connected

to

either

GND

or

V
DD
via

a

low

resistance path.
fan-in of nre
q
uires 2n
(
n
N
-t
yp
e + nP-t
yp
e
)
devices
q
(
yp
yp)
D
y
namiccircuits rel
y
on the tem
p
orar
y
stora
g
e of si
g
nal values
y
ypygg
on the capacitance of high impedance nodes.
requires on n+ 2 (n+1 N-type + 1 P-type) transistors
26
VLSI Design-Circuit technique
CMOS
Logic Styles
In staticcircuits at every point in time (except when switching)
theoutputisconnectedtoeitherGNDorV
viaalow
the

output

is

connected

to

either

GND

or

V
DD
via

a

low

resistance path.
fan-in of nre
q
uires 2n
(
n
N
-t
yp
e + nP-t
yp
e
)
devices
q
(
yp
yp)
D
y
namiccircuits rel
y
on the tem
p
orar
y
stora
g
e of si
g
nal values
y
ypygg
on the capacitance of high impedance nodes.
requires on n+ 2 (n+1 N-type + 1 P-type) transistors
27
VLSI Design-Circuit technique
CMOS
Logic Styles
Static CMOS
Dynamic CMOS
VDD
I
1
M
Clk
I
n
1
In2
InN
PUN
PMOS only
In
1
M
p
Clk
Out
C
F(In1,In2,…InN)
InN
In1
In
2
PDN
In
1
In2PDN
InN
C
L

In
2
InN
PDN
NMOS only
Me
Clk
28
VLSI Design-Circuit technique
CDABF+=
CMOS
Static AOI
CDABF+=
V
dd
A
B
C
D
A.B
C.D
P
P
CDAB
P
P
P
P
A
B
B
D
(a)
CD
P
P
F
P
P
AB
N
N
N
N
C
D
A
B
(
d
)
C
D
(A.B)+(C.D)
A
B
(
A
+B)(C+
D
)
CD
P
P
(
d
)
A
B
V
ss
29
(c)
B
C
D
(e)
VLSI Design-Circuit technique
CDABF+=
CMOS
Pseudo Static Logic
V
V
VDD
β
p
I
V
DD
V
DD
β
n
I
Dp
I
Dn
VOUT
n
MOS
g
ic array
m
-input
Ouput
n
MOS
g
ic array
m
-input
Ouput
n
V
IN
n
Lo
g
m
n
Lo
g
m
30
VLSI Design-Circuit technique
CMOS
Pseudo Static Logic
VDD
VDD
F
F
A0
A1
A2
A3
A4
A5
A0
A
A2
A
A4
A
A
1
A
3
A
5
5
43210
AAAAAAF+++++=
5
43210
AAAAAAF++=
31
VLSI Design-Circuit technique
CMOS
Tri-state Static Logic
V
Y
Data
V
DD
En
En
Y
En
Mp
Mn
En Y
0 z
En
Data
Mn
1 Data
32
VLSI Design-Circuit technique
CMOS
Clocked CMOS Logic
VDD
V
DD
Output, Hi Z
pMOS
Logic array
a
b
c
DD


φ
Y
φ
Mp
Mn
φ
Y=A.B
φ
φ
Logic valid
Mn
pMOS
Logic array
a
b
c
a
b
Input change: clock=low
Readout:
Clock
=
high
33
Read

out:
Clock

high
VLSI Design-Circuit technique
CMOS
Dynamic gates
Circuits rely on the temporary storage of signal values
on the capacitance of high impedance nodes.
VDD
Precharge
VDD
Precharge
Precharge
Y=(AB)+C
A
B
C
Y
nMOS
L
ogic array
m-input
Cout
φ
φ
Evaluate
φ
Evaluate
L
Evaluate
Inputchange(Pre
-
charge):
clock=low
34
Input

change

(Pre
charge):

clock=low
Read out (Evaluate):Clock = high
VLSI Design-Circuit technique
CMOS
Dynamic gates / Properties
Logic function is implemented by the PDN only
bfiiN
2
(
2
Nfi
num
b
er o
f
trans
i
stors
i
s
N
+
2

(
versus
2
N

f
or stat
i
c
complementary CMOS)

ﱬ葉オ




ﱬ

葉

オ














Non-ratioed -sizing of the devices does not affect the logic levels

若








﹧


reduced load capacitance due to lower inputcapacitance (Cin)
ddlditdtllttldi(Ct)
re
d
uce
d

l
oa
d
capac
it
ance
d
ue
t
o sma
ll
er ou
t
pu
t

l
oa
di
ng
(C
ou
t)
no Isc, so all the current provided by PDN goes into
dischargingC
35
discharging

C
L
VLSI Design-Circuit technique
CMOS
Dynamic gates / Properties
Overall power dissipation usually higher than static CMOS
no static current path ever exists between V
DD
and GND
(including Psc)
no glitching
hihtitibbiliti

hi
g
h
er
t
rans
iti
on pro
b
a
biliti
es
extra load on Clk










@

ョ



ﹰ










ﰠ


ﰠ



ﰠ


ﱯ﹯拾ﵡ葉ﱯ﹍


ﱯ

﹯拾

ﵡ葉

ﱯ




Needs a precharge/evaluate clock
36
VLSI Design-Circuit technique
CMOS
Dynamic gates / Problems
CLK
Charge Leakage
Clk
Out
(1)
(2)
Mp
CL
Clk
A
M
VOut
Evaluate
Clk
M
e
Lk
Precharge
L
ea
k
age sources
37
VLSI Design-Circuit technique
CMOS
Dynamic gates / Solutions
Charge Leakage
Solution : Bleeder Transistor
Bleeder
Bleeder
Clk
Mp
Mbp
Clk
Mp
Out
Mbp
CL
A
B
Out
A
B
Clk
Me
B
Clk
Me
Bleeder device is kept small to have high resistance

ﱩ
38

U
sua
ll
y
i
mp
l
emente
d

i
n a
f
ee
db
ac
k
con
fi
gurat
i
on to e
li
m
i
nate
the static power dissipation
VLSI Design-Circuit technique
CMOS
Dynamic gates / Problems
Charge Sharing
I.Assume that all inputs are set to 0
during precharge, and that the
capacitance CA
is discharged.
II.Later input A makes a 0 =>1 turning
M
a
on.ChargestoredoriginallyonC
L
M
a
on.

Charge

stored

originally

on

C
L
is redistributed (shared) over C
A
Charge sharing causes a drop in the output voltage, which
can not be recovered due to the dynamic nature of the
circuit
39
circuit
.
VLSI Design-Circuit technique
CMOS
Dynamic gates / Problems
Charge Sharing
CBAExample

⊕:
Clk

V?
C
L
=50fF
Clk
AA
Out

V

?
L
B
B

Ca㴱㕦=
C
b
=


CC
Cc㴱㕦=
C
b
=


Cd㴱て=
䍬C

∆Vout = VDD ((Ca + Cc)/((Ca + Cc) + CL))
VLSI Design-Circuit technique
CMOS
Dynamic gates / Solutions
Charge Sharing
Clk
M
p
Mk
p
Clk
A
Out
B
Clk
Me
Precharge internal nodes using a clock-driven transistor
(hfidd)
41
(
at t
h
e cost o
f

i
ncrease
d
area an
d
power
)
VLSI Design-Circuit technique
CMOS
Domino Logic
VDD
Precharge
2-stage, Basic Cell
Y
nMOS
ogic array
m-input
Cout
φ
Evaluate
L
The cascading of dynamic gates with an inverter inserted in
b
b
etween.
All the inputs are set to 0 at the end of precharge phase.
Thusonlytransitionsduringevaluationphaseare
0

1
42
Thus

only

transitions

during

evaluation

phase

are

0


1
=
Only non-invertinglogic can be implemented
VLSI Design-Circuit technique
CMOS
Domino Logic
Clk
Ini
PDN
In
j
Ini
PDN
In
j
Ini
PDN
In
j
In
i
PDN
In
j
Clk
j
j
j
j

Allthegatesareprechargedinparallelthen

All

the

gates

are

precharged

in

parallel

then

sequentially evaluated like falling dominos
Ver
y
hi
g
h s
p
eed can be achieve
d
ygp
only rising edge delay exists ( tPHL
= 0 )
The inverter also
iiii
43

i
ncreases no
i
se
i
mmun
i
ty
can be used to drive a bleeder device
VLSI Design-Circuit technique
CMOS
Dual-rail Logic
Inverting and non-inverting
inputs/output
inputs/output
Widely used in high-performance
microprocessors
VDD
VDD
VDD
a
a.ba.b
a+b
a+b
Y
Y
Mp2
Mp1
a
b
b
a
b
a
b
a
b
a
b
c
c
Sw1Sw2
44