Package Design Automation

mittenturkeyElectronics - Devices

Nov 26, 2013 (3 years and 4 months ago)

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VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

1

2013/11/26

Package Design Automation

Presenter: Tsun
-
Yu Yang

Professor: Hung
-
Ming Chen


VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

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2013/11/26

Outline


Introduction


Free
-
Assignment Routing Problem


Pre
-
Assignment Routing Problem


Conclusion and Future Work


Reference

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

3

2013/11/26

Traditional VLSI Design Flow

System Spec
.
Function
/
Architecture Design
Logic Synthesis
Circuit Design
Physical Synthesis
Fabrication
Packaging
Die

Package

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Institute of Electronics, National Chiao Tung University

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2013/11/26

What is Package Design?

Print Circuit Board

Component

Ball Grid Array

Finger

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

Layer 1

Layer 2

Layer 3

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2013/11/26

BGA Package Cross
-
section View

Wire Bond

Die

Finger

Bump Ball

Button View

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2013/11/26

Why Package Design Automation?


Number of IO pins has grown to hundreds, or
even thousands.


Electronic properties of high frequency signals
and analog signals have to be concerned.


VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

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2013/11/26

Two Kinds of Package Routing Problem


Free
-
Assignment Routing Problem


Determining the assignment of a finger to a ball
during routing


Easily solved by network
-
flow formulations



Pre
-
Assignment Routing Problem


The mapping among the fingers and balls can not
be changed during routing


Easy for Chip
-
Package
-
PCB Co
-
design


Much harder but more practical

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

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2013/11/26

PCB
-
Package
-
Chip Co
-
design Flow

Pin Assignment

Substrate Routing

Output Result

NO

YES

Routing results meet

requirements?

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2013/11/26

Challenges


Routing resource is limited by balls and vias


Via resource is limited


Any angle routing


Usually two layer routing

Ball

Via

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

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2013/11/26

Outline


Introduction


Free
-
Assignment Routing Problem

z
Pre
-
Assignment Routing Problem


Conclusion and Future Work


Reference

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

11

2013/11/26


Interchangeable Pin Routing with Application
to Package Layout

Man
-
Fai Yu; Darnauer, J.; Dai, W.W.
-
M., "Interchangeable pin routing
with application to package layout," Computer
-
Aided Design, 1996.
ICCAD
-
96. 1996 IEEE/ACM International Conference on Digest of
Technical Papers., pp.668
-
673, 10
-
14 Nov 1996

Free
-
Assignment Routing Problem:

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Motivation


P2TIR


Planar Two
-
Terminal Interchangeable Pin Routing


NP
-
C problem


BGA, PCB, and pin redistribution routing are
instances


Transform solution space to flows in a triangulated
routing network


Min
-
cost
-
max
-
flow heuristic considering only the most
important cuts in the design


The Heuristic handles multiple layers, prerouted nets,
and all angle, octilinear or rectilinear wiring styles


VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

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2013/11/26

Problem Definition


Instance



6
-
tuple (b, A, B, O, w, s)



b

the routing area boundary.


A

a set of polygons for one class of pins.


B

a set of polygons for the other class of pins.


0

a
set of polygons representing obstacles.


w

positive integer for the minimum wire width.


s

positive integer for the minimum wire spacing.




A, B, 0 are non
-
overlapping polygons inside b.


Output



Routable topological routing

VLSI Design Automation LAB

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Delaunay Triangulation

From http://en.wikipedia.org/wiki/Delaunay_triangulation


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Network Flow Formulation


Delaunay triangulation D on


Δ is the dual of D


Routing Network T(V,E,s,t) is a network where


V =


E consists of the following arcs



A pair of opposite arcs for each edge in Δ


A pair of opposite arcs between each point in


Each arc has a capacity and a non
-
negative cost


B
A
~
~



b
O
B
A



~
~
~
B
A
~
~

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

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2013/11/26

Network Flow Example

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

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The Flow Router

Building The Routing Network
Min
-
Cost Max
-
Flow Algo
.
Transforming a Flow Solution
to a Topological Routing
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Building The Routing Network


The edge in the dual of the triangulation

Capacity




The edges terminate at pins, t, s

Capacity


1













width
Wire
spacing
Wire
spacing
Wire
sizes
Pad
cut
of
Length
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Institute of Electronics, National Chiao Tung University

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Min
-
cost Max
-
Flow Algo.

Algorithm BUILDUP (Routing network T)

For totalflow


|A|

Path p


SHORTESTPATH(T)

If path is not found, return “T is unroutable”.

Increment flow on all edges of p by 1

endfor

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

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2013/11/26

Experimental Results

96 pin PGA with the triangulation graph and wiring

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

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2013/11/26

Experimental Results

A 444 staggered pin PGA package and a two layer 280
-
pin BGA package


Can accommodate
different design
rules of each layer

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

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2013/11/26

Experimental Results

400 connection test

probe card with prerouted nets.


These nets constrained the routing

so that wires to each chip is

grouped together.

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

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2013/11/26

Outline


Introduction


Free
-
Assignment Routing Problem


Pre
-
Assignment Routing Problem


Conclusion and Future Work


Reference

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

24

2013/11/26

A Two
-
Layer Global Router for Ball Grid
Array Packages

Y.
-
C. Lin, K.
-
Y. Lee, and T.
-
C. Wang, “A Two
-
Layer Global Router for
Ball Grid Array Packages,” in Proceedings of The Workshop on
Synthesis And System Integration of Mixed Information technologies
(SASIMI), Okinawa, Japan, March 2009.

Pre
-
Assignment Routing Problem:

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

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2013/11/26

Preliminaries


Ball Grid Model

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Problem Formulation


Given:


The order of fingers


The ball sequence of each ball row


The netlist which defines the connection from a finger
to a ball


The boundary capacity of each grid


Goal


Find a global routing which minimizes the total
overflow, maximum overflow and total wirelength.

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

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2013/11/26

Routing Algorithm

Order of Fingers
,
Balls
Sequences
,
Netlist
,
and
User
-
defined Parameters
Routing Graph
Construction
Max
_
overflow
_
toleranc
e
=
0
Fetching next net
Expanding Routing
Subgraph
Routing the net
Updating Routing Graph
Max
_
overflow
_
tolerance
+
1
Reset
_
graph
()
Fetch the
1
st
net
Output the Routing Results
Routed
?
The number of expands
reaching the bound
?
every net routed
?
Yes
Yes
No
No
Yes
No
Routing Subgraph
Determination
VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

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2013/11/26

Routing Graph Construction

Layer
-
1 grid node

Layer
-
2 grid node

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2013/11/26

Routing Subgragh determination Method

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

Experimental Result

Ckt.

[3]

[2]

Improvement(%)

wl

of

m
a
x

exe

wl

of

m
a
x

exe

wl

of

max

exe

data2

1430

24

5

4.14

1313

0

0

1.41

8.18

100

100

2.94x

data3

1223

3

3

1.47

1049

0

0

0.43

14.23

100

100

3.42x

data4

1218

5

2

5.94

1012

0

0

1.08

16.91

100

100

5.50x

data5

1220

2

2

5.54

1016

0

0

1.63

16.72

100

100

3.40x

data6

1444

17

4

4.11

1317

1

1

2.54

8.80

94.12

75

1.62x

data7

1699

32

3

13.36

1268

2

1

2.64

25.37

93.75

66.67

5.06x

data8

1482

42

6

17.45

1263

1

1

2.12

14.78

97.62

83.33

8.23x

avg

15.21

96.80

83.33

4.39x

30

2013/11/26

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

31

2013/11/26

Outline


Introduction


Free
-
Assignment Routing Problem


Pre
-
Assignment Routing Problem


Conclusion and Future Work


Reference

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

32

2013/11/26

Conclusion

[1]


Much more degree of freedom


Can handle multiple layers and pre
-
routed nets.


Can be applied in many fields such as ASIC,
packaging and testing.

[2]


Routability

according to pre
-
assignment


More practical

VLSI Design Automation LAB

Institute of Electronics, National Chiao Tung University

33

2013/11/26

Future Work


Solve
P
re
-
Assignment

Problem


In order to do Chip
-
Package
-
PCB Co
-
design


Construct a Package Design Automation Flow


Pin Assignment


Substrate Routing


Via Assign
ment

& Global Rout
ing


Detail Routing


Electricity Consideration


Pin

assignment for power/ground pins


Differential
P
air
C
onsideration


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Institute of Electronics, National Chiao Tung University

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2013/11/26

Reference

[1]Man
-
Fai Yu; Darnauer, J.; Dai, W.W.
-
M., "Interchangeable pin
routing with application to package layout," Computer
-
Aided Design, 1996. ICCAD
-
96. 1996 IEEE/ACM
International Conference on Digest of Technical Papers.,
pp.668
-
673, 10
-
14 Nov 1996

[2]Y.
-
C. Lin, K.
-
Y. Lee, and T.
-
C. Wang, “A Two
-
Layer Global
Router for Ball Grid Array Packages,” in Proceedings of The
Workshop on Synthesis And System Integration of Mixed
Information technologies (SASIMI), Okinawa, Japan, March
2009.

[3]Y. Kubo and A. Takahashi, “Global Routing by Iterative
Improvements for 2
-
Layer Ball Grid Array Packages,” IEEE
Transactions on Computer
-
Aided Design of Integrated
Circuits and Systems, vol. 25, no. 4, pp. 725

733, 2006.


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Institute of Electronics, National Chiao Tung University

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2013/11/26