lecture09 - Brown University

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Nov 26, 2013 (3 years and 9 months ago)

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S. Reda VLSI Design

Design and Implementation of VLSI Systems

(EN1600)

lecture09

Prof. Sherief Reda

Division of Engineering, Brown University

Spring 2008

[sources: Weste/Addison Wesley


Rabaey/Pearson]

S. Reda VLSI Design

Summary of transistor operation

NMOS transistor

PMOS transistor

S. Reda VLSI Design

DC transfer characteristics

S. Reda VLSI Design

PMOS on (linear), NMOS off

V
in0
V
in0
I
dsn
,
|
I
dsp
|
V
out
V
DD

Vin = 0

S. Reda VLSI Design

PMOS on (linear), NMOS on (saturation)

V
in1
V
in1
I
dsn
,
|
I
dsp
|
V
out
V
DD

V
in

= 0.2V
DD

S. Reda VLSI Design

PMOS on (linear ~ sat) and NMOS (sat)

V
in2
V
in2
I
dsn
,
|
I
dsp
|
V
out
V
DD

V
in

= 0.4V
DD

S. Reda VLSI Design

PMOS on (sat) NMOS on (linear)

V
in3
V
in3
I
dsn
,
|
I
dsp
|
V
out
V
DD

Vin = 0.6VDD

S. Reda VLSI Design

PMOS on (off ~ linear) and NMOS on (linear)

V
in4
V
in4
I
dsn
,
|
I
dsp
|
V
out
V
DD

Vin = 0.8VDD

S. Reda VLSI Design

NMOS on (linear) and PMOS cut off

V
in5
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
,
|
I
dsp
|
V
out
V
DD

Vin = VDD

S. Reda VLSI Design

Summary of voltage transfer function

A

B

C

E

D

S. Reda VLSI Design

Noise margins

S. Reda VLSI Design

CMOS inverter noise margins

desired regions

of operation

S. Reda VLSI Design

What is the impact of altering the PMOS width in
comparison to the NMOS width on the DC char?

V

in3

I

dsn

,


|

I

dsp

|

V

out

V

DD

V

in3

V

in3

n+
n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,

ox
= 3.9)
polysilicon
gate
V

in3

If we increase (decrease) the width of PMOS compared to NMOS



for the same input voltage, a higher (lower) output voltage is obtained

V

in

V

out

S. Reda VLSI Design

Impact of
skewing

transistor sizes on
inverter noise margins



Increasing (decreasing) PMOS width to NMOS width
increases (decreases) the low noise margin and decreases
(increases) the high noise margin

S. Reda VLSI Design

Pass transistor DC characteristics


As the source can rise to within a threshold voltage of the
gate, the output of several transistors in series is no more
degraded than that of a single transistor

S. Reda VLSI Design

Summary


Ideal transistor characteristics


Non
-
ideal transistor characteristics


Inverter DC transfer characteristics


Simulation with SPICE and integration with L
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