EM6021 VLSI Lanjut (II)

mittenturkeyElectronics - Devices

Nov 26, 2013 (3 years and 8 months ago)

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23-Sep-05EM 6021 Advance VLSI Design
EM6021 VLSI Lanjut(II)
Semester Ganjil
23-Sep-05EM 6021 Advance VLSI Design
Power-Reduction Design Space
System
Algorithm
Architecture
Logic & Circuit
Device & Process
23-Sep-05EM 6021 Advance VLSI Design
Processing
PowerReductions
•Improved device characteristics
•Smaller capacitances due to small dimensions,
special oxides, SOI, smaller junction capacitances
•Multi and variable Vth(e.g. low-leakage)
•Improved interconnect technology, like
copper and local interconnect lines
(Tungsten-filled grooves)
•More internal interconnect(straps, LIL) &
less external
23-Sep-05EM 6021 Advance VLSI Design
Circuit / Logic
Power Reductions
•Static design versus dynamic design
•Reduction of switching activity (f .C.Vdd
2
)
•Reduce number of transistors
•Clock & bus optimisation(gated clocking)
•Reduce the voltage swing & power supply
•Multi Vth
23-Sep-05EM 6021 Advance VLSI Design
Architecture
PowerReductions
•System level modifications most rewarding
•Clever signal processing
•Only carry out useful calculations (handshake)
•Clever encoding of sequential circuits
•Clever use of
coding
of data (adiabatic)
23-Sep-05EM 6021 Advance VLSI Design
Algorithmic
PowerReductions
•Algorithmic level modifications veryrewarding
•Minimize number of operations (e.g. less
parallelism)
•Data coding for minimum switching activity
23-Sep-05EM 6021 Advance VLSI Design
Long-Term Trends
•IC market growth averaged 17% per year
•CMOS circuits represent more than 75% of the world’s
semiconductors
•16% annual chip feature size reduction 1995-2001
•11% annual chip feature size reduction 2002 –future
•DRAM chip size increases 12% / year
•Pins/balls on packages increase 10% / year
•Pin cost decreases 5% / year
•Average package cost increases 5% / year
•Packaging share of system cost doubles over 15 years
–Drives migration to SoC, Multi-Chip Modules(MCMs), or SIP
devices
23-Sep-05EM 6021 Advance VLSI Design
Typical Problems
“Microscopic Problems”
•Ultra-high speed design
•Interconnect
•Noise, Crosstalk
•Reliability,
Manufacturability
•Power Dissipation
•Clock distribution.
“Macroscopic Issues”
•Time-to-Market
•Millions of Gates
•High-Level Abstractions
•Reuse & IP: Portability
•Predictability
•etc.
23-Sep-05EM 6021 Advance VLSI Design
Design Quality
•ACHIEVE SPECIFICATIONS (Static & Dynamic)
•DIE SIZE
•POWER DISSIPATION
•YIELD AND MANUFACTURABILITY
•RELIABILITY
•TECHNOLOGY UPDATABLE
•TESTABILITY
–generation of good test vectors
–availablityof reliable test fixture at speed
–design of testable chip
•YIELD AND MANUFACTURABILITY
–functional yield
–parametric yield
•RELIABILITY
–premature aging (Infant mortality)
–ESD/EOS
–latchup
–on-chip noise and crosstalk
–power and ground bouncing
•TECHNOLOGY UPDATABLE
–Easily updated to new design rules
23-Sep-05EM 6021 Advance VLSI Design
VLSI CAD Technology
CATAGORIES OF CAD TOOLS
1. High Level Synthesis (HDLs)
2. Logic Synthesis
3. Circuit Optimization
a. transistor sizing for min delays
b. process variations
c. statistical design
4. Layout
a. floorplanning
b. place & route
c. module generation
d. automatic cell placement and routing
5. Layout Extraction
6. Simulation (SPICE for circuit-level simulation)
7. Layout -Schematic Verification
8. Design Rule Check
23-Sep-05EM 6021 Advance VLSI Design
Computer Based on Vacuum Tubes
The ENIAC computer (1946)
•18000 tubes
•25 meters long
•3 meters high

Requires own
power plant
Reliability
problem !
23-Sep-05EM 6021 Advance VLSI Design
The History of MOSTechnology
Design of Low
Design of Low
-
-
Power, High
Power, High
-
-
Speed Digital VLSI for SoC
Speed Digital VLSI for SoC
1926 Lilienfeld: invention of bulk field-effect transistor
1955 Ross: suggests gate/dielectric/inversion layer stack
1960 Ligenza: first good quality (thin) SiO
2
on Si
1960 Atalla& Kahng: first surface FET
1958 Kilby: integrated circuit
1958 Hoerni& Noyce: planar technology
1959 Noyce: interconnect
1966 Kooi: field isolation (LOCOS)
1966 Dill: Self-aligned source and drain
1970-1972: memories
23-Sep-05EM 6021 Advance VLSI Design
The Early Days: 1947 -1960
Early bipolar chip (1958)First Germanium
transistor (1947)
Bipolar junction transistor,
Shockley (1949)
23-Sep-05EM 6021 Advance VLSI Design
Six Wiring / Interconnection Levels
MOS
Transistor
M4 –M5 Via
23-Sep-05EM 6021 Advance VLSI Design
ITRS 2003: Vdd& Power Dissipation
Year of Production 2003 2004 20052006 2007 2008 2009
Power Supply Voltage (V)
Vdd(high-performance)1.2 1.2 1.1 1.1 1.1 1.0 1.0
Vdd(Low Operating Power,
high Vddtransistors)1.0 0.9 0.9 0.9 0.8 0.8 0.8
Allowable Maximum Power High-performance with heatsink(W)149 158 167 180 189 200 210
Cost-performance (W)80 84 91 98 104 109 114
Battery (W)—(low-cost/hand-held)2.1 2.2 2.3 2.4 2.5 2.6 2.7
Design of Low
Design of Low
-
-
Power, High
Power, High
-
-
Speed Digital VLSI for SoC
Speed Digital VLSI for SoC
23-Sep-05EM 6021 Advance VLSI Design
Increase in Mips/ $
90 95 00 05 10
0.1 1 10 100 1000 10000
Year
Mips/ $
61 % grow / year
23-Sep-05EM 6021 Advance VLSI Design
New generation of Video processors
MPEG
MBS
+
VIP
MMI+AICP
1394
MSP
M-PI
MIPS
TriMedia VLIW
T-PI
Conditional
access
CAB

ASB and DTV
•domain specific
•and programmable
•0.18 µm / 8M
•1.8V / 4.5 W
•75 clock domains
•35 M transistors
23-Sep-05EM 6021 Advance VLSI Design
Summary
•Moore’s Law continues to hold
–Transistor count doubles every 26 months
–Microprocessor clock rates double every 34 months
•Progressed through SSI, MSI, LSI, VLSI, ULSI,
System-on-a-Chip(SoC) eras
•Now in System-on-a-Package(SIP) era
•Nanotechnology era has begun (features
smaller than 100 nanometers)
•Design will become increasingly difficult and multi-
disciplinary. Programmability & reuse crucial.
23-Sep-05EM 6021 Advance VLSI Design
Active + Passive Devices + Wires
wires
23-Sep-05EM 6021 Advance VLSI Design
Development of Processor Die Sizes
4004
8008
8080
8085
8086
286
386
486
Pentium ®proc
P6
1
10
100
19701980199020002010
Year
Die size (mm)
~7% growth per year
~2X growth in 10 years
Die size goes up, so wafer size has to go up!
~ 40mm
23-Sep-05EM 6021 Advance VLSI Design
Generations of Die Sizes
0.1
1
10
100
1.000
10.000
1960
1965
1970
1975
1980
1985
1990
1995
2000
2005
2010
2015
2020
2025
Total (10% growth per year)
Year
Total Si-area (10
6
inch
2
)
3
”+4

5”+6

8”
300
mm
450 mm
Source: I300I consortium 1998
23-Sep-05EM 6021 Advance VLSI Design
Size of Current Production Wafers
300 mm wafers& 90 nano-
meter technology
23-Sep-05EM 6021 Advance VLSI Design
The Costs per Transistor
0.0000001
0.0000001
0.000001
0.000001
0.00001
0.00001
0.0001
0.0001
0.001
0.001
0.01
0.01
0.1
0.1
1
1
1982
1982
1985
1985
1988
1988
1991
1991
1994
1994
1997
1997
2000
2000
2003
2003
2006
2006
2009
2009
2012
2012
cost:
cost:
¢
¢
-
-
per
per
-
-
transistor
transistor
Fabrication capital cost per transistor (Moore’s law)
Around 0.0001 $ cent / transistor
23-Sep-05EM 6021 Advance VLSI Design
From Mask Patterns to Structures
23-Sep-05EM 6021 Advance VLSI Design
From Mask Patterns to Structures (2)
oxidation
optical
mask
process
step
photoresistcoating
photoresist
removal (ashing)
spin, rinse, dry
acid etch
photoresist
stepper exposure
development
Typical operations in a single
photolithographic cycle (from [Fullman]).
Design layout
data from chip
designer
23-Sep-05EM 6021 Advance VLSI Design
Mask Making (Step & Repeat)
23-Sep-05EM 6021 Advance VLSI Design
Masks
•16 masks not unusual (set: 1 M$)
•Chromium on glass
•GDS2 of GIF format from layout CAD
23-Sep-05EM 6021 Advance VLSI Design
23-Sep-05EM 6021 Advance VLSI Design
Well Ion Implantation & Masks
N & P Well
formation
N well: NW
P well: PW
23-Sep-05EM 6021 Advance VLSI Design
Oxide and Poly Layer
poly
Local field
oxide
poly
gate
oxide
Oxide: OD
Poly: PO
23-Sep-05EM 6021 Advance VLSI Design
Source & Drain Extend Implantations
Use ion implantation (for well contacts)
N+
mask
23-Sep-05EM 6021 Advance VLSI Design
Spacer Formation (Sio2/Nitride)
spacers
23-Sep-05EM 6021 Advance VLSI Design
Source & Drain Ion Implants
N+
source & drain
S & D:
NP PP
23-Sep-05EM 6021 Advance VLSI Design
Contacts, Well Contacts & Vias
contacts
vias
Hitachi ion etcher
Well
contact
Contact: COVia: Via1, Via2

23-Sep-05EM 6021 Advance VLSI Design
Via Filling & Metallization
Tungsten, Alu, Cu
Metal: M1, M2, …
23-Sep-05EM 6021 Advance VLSI Design
Multiple Metallization Levels
23-Sep-05EM 6021 Advance VLSI Design
Comparing Key Processes
0.30.40.50.60.70.80.9
MotorolaIBMTIIntelSTUMCTSMC
IC Company
Pitch [um]
Active
Poly
Metal
Mx
n+/p+
0.18 µ
µµµm
23-Sep-05EM 6021 Advance VLSI Design
DesignData of Some Processes
•Currently in processing:
–0.13 um in high-volume production (2002)
–0.09 um (64 nm!) in research phase
–Voltages: down to 0.8V (Vth: 0.6-0.7)
23-Sep-05EM 6021 Advance VLSI Design
Manufacturing Process Problems
ITRS 2000 topics with “no known solution”:
•90 nm node:
•Shallow junctions with x
j
20-30 nm, R
s
250-


600 W/
•60 nm node:
–Gate dielectric thickness < 1.2 nm
–Gate tunnel current < 20 A/cm
2
–Gate doping > 4x10
20
cm
-3
MOS transistor requires research breakthroughs to
continue scaling beyond the 100 nm node!
23-Sep-05EM 6021 Advance VLSI Design
Future Developments in Processing
•Use other low-resistance conductors, like copper
(Copper mine)
•Use other dielectricalmaterials between interconnects
(low K materials) and gate oxide (high K)
•Use Silicon-on-Insulator process (costly)
•Inclusion of MEMS / RF & MOEMS
•Three dimensional ICs (stacking, bonding)
•Alternative devices: spin electronics,
molecular electronics, self-assembly
•Superconducting (R=0) electronics
23-Sep-05EM 6021 Advance VLSI Design
Major Developments (1)
Gate oxide thickness