CPE488D (VLSI) (VHDL Tutorial)

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Nov 26, 2013 (3 years and 9 months ago)

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INTRO TO VLSI DESIGN (CPE 448)




(VHDL Tutorial
)

Prof: Asuif Mahmood

Introduction to VHDL


VHDL is a language that is used to describe the behavior of
digital circuit designs.








VHDL designs can be simulated and translated into a form
suitable for hardware implementation.


History of VHDL


Developed by Department of Defense (DoD) between 1970s
and 80s, it was officially standardized as IEEE 1076 in 1987.



IEEE 1164 is the latest standardization that bring about the
interoperability between the common packages used by EDA
venders.



VHDL is now used extensively by industry and academia for
the purpose of simulating and synthesizing digital circuit
designs.


Digital System Design


Process flow of Digital System Design can be described more
by following flow:

Functional Design

Register Transfer Level Design

Logic Design

Circuit Design

Physical Design

Requirement

Behavioral Simulation

RTL Simulation Validation

Logic Simulation Verification, Fault Simulation

Timing Simulation , Circuit Analysis

Design Rule Checking

Design View and Abstraction Level


Based on implementation the type and level of abstraction is
decided.


In most of the implementation one is preferred over other.


Register Transfer

Boolean Expressions

Transfer Functions

Registers

Gates

Transistors

Cell

Modules

Chips

Boards

PHYSICAL

Benefits of VHDL


Interoperability :
The VHDL language provides set of constructs
that can be applied at multiple levels of abstractions and multiple
view of system. This significantly expands the scope of the
application of the language.



Technology Independence:
Independent of CPLD or FPGA can
be used for ASIC as will.



Design Reuse:
Once created be used components for future
usages.

VHDL Invariants


Case Sensitivity:
VHDL is not case sensitive.





White Space :
VHDL is not sensitive to white space (spaces and
tabs).




Comments:
Comments in VHDL begin with “
--
“ .

Dout <= A
and B;

doUt <= a
AND b;

nQ <= In_a
or In_b;

nQ <= In_a
or In_b;

--

This next section of code is used to blah
-
blah

--

blah
-
blah blah
-
blah. This type of comment is the best

--

fake for block
-
style commenting.


PS <= NS_reg;
--

Assign next state value to present state

VHDL Invariants(cont.)


Parenthesis:
a better idea is to practice liberal use of parenthesis
to ensure the human reader of your source code understands the
purpose the code.








VHDL Statements :
Every VHDL statement is terminated with a


semicolon.


if x = ‘0’ and y = ‘0’ or z = ‘1’ then

blah;

end if;


if ( ((x = ‘0’) and (y = ‘0’)) or (z = ‘1’) ) then

blah;

end if;

big_sig_b

:
in
std_logic
;

sv0, sv1 :
in
std_logic
;

VHDL Invariants(cont.)


if, case, and loop Statements:



Every
if statement has a corresponding then component




Each
if statement is terminated with an “end if”



If you need to use an “else if” construct, the VHDL version is

elsif”



Each
case statement is terminated with an “end case”



Each
loop statement has a corresponding “end loop“
statement

VHDL Invariants(cont.)


Identifiers :
An
identifier refers to the name given to discern
various items in VHDL (
variable names, signal names, and
port names
).


Listed below are the hard and soft rules:


Identifiers should be self
-
commenting. In other words, the text
you apply to identifiers should provide information as to the use
and purpose of the item the identifier represents.



Identifiers can be as long as you want (contain many characters).
Shorter names make for more readable code, but longer names
present more information. It’s up to the designer to choose a
reasonable identifier length.

VHDL Invariants(cont.)


Identifiers must start with an alphabetic character.


Identifiers must not end with an underscore and must never have
two consecutive.


Examples:



VHDL Invariants(cont.)


Reserved Words:
There is a list of words that have been
assigned special meaning by the VHDL language:


VHDL Coding Style


Coding style refers to the appearance of the VHDL source
code.


Best Practice :


Purposes for VHDL is Documentation , Synthesis and Simulation.



Document your code . So other people can understand your code.



Your code should be written readable.



Use uppercase for all VHDL keywords.



Use lowercase for all identifiers.



The color highlighting used be Altera Quartus II has been used to
enhance the readability of the VHDL code fragments.



VHDL Operators

Basic VHDL Design Units


A digital system in VHDL consists of a design
Entity

that can
contain other entities that are then considered components of
the top
-
level entity.



Each entity is modeled by an entity declaration and an
architecture body.



Entity declaration
consider as the interface to the outside
world that defines the input and output signals.



Architecture body
contains the description of the entity and is
composed of interconnected entities , processes and
components, all operating concurrently.

Basic VHDL Design Units (Cont.)


VHDL Entity

Interface

(Entity declaration)

Body

(Architecture )

Sequential,

Combinational

processes

Subprogram

Ports

Entity

A.
Entity Declaration
: The entity declaration defines the NAME
of the entity and lists the input and output ports. The general
form is as follows:










An entity always starts with the keyword
entity
, followed by its name
and the keyword
is
.



ENTITY

NAME_OF_ENTITY
IS


PORT

(
signal_names
:
mode

type
;




signal_names
:
mode
type
;




:




signal_names
:
mode
type
);

END

[NAME_OF_ENTITY] ;


Entity (cont.)


Next are the port declarations using the keyword
port
.



An entity declaration always ends with the keyword
end
, optionally [ ]
followed by the name of the entity.




The NAME_OF_ENTITY is a user
-
selected identifier.



signal names
consists of a comma separated list of one or more user
-
selected identifiers that specify external interface signals.



mode
: is one of the reserved words to indicate the signal direction:



in



indicates that the signal is an input



out



indicates that the signal is an output of the entity whose value can only
be read by other entities that use it.



buffer



indicates that the signal is an output of the entity whose value can
be read inside the entity’s architecture.


inout



the signal can be an input or an output.


Entity (Cont.)


Type
: a built
-
in or user
-
defined signal type. Examples:



bit



can have the value 0 and 1.



bit_vector



is a vector of bit values (e.g. bit_vector (0 to 7)



std_logic, std_ulogic, std_logic_vector, std_ulogic_vector
: can have 9
values to indicate the value and strength of a signal. Std_ulogic and std_logic
are preferred over the bit or bit_vector types.



boolean



can have the value TRUE and FALSE.



integer



can have a range of integer values.



real



can have a range of real values.



character



any printing character.



time



to indicate time.


Entity (cont.)


Example 1:


Full adder:

Entity

fulladder
IS


PORT
(a, b, c:
IN

std_logic;



sum, carry:
OUT

std_logic);


END

fulladder;


Full

Adder

a

b

c

carry

sum

Entity (cont.)


Example2:


AND Gate:


Entity

andgate

IS


PORT
(




a:
IN

std_logic;




b:
IN

std_logic;




c:
OUT

std_logic);

END

andgate
;


a

b

c

Entity (cont.)

B.
Architecture body:


The architecture body specifies how the circuit operates and how it is
implemented.


An entity or circuit can be specified in a variety of ways, such as
behavioral
,
structural

(interconnected components), or
dataflow
.


The architecture body looks as follows:


ARCHITECTURE

architecture_name
OF

NAME_OF_ENTITY
IS


--

Declarations



--

components declarations



--

signal declarations



--

constant declarations



--

function declarations



--

procedure declarations



--

type declarations



BEGIN


--

Statements

END

architecture_name;


Entity (cont.)


Example :


AND Gate:

Entity

andgate

IS


PORT
(




a:
IN

std_logic;




b:
IN

std_logic;




c:
OUT

std_logic);

END

andgate
;


b

c

a

ARCHITECTURE

synthesis1
OF

andgate
IS


BEGIN



c <= a AND b;

END

synthesis1;

Entity (cont.)

C.
Library and Packages
:
library

and
use

keywords


A library can be considered as a place where the compiler stores
information about a design project.



A VHDL package is a file or module that contains declarations of
commonly used objects, data type, component declarations, signal,
procedures and functions that can be shared among different VHDL
models.



std_logic is defined in the package ieee.std_logic_1164 in the ieee
library.



In order to use the std_logic one needs to specify the library and
package.

Entity (cont.)


This is done at the beginning of the VHDL file using the
library

and the
use

keywords as follows:







The .
all

extension indicates to use all of the ieee.std_logic_1164
package.


LIBRARY

ieee;

USE

ieee.std_logic_1164.
ALL
;


Simple System Design


Example1:


Half Adder

LIBRARY

ieee;

USE

ieee.std_logic_1164.
ALL
;



ENTITY

half_adder
IS


PORT
( a,b


: in bit;



sum,carry : out bit);

END

half_adder;



ARCHITECTURE

bool
OF

half_adder
IS

BEGIN


sum <= (a xor b);


carry <= (a and b);

END

bool;


Half

Adder

a

b

carry

sum

Simple System Design (cont.)


Example 2:


4 bit comparator:

LIBRARY

ieee;

USE

ieee.std_logic_1164.
ALL
;



Entity

eq_comp4
IS


PORT

(



a,b

: in bit_vector(3 downto 0);




equals


: out bit);

END

eq_comp4;



AECHITECTURE

dataflow
OF

eq_comp4
IS

BEGIN


equals <= '1'



when (a = b)



else '0';

END

dataflow;


Basic System Descriptions


From the level of abstraction systems can be described in
there types:


1.
Behavioral


2.
Dataflow


3.
Structural



Behavioral


We can describe a system in terms of processing it performs
on its input signals and the type of output it signals it produces.


Example :

LIBRARY

ieee;

USE

ieee.std_logic_1164.
ALL
;



ENTITY

eq_comp4 is



PORT
(


a,b : in std_logic_vector(3 downto 0);


equals : out std_logic);


END

;



ARCHITECTURE

behvioral
OF

eq_comp4
IS

BEGIN


comp:
PROCESS

(a,b)



BEGIN




IF

(a=b) then


equals <= '1';

Else


equals <= '0';

END

IF
;


END

PROCESS

comp;

END

behvioral;


Dataflow


Dataflow architecture specifies how data will be transferred
from signal to signal and input to input without the sequential
statements.


Some distinguish between dataflow and behavioral others
lump them together in behavioral description.


Primary difference is that behavioral uses processes while
dataflow does not.


The other main difference between dataflow and behavioral
architectures is that the body of the process statement
contains only
sequential statements.

Dataflow


Example 1 :

LIBRARY

ieee;

USE

ieee.std_logic_1164.
ALL
;



Entity

eq_comp4
IS


PORT

(



a,b

: in bit_vector(3 downto 0);




equals


: out bit);

END

eq_comp4;



AECHITECTURE

dataflow
OF

eq_comp4
IS

BEGIN


equals <= '1'



when (a = b)



else '0';

END

dataflow;


Dataflow (cont.)


Example 2:

library

ieee;

use

ieee.std_logic_1164.all;



entity

eq_comp4
is


port

(



a,b

: in std_logic_vector(3 downto 0);



equals

: out std_logic);


end

eq_comp4;



architecture

bool of eq_comp4
is

begin


equals <= not (a(0) xor b(0))




and not (a(1) xor b(1))




and not (a(2) xor b(2))




and not (a(3) xor b(3));

end

bool;


Structural


One way to describe a system is to describe component chips and
the interconnections assuming that the user is familiar with it.


This kind of definition is the structural definition.


Example 1:


library

ieee;

use

ieee.std_logic_1164.all;



entity

full_adder
is



port(



a,b,ci : in std_logic;



sum,co : out std_logic);



end

full_adder;



architecture

bool
of

full_adder
is

signal

s1,s2,s3 : std_ulogic;

begin



u0: s1 <= (a xor b);


u1: s2 <= (ci and s1);


u2: s3 <= (a and b);


u3: sum <= (s1 xor ci);


u4 : co <= (s2 or s3);

end

bool
;


Structural (cont.)


Example 2:

library

IEEE;

use

IEEE.STD_LOGIC_1164.
all
;



entity

fa_en
is


port
(A,B,Cin
:in

bit
; SUM, CARRY
:out

bit
);

end

fa_en;



architecture

fa_ar
of

fa_en
is



component

ha_en


port
(A,B
:in

bit
;S,C
:out

bit
);



end

component
;



signal

C1,C2,S1
:bit
;



begin


HA1
:
ha_en
port

map
(A,B,S1,C1);


HA2
:
ha_en
port

map
(S1,Cin,SUM,C2);


CARRY

<=
C1
or

C2;

end

fa_ar;

library

IEEE;

use

IEEE.STD_LOGIC_1164.
all
;



entity

ha_en
is


port
(


A,B
:

in

BIT
;


S,C
:

out

BIT
);

end

ha_en;



architecture

ha_beha_ar
of

ha_en
is

begin


process_beh
:process
(A,B)


begin


S
<=

A
xor

B;


C
<=
A
and

B;



end

process

process_beh;



end

ha_beha_ar;

Structural (cont.)


Example 3 (not complete):

library

ieee;

use

ieee.std_logic_1164.all;



entity

eq_comp4
is


port

(



a,b

: in std_logic_vector(3 downto 0);



equals

: out std_logic);


end

eq_comp4;



architecture

struct
of

eq_comp4
is


signal
x : std_logic_vector(3 downto 0);

Begin


U0: xnor_2
port map
(a(0),b(0),x(0));


U1: xnor_2
port map
(a(1),b(0),x(0));


U2: xnor_2
port map
(a(2),b(0),x(0));


U3: xnor_2
port map
(a(3),b(0),x(0));


U4: and_4
port map
(x(0),x(1),x(2),x(3),equals);

End

struct;


Components


Component declaration




COMPONENT

identifier
IS


[
generic

(generic_interface_list ); ]


[
port

(port_interface_list ); ]

END COMPONENT

[ identifier ];


COMPONENT

flipflop
IS


generic

(Tprop, Tsetup, Thold : delay_length);


port

(clk, clr, d

:


in

bit;



q

:

out

bit );

END COMPONENT

flipflop;

Component Example


Example:

entity reg4

is


port (clk, clr

: in

bit;



d


: in

bit_vector(0 to 3);



q


: out bit_vector(0 to 3);

end entity reg4;


architecture struct of reg4 is


component flipflop is



generic (Tprop, Tsetup, Thold

: delay_length);



port ( clk, clr, d


: in bit;



q



: out bit);


end component flipflop;

begin

bit0:

component flipflop


generic map ( Tprop => 2 ns, Tsetup => 2ns, Thold => 1ns)


port map ( clk => clk, clr => clr, d => d(0), q => q(0) );

bit1:

component flipflop


generic map ( Tprop => 2 ns, Tsetup => 2ns, Thold => 1ns)


port map ( clk => clk, clr => clr, d => d(1), q => q(1) );

bit2:

component flipflop


generic map ( Tprop => 2 ns, Tsetup => 2ns, Thold => 1ns)


port map ( clk => clk, clr => clr, d => d(2), q => q(2) );

bit3:

component flipflop


generic map ( Tprop => 2 ns, Tsetup => 2ns, Thold => 1ns)


port map ( clk => clk, clr => clr, d => d(3), q => q(3) );

end architecture struct;

Quartus II Software


We will use in this course
Quartus II Software
to write the
VHDL projects.



The software already installed on all Computers at the
technology Building LAB110,LAB111 and LAB113.



You can install the
Quartus II Software
on your PC or your
laptop.



To install the software on your computer
Click Here

Handout and Videos


Handout:
Quick Start Guide.pdf



You can watch the videos online or you can download it:


Online:

1.
https://mysupport.altera.com/etraining/webex/QII_80_Intro/player.html

2.
https://mysupport.altera.com/etraining/webex/Tutorial/qtutorial.htm




Download:

1.
https://mysupport.altera.com/etraining/webex/QII_80_Intro/QII80.zip

2.
https://mysupport.altera.com/etraining/webex/Tutorial/Tutorial.zip


First Assignment


Read all Handouts what I gave you in the lab.


Watch the videos.


Practice the all examples which in the handouts:


Understand each later in the example.


You have to submit hard copy of your assignment.


You have to do demo during the next lab.


Be ready for questions.


Please do not copy from any one.