Course overview, VLSI design

mittenturkeyElectronics - Devices

Nov 26, 2013 (3 years and 11 months ago)

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Design Abstraction Levels
n+n+
S
G
D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
Behavior description
(Verilog, HDL, etc.)
Silicon compilation
Physical description
(layout, circuit, etc.)
Simulation for system
specification
Course overview, VLSI design
￿
VLSI design challenges

Power consumption
, especially leakage
power. Also affects chip cooling.

Noise issues
, as transistors and wires move
closer together. Design of noise-tolerant
circuits.

Clocking
: distributing high-frequency clock
with minimum of skew (difference in clock
arrival time between points on a chip)
Course overview, VLSI design
￿
VLSI design challenges, continued

Scaling
: continue to make transistors smaller.
Why? Smaller transistors are faster, can put
more transistors on a die

Integration:
combining large VLSI systems to
form a “system-on-a-chip”
-
Design for reuse
-
Design for testability
-
Advanced CAD tools required
VLSI Design Stages
￿
Logic Design/Simulation

Partition architecture into cycles / latches

Verify against architecture specification
￿
Circuit Design/Simulation

Transistor sizing

Performance verification
￿
Static Timing Analysis

Verify margin requirements
￿
Physical Design

Draw masks for layout, following design rules

Placement and routing

Parasitic extraction
VLSI CAD Tools
￿
Synthesis

Architectural, Logic, Physical
￿
Static Analysis

Design rule checking (DRC)

Circuit extraction

Design verification

Test generation
￿
Dynamic Analysis

Logic simulation

Switch-level simulation

Circuit simulation (SPICE)
This design style provides a means for fast prototyping and
Also for cost-effective chip design, especially for low volume applications.
VLSI Design Approaches
￿
Gate Arrays

Prefabricated chips containing transistors/gates and
local interconnects

Upper level wires added to implement design

Quick, but sub-optimal
￿
Standard Cells

Cells in a library with fixed height, width

Cells characterized for delay, power

Design is fast –layout mostly automatic
￿
Custom Design

Variable sizes

Extensive checking / verification required

Dense design, best performance
Performance
Ease of Design
Brief Review of MOSFETs
￿
A brief review of the structure and behavior of FETsis in
order…
￿
What makes a FET?

A channelfor conduction –connected between two terminals
called sourceand drain

A means of controlling conduction –called the gate

Voltage applied to the gate controls the conductivity of channel
Gate
Source
Drain
Substrate
(Optional)
Circuit
Schematic
How does conduction occur?
￿
Consider a p substrate (substrate with excess of holes) and a gate
over the substrate…
Gate
Voltage
++++
+++
++++
Gate
Insulator
Channel
Substrate
￿
Note that native silicon is “P” –hence this example!
When does conduction occur?
￿
As Gate Voltage becomes positive, holes in the channel begin to be
repelled.

This is called depletionbecause the channel is being depleted of
majority carriers.
Small +
Gate
Voltage
++
+++
++++
Gate
Insulator
Channel
Substrate
+
+
When does conduction occur?
￿
As voltage increases, all majority carriers are repelled away.
Voltage then begins to attract minority carriers.

This is called inversionbecause the channel is being populated by
minority carriers.
Large +
Gate
Voltage
--
+++
++++
Gate
Insulator
Channel
Substrate
+
+
++
--
￿
Voltage where inversion begins: Threshold Voltageor Vt
￿
The channel then becomes conductive –becomes a low-ohm
resistor
This is called an
n-channeldevice.
NMOS and PMOS
￿
The example up above was of an n-channel MOS transistor

This is usually called an NMOS device, meaning “n-channel MOS
device”
￿
There is an opposite case:

Majority carrier = electron

Minority carrier = channel carrier = hole

p-channel MOS device = PMOS
￿
Opposite reasoning applies

Applied gate voltage is negative and inversion occurs below some
negative threshold voltage
￿
Since holes move more slowly than electrons, P-channel devices are
always weaker than the same sized N-channel devices
￿
Silicon must be doped with N material (rich in donor electrons) in
order to form a P-channel device

Changes the “+” to “-” in the original diagram above

Called an “N-well” as will be seen below
Why are certain dopantsused?
￿
Carbon, Silicon, and Germanium can both accept and donate electrons

One column to the left = 1 less electron = Acceptorof electrons (Boron)

One column to the right = 1 more electron = Donorof electrons (Phosphorus)
￿
Some semiconductors are made from equal parts of column III and column V –
called III-V semiconductors

Examples: GaAs, InP, GaAlAs
Calculating V
T0
(Equation 3.19)
￿
Four physical components of threshold voltage

Work function difference between gate and channel
-
ΦGC

Gate voltage needed to change surface of channel
-
ΦF
–See equations 3.4 and 3.5

Gate voltage needed to deplete the channel
-
Function of embedded charge, Q
B0
, and gate capacitance, C
OX
-
QB0
can be found from Eq. 3.16
-
COX
can be found from gate thickness and intrinsic capacitance of
silicon dioxide (Eq. 3.18)

Gate voltage to offset charges in gate oxide and oxide interface
-
Function of embedded charge Q
OX
and gate capacitance C
OX
￿
For n-channel (p-type semiconductor) devices:

Increase V
T0
by adding p dopants, decrease V
T0
by adding n
dopants
Homework Set 1
￿
Work problem 3.1 in the book
Another look at the MOSFET…
￿
We saw above how changing the gate voltage controlled the channel

Gate voltage is typically referenced to the Source, and so is called V
GS

Key point: V
GS
affects the conductivity of the channel
￿
Next, let’s look at what affects current flow through the channel…
Gate
Source
Drain
Substrate
(Optional)
Circuit
Schematic
Channel
Effect of Current Flow: What happens when V
DS
>0?
￿
When the channel conducts (inverts), it behaves like a
resistor

Current is (approximately) a linear functionof voltage

The value of the resistance drops as the gate voltage is
increased –more minority carriers in the channel

May be easier to think in terms of the conductivityincreasing
with the gate voltage
￿
What happens if/when you try to push current through
the channel?

Current flow causes the inverted minority carriers to shift around
￿
Enough current flow causes the drain side to become
“pinched off”

The channel then stops before it reaches the opposite side

Minority carriers can still tunnel over to the other side

Channel becomes a constant-current source at that point –
increases in voltage do not increase the current

The channel is said to be saturatedat that point
Resulting I-V graph of a MOSFET (Fig. 3.17)
So what do we need to fabricate?
Example: NMOS (Not to scale!)
Gate
Insulator
P Substrate
Source (N)Drain (N)
Wiring
Wiring
￿
Let’s see how these devices are fabricated…
Fabrication cycle
Thermal Oxidation: Basic Concepts
•SiO
2
and the Si/SiO
2
interface are the principal
reasons for silicon’s dominance in the IC industry.
￿
SiO
2
:
• Easily selectively etched using lithography.
• Masks most common impurities (B, P, As, Sb
).
• Excellent insulator (> > 10
16
cm, Eg> 9eV).
• High breakdown field (10
7
Vcm
-1
)
• Excellent junction passivation.
• Stable bulk electrical properties.
• Stable and reproducible interface with Si.
Uses of SiO
2
in Silicon Technology
Modern example of gate oxide
￿
Found recently in a modern process…
7 atomsthick!
Individual
atoms
￿
This is so thin that quantum-mechanical tunnelingoccurs from channel to
gate
￿
This has driven the search for materials with a higher dielectric constant
(higher “kappa” or ) so that the gate oxide can be thicker but with the same
overall capacitance
Dual Well CMOS
TA 3-7, p. 94
(bottom)
Metallization plan
Technology Generations
TA 3-12, p. 97
(middle)
TA 3-15, p. 98
(bottom)
Design Rules: Bridges between
technology capability and
design considerations
Layout Design Rules
MOS transistor