Electronics - Devices

Nov 26, 2013 (4 years and 5 months ago)

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Introduction to

CMOS VLSI

Design

Lecture 11:

David Harris

Harvey Mudd College

Spring 2004

CMOS VLSI Design

Slide
2

Outline

Single
-

Carry
-

Carry
-

Carry
-

Carry
-

Carry
-

CMOS VLSI Design

Slide
3

Single
-

A

B

C
out

S

0

0

0

1

1

0

1

1

A

B

C

C
out

S

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

A
B
S
C
out
A
B
C
S
C
out
out
S
C

out
S
C

CMOS VLSI Design

Slide
4

Single
-

A

B

C
out

S

0

0

0

0

0

1

0

1

1

0

0

1

1

1

1

0

A

B

C

C
out

S

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

1

1

1

0

1

0

0

0

1

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

A
B
S
C
out
A
B
C
S
C
out
out
S A B
C A B
 

out
(,,)
S A B C
C MAJ A B C
  

CMOS VLSI Design

Slide
5

PGK

For a full adder, define what happens to carries

Generate: C
out

= 1 independent of C

G =

Propagate: C
out

= C

P =

Kill: C
out

= 0 independent of C

K =

CMOS VLSI Design

Slide
6

PGK

For a full adder, define what happens to carries

Generate: C
out

= 1 independent of C

G = A

B

Propagate: C
out

= C

P = A

B

Kill: C
out

= 0 independent of C

K = ~A

~B

CMOS VLSI Design

Slide
7

Brute force implementation from eqns

out
(,,)
S A B C
C MAJ A B C
  

A
B
C
S
C
out
MAJ
A
B
C
A
B
B
B
A
C
S
C
C
C
B
B
B
A
A
A
B
C
B
A
C
B
A
A
B
C
C
out
C
A
A
B
B
CMOS VLSI Design

Slide
8

Factor S in terms of C
out

S = ABC + (A + B + C)(~C
out
)

Critical path is usually C to C
out

S
S
C
out
A
B
C
C
out
MINORITY
CMOS VLSI Design

Slide
9

Layout

Clever layout circumvents usual line of diffusion

Use wide transistors on critical path

Eliminate output inverters

CMOS VLSI Design

Slide
10

Complementary Pass Transistor Logic (CPL)

Slightly faster, but more area

A
C
S
S
B
B
C
C
C
B
B
C
out
C
out
C
C
C
C
B
B
B
B
B
B
B
B
A
A
A
CMOS VLSI Design

Slide
11

Dual
-
rail domino

Very fast, but large and power hungry

Used in very fast multipliers

C
out
_h
A_h
B_h
C_h
B_h
A_h

C
out
_l
A_l
B_l
C_l
B_l
A_l

S_h
S_l
A_h
B_h
B_h
B_l
A_l
C_l
C_h
C_h

CMOS VLSI Design

Slide
12

N
-

Each sum bit depends on all previous carries

How do we compute all these carries quickly?

+
B
N...1
A
N...1
S
N...1
C
in
C
out
11111
1111
+0000
0000
A
4...1
carries
B
4...1
S
4...1
C
in
C
out
00000
1111
+0000
1111
C
in
C
out
CMOS VLSI Design

Slide
13

Carry
-

Critical path goes from Cin to Cout

Design full adder to have fast carry delay

C
in
C
out
B
1
A
1
B
2
A
2
B
3
A
3
B
4
A
4
S
1
S
2
S
3
S
4
C
1
C
2
C
3
CMOS VLSI Design

Slide
14

Inversions

Critical path passes through majority gate

Built from minority + inverter

Eliminate inverter and use inverting full adder

C
out
C
in
B
1
A
1
B
2
A
2
B
3
A
3
B
4
A
4
S
1
S
2
S
3
S
4
C
1
C
2
C
3
CMOS VLSI Design

Slide
15

Generate / Propagate

Equations often factored into G and P

Generate and propagate for groups spanning i:j

Base case

Sum:

:
:
i j
i j
G
P

:
:
i i i
i i i
G G
P P
 
 
0:0
0:0
0
in
GC
P

0:0
0:0
0
in
GC
P

0:0 0
0:0 0
G G
P P
 
 
i
S

CMOS VLSI Design

Slide
16

Generate / Propagate

Equations often factored into G and P

Generate and propagate for groups spanning i:j

Base case

Sum:

:::1:
::1:

i j i k i k k j
i j i k k j
G G P G
P P P

 

:
:

i i i i i
i i i i i
G G A B
P P A B
 
  
0:0
0:0
0
in
GC
P

0:0
0:0
0
in
GC
P

0:0 0
0:0 0
0
in
G G C
P P
 
 
1:0
i i i
S P G

 
Gi
-
1:0 is simply the carry
-
in of this
stage, ie., Ci

Si = Pi xor Ci = (Ai xor Bi) xor Ci

Valency
-
2 equation;
uses P/G of two smaller
groups

CMOS VLSI Design

Slide
17

PG Logic

S
1
B
1
A
1
P
1
G
1
G
0:0
S
2
B
2
P
2
G
2
G
1:0
A
2
S
3
B
3
A
3
P
3
G
3
G
2:0
S
4
B
4
P
4
G
4
G
3:0
A
4
C
in
G
0
P
0
1: Bitwise PG logic
2: Group PG logic
3: Sum logic
C
0
C
1
C
2
C
3
C
out
C
4
C4 = G4 + P4 G3:0

CMOS VLSI Design

Slide
18

Carry
-
Ripple Revisited

:0 1:0

i i i i
G G P G

 
S
1
B
1
A
1
P
1
G
1
G
0:0
S
2
B
2
P
2
G
2
G
1:0
A
2
S
3
B
3
A
3
P
3
G
3
G
2:0
S
4
B
4
P
4
G
4
G
3:0
A
4
C
in
G
0
P
0
C
0
C
1
C
2
C
3
C
out
C
4
Note: Carry
propagates
through
And/or
network
MAJ gate
network

CMOS VLSI Design

Slide
19

Carry
-
Ripple PG Diagram

Delay
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
Bit Position
ripple
t

CMOS VLSI Design

Slide
20

Carry
-
Ripple PG Diagram

Delay
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
Bit Position
ripple xor
( 1)
pg AO
t t N t t
   
1
-
bit prop/gen cell

delay of And/OR
in grey cell

Final SUM
bit xor

CMOS VLSI Design

Slide
21

PG Diagram Notation

i:j
i:j
i:k
k-1:j
i:j
i:k
k-1:j
i:j
G
i:k
P
k-1:j
G
k-1:j
G
i:j
P
i:j
P
i:k
G
i:k
G
k-1:j
G
i:j
G
i:j
P
i:j
G
i:j
P
i:j
P
i:k
Black cell
Gray cell
Buffer
Generate
only

Both Gen/Prop

CMOS VLSI Design

Slide
22

Carry
-

Carry
-
ripple is slow through all N stages

Carry
-
skip allows carry to skip over groups of n bits

Decision based on n
-
bit propagate signal

C
in
+
S
4:1
P
4:1
A
4:1
B
4:1
+
S
8:5
P
8:5
A
8:5
B
8:5
+
S
12:9
P
12:9
A
12:9
B
12:9
+
S
16:13
P
16:13
A
16:13
B
16:13
C
out
C
4
1
0
C
8
1
0
C
12
1
0
1
0
Critical path: Generate carry in first bit, then ripple thru
next three bits. Then skip next two four
-
bit stages, then
ripple through last stage.

CMOS VLSI Design

Slide
23

Carry
-
Skip PG Diagram

For k n
-
bit groups (N = nk)

skip
t

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
16:0
CMOS VLSI Design

Slide
24

Carry
-
Skip PG Diagram

For k n
-
bit groups (N = nk)

skip xor
2 1 ( 1)
pg AO
t t n k t t
     
 
 
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
16:0
First, last group ripple

skip thru muxes

CMOS VLSI Design

Slide
25

Variable Group Size

Delay grows as O(sqrt(N))

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
16:0
Smaller groups at first/last

CMOS VLSI Design

Slide
26

Carry
-

Carry
-
i:0
for many bits
in parallel.

Uses higher
-
valency cells with more than two inputs.

C
in
+
S
4:1
G
4:1
P
4:1
A
4:1
B
4:1
+
S
8:5
G
8:5
P
8:5
A
8:5
B
8:5
+
S
12:9
G
12:9
P
12:9
A
12:9
B
12:9
+
S
16:13
G
16:13
P
16:13
A
16:13
B
16:13
C
4
C
8
C
12
C
out
CMOS VLSI Design

Slide
27

CLA PG Diagram

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
16:0
Collecting Generate/Propagate over many cells

CMOS VLSI Design

Slide
28

Higher
-
Valency Cells

i:j
i:k
k-1:l
l-1:m
m-1:j
G
i:k
G
k-1:l
G
l-1:m
G
m-1:j
G
i:j
P
i:j
P
i:k
P
k-1:l
P
l-1:m
P
m-1:j
Just the recursive definition of
Generate

CMOS VLSI Design

Slide
29

Carry
-

Trick for critical paths dependent on late input X

Precompute two possible outputs for X = 0, 1

Select proper output when X arrives

Carry
-
-
bit sums

For both possible carries into n
-
bit group

C
in
+
A
4:1
B
4:1
S
4:1
C
4
+
+
0
1
A
8:5
B
8:5
S
8:5
C
8
+
+
0
1
A
12:9
B
12:9
S
12:9
C
12
+
+
0
1
A
16:13
B
16:13
S
16:13
C
out
0
1
0
1
0
1
CMOS VLSI Design

Slide
30

Carry Select Critical Path

T
select
= T
pg

+ [N+(K
-
2)]T
AO

+ T
mux

N = adder size in each group, K groups

Slightly faster than Carry
-
skip.

For optimal delay, do not want each group to have the
same size, want each group to grow in order to match
mux select arrival time with carry generation time.

CMOS VLSI Design

Slide
31

Carry
-

Factor initial PG and final XOR out of carry
-
select

5:4
6:4
7:4
9:8
10:8
11:8
13:12
14:12
15:12
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
increment
t

CMOS VLSI Design

Slide
32

Carry
-

Factor initial PG and final XOR out of carry
-
select

5:4
6:4
7:4
9:8
10:8
11:8
13:12
14:12
15:12
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0

increment xor
1 ( 1)
pg AO
t t n k t t
     
 
 
Carry
-
select have
redundant
logic, factor
this out,
reduces
logic size,
delay
essentially
the same.

CMOS VLSI Design

Slide
33

Variable Group Size

Also buffer

noncritical

signals

3:2
5:4
6:4
8:7
9:7
12:11
13:11
14:11
15:11
10:7
3:2
5:4
6:4
8:7
9:7
12:11
13:11
14:11
15:11
10:7
6:0
3:0
1:0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
Observe that
so that buffer
delay is not on
critical path!

CMOS VLSI Design

Slide
34

Recursive lookahead gives O(log N) delay

CMOS VLSI Design

Slide
35

Brent
-
Kung

1:0
3:2
5:4
7:6
9:8
11:10
13:12
15:14
3:0
7:4
11:8
15:12
7:0
15:8
11:0
5:0
9:0
13:0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
Lots of logic
levels!

Buffers not really
necessary

CMOS VLSI Design

Slide
36

Sklansky

1:0
2:0
3:0
3:2
5:4
7:6
9:8
11:10
13:12
15:14
6:4
7:4
10:8
11:8
14:12
15:12
12:8
13:8
14:8
15:8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
High Fanout

CMOS VLSI Design

Slide
37

Kogge
-
Stone

1:0
2:1
3:2
4:3
5:4
6:5
7:6
8:7
9:8
10:9
11:10
12:11
13:12
14:13
15:14
3:0
4:1
5:2
6:3
7:4
8:5
9:6
10:7
11:8
12:9
13:10
14:11
15:12
4:0
5:0
6:0
7:0
8:1
9:2
10:3
11:4
12:5
13:6
14:7
15:8
2:0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
Lots
-
o
-
wires

CMOS VLSI Design

Slide
38

Ideal N
-

L

= log N logic levels

Fanout never exceeding 2

No more than one wiring track between levels

-
D taxonomy (
l
,
f
,
t
)

Logic levels:

L

+
l

Fanout:

2
f

+ 1

Wiring tracks:

2
t

Known tree adders sit on plane defined by

l
+
f

+
t

=
L
-
1

CMOS VLSI Design

Slide
39

f
(Fanout)
t
(Wire Tracks)
l
(Logic Levels)
0 (2)
1 (3)
2 (5)
3 (9)
0 (4)
1 (5)
2 (6)
3 (8)
2 (4)
1 (2)
0 (1)
3 (7)
CMOS VLSI Design

Slide
40

f
(Fanout)
t
(Wire Tracks)
l
(Logic Levels)
0 (2)
1 (3)
2 (5)
3 (9)
0 (4)
1 (5)
2 (6)
3 (8)
2 (4)
1 (2)
0 (1)
3 (7)
Kogge-Stone
Brent-Kung
Sklansky
Logic
levels

Wire tracks

Fanout

CMOS VLSI Design

Slide
41

Han
-
Carlson

1:0
3:2
5:4
7:6
9:8
11:10
13:12
15:14
3:0
5:2
7:4
9:6
11:8
13:10
15:12
5:0
7:0
9:2
11:4
13:6
15:8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
CMOS VLSI Design

Slide
42

Knowles [2, 1, 1, 1]

1:0
2:1
3:2
4:3
5:4
6:5
7:6
8:7
9:8
10:9
11:10
12:11
13:12
14:13
15:14
3:0
4:1
5:2
6:3
7:4
8:5
9:6
10:7
11:8
12:9
13:10
14:11
15:12
4:0
5:0
6:0
7:0
8:1
9:2
10:3
11:4
12:5
13:6
14:7
15:8
2:0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
Half the wires at last stage than Kogge
-
Stone, but double

CMOS VLSI Design

Slide
43

-
Fischer

1:0
3:2
5:4
7:6
9:8
11:10
13:12
3:0
7:4
11:8
15:12
5:0
7:0
13:8
15:8
15:14
15:8
13:0
11:0
9:0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
CMOS VLSI Design

Slide
44

Taxonomy Revisited

f
(Fanout)
t
(Wire Tracks)
l
(Logic Levels)
0 (2)
1 (3)
2 (5)
3 (9)
0 (4)
1 (5)
2 (6)
3 (8)
2 (4)
1 (2)
0 (1)
3 (7)
Kogge-
Stone
Sklansky
Brent-
Kung
Han-
Carlson
Knowles
[2,1,1,1]
Knowles
[4,2,1,1]
Fischer
Han-
Carlson
Fischer
New
(1,1,1)
(c) Kogge-Stone
1:0
2:1
3:2
4:3
5:4
6:5
7:6
8:7
9:8
10:9
11:10
12:11
13:12
14:13
15:14
3:0
4:1
5:2
6:3
7:4
8:5
9:6
10:7
11:8
12:9
13:10
14:11
15:12
4:0
5:0
6:0
7:0
8:1
9:2
10:3
11:4
12:5
13:6
14:7
15:8
2:0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
(e) Knowles [2,1,1,1]
1:0
2:1
3:2
4:3
5:4
6:5
7:6
8:7
9:8
10:9
11:10
12:11
13:12
14:13
15:14
3:0
4:1
5:2
6:3
7:4
8:5
9:6
10:7
11:8
12:9
13:10
14:11
15:12
4:0
5:0
6:0
7:0
8:1
9:2
10:3
11:4
12:5
13:6
14:7
15:8
2:0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
(b) Sklansky
1:0
2:0
3:0
3:2
5:4
7:6
9:8
11:10
13:12
15:14
6:4
7:4
10:8
11:8
14:12
15:12
12:8
13:8
14:8
15:8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
1:0
3:2
5:4
7:6
9:8
11:10
13:12
3:0
7:4
11:8
15:12
5:0
7:0
13:8
15:8
15:14
15:8
13:0
11:0
9:0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
(a) Brent-Kung
1:0
3:2
5:4
7:6
9:8
11:10
13:12
15:14
3:0
7:4
11:8
15:12
7:0
15:8
11:0
5:0
9:0
13:0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
1:0
3:2
5:4
7:6
9:8
11:10
13:12
15:14
3:0
5:2
7:4
9:6
11:8
13:10
15:12
5:0
7:0
9:2
11:4
13:6
15:8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15:0
14:0
13:0
12:0
11:0
10:0
9:0
8:0
7:0
6:0
5:0
4:0
3:0
2:0
1:0
0:0
(d) Han-Carlson
CMOS VLSI Design

Slide
45

Hybrid Tree/Carry Select

-
logic to compute the carries,
but also use short ripple chains to reduce the
number of gates

Fig 10.39 of the book shows a good example of a

CMOS VLSI Design

Slide
46

Summary

Architecture

Classification

Logic
Levels

Max
Fanout

Tracks

Cells

Carry
-
Ripple

N
-
1

1

1

N

Carry
-
Skip n=4

N/4 + 5

2

1

1.25N

Carry
-
Inc. n=4

N/4 + 2

4

1

2N

Brent
-
Kung

(L
-
1, 0, 0)

2log
2
N

1

2

1

2N

Sklansky

(0, L
-
1, 0)

log
2
N

N/2 + 1

1

0.5 Nlog
2
N

Kogge
-
Stone

(0, 0, L
-
1)

log
2
N

2

N/2

Nlog
2
N