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maliciousgunSoftware and s/w Development

Oct 29, 2013 (4 years and 8 months ago)


December 28, 2006

Analyst Gary Smith: top 10 EDA topics for 2007

SANTA CRUZ, Calif. — Veteran EDA analyst Gary Smith, founder and chief analyst of Gary Smith EDA,
has provided a
"top ten list" of hot topics for electronic design in 2007. Smith was Gartner Dataquest's chief EDA analyst until that firm
suddenly closed its CAD research group
in October 2006. The top ten topics, with explanations by Smith, follow. Smith
noted that they aren't in any particular order of importance, and that the most significant, in fact, is number ten (multicore
1. Electronic design — surviving the inflection point.
Smith has been talking about an "inflection point" in EDA, driven by the move to electronic system level (ESL) design, for
some time. This inflection point is compounded by the requirements of design for manufacturability (DFM) in the IC
physical design flow, Smith said. It's similar to the late 1980's, Smith said, when there was a move to RTL design and
synthesis, and Cadence Design Systems came out with the next generation of IC CAD tools.
2. ESL — moving from a semiconductor design-driven market to an embedded FPGA/microprocessor design
driven market.
There are three groups of designers using ESL tools, Smith said — system-on-chip (SoC) designers, system designers,
and "strictly embedded guys." The system designers, he said, are starting to use FPGAs in conjunction with
microcontrollers. "It looks like the semiconductor group may account for only 22 percent of revenues," Smith said. "If the
market really takes off, the main players are going to be the embedded designers. Otherwise there's going to be a 50-50
split between embedded and system designers."
3. DFM/DFY — is the real DFM emerging?
Smith said that Clear Shape Technologies, which introduced its InShape and OutPerform offerings in November,
offering the first real DFM tool. "It's the first one targeted for the designer," Smith said. "All the rest have been post-
GDSII tools." Design for yield (DFY), Smith noted, is a post-GDSII exercise aimed at changes that might help improve
4. Second generation SoC — it's the software, stupid
In a presentation at the Design Automation Conference
in July, Smith emphasized that the biggest problem with SoC
design is embedded software development, telling the audience that "it's the software, stupid." Now, said Smith, the
message has come back to the semiconductor and ASSP companies that reference designs must include software.
"What we've seen is that the ASSP and ASIC
guys are hiring more software
engineers than hardware engineers," he
said. "They're waking up to the problem."
5. IP usage — will we ever reach the 80-90 percent die area goal?
"When we first started looking at IP [intellectual property] in the late 1990s, the idea was that IP was going to take up 80
to 90 percent of the die," Smith said. "We have been sort of stuck between 55 and 70 percent of the die area for the last
four years." What might break that bottleneck, he said, is that fabless semiconductor companies are starting to get into
the IP market. "That makes a lot of sense, and could be the answer to getting a lot more IP on the die," Smith said.
6. Analog/RF — will a new large company emerge to drive the transition to the new analog/custom design
It's a possibility, Smith said, but such a company would have to enable designs to start at the register-transfer level, so
that analog design becomes available to the ASIC designer. Right now, Smith said, "you don't have the automated
physical design you need, and you don't have the gate-level netlist that would allow the move to RTL." Analog

"synthesis" tools that have emerged so far are really target compilers, he said.
By Richard Goering
7. ASIC design — globalization is not longer just adding China and India to the existing ASIC design regions.
"All of a sudden designs are coming from everywhere," Smith said. "South Africa, Brazil, Bulgaria, Romania, Armenia —
we're seeing designs come throughout the world, and the Internet allows this explosion of designs to happen. How are
the semiconductor companies going to handle that? The web might have caused it, but I don't see the web as the
answer. You still need bodies in place."
8. FPGAs — FPGAs come of age as a system development platform.
There are two trends involving FPGAs, Smith said. The first is that FPGAs have become so large that they can
accommodate complete systems. The second is that FPGA design has become a major market for ESL tools.
9. Outsourcing — outsourcing and the design value chain; be careful, be very very careful.
The issue here isn't globalization, Smith said — it's about sending designs out to consulting houses, and what happens
to intellectual property rights. "The law is not super clear, but the indications are that if you do a design with a consulting
house, and certainly if you do one offshore, the consulting house has the same rights to the design that you do," he said.
potential result: you lose control over the IP, you don't have in-house engineering expertise, and the consulting house
comes back to compete with you.
10. Multicore designs — Moore and Von Neumann part company.
It may be tenth on the list, but it's the most important trend of all, Smith said. The issue with homogenous multicore
designs, he said, is that "the general purpose computer
is in jeopardy. You can probably only do four processors before
parallelism runs out of steam." That's leading to application-specific servers, such as Sun's Niagara.
"Do we solve our
problems with application-specific computers or do we find our way around general-purpose computing?" Smith asked.
"That's where the software guys are saying, we really need to move away from C
and use a concurrent language."
With heterogeneous multicore devices, Smith said, "we're using padded cell technology. You take the engine for a cell
phone and you put it on chip
and you isolate it, and then you take the web browser
and separate it from everything else.
The Japanese have made various efforts to combine applications intelligently on an SoC, but you just don't have the
software tools to do it, and the C language doesn't easily allow concurrent design."
With the exception of Green Hills Software, which is offering debuggers for multiple processors, the software providers
are "oblivious" to the heterogeneous multicore problem, Smith said. "That could cause a significant disruption of the
entire electronics market," he said. "Without solving the concurrent problem, about all we can do is build more padded
cell designs or just dump a lot of memory
on it. Sophisticated designs will come to a halt."

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