Scaling Issue
s
for
VLSI Implementation
s
of
Biologica
l
ly
Accurate
Neuron
s
and
Central Pattern Generator
s
Daniel DeBolt
Electrical and Computer Engineering
Northeastern University
Boston, Massachusetts
ddebolt@ece.neu.edu
Yong

Bin Kim
Electrical and Computer Engineering
Northeastern University
Boston, Massachusetts
ybk@ece.neu.edu
Joseph Ayers
Marine Science Center
Northeastern University
Nahant, Massachusetts
lobster@neu.edu
Abstract
—
Research on the biomimetic c
ontrol of robot
s has
been recently progressing
. This approach allows lifelike and
robust movement by mimicking the control mechanisms of
rhythmic motions seen in behaving animals. Adapting these
control models to micro

robots presents challenges. Operating
nano

scale CMOS circuits at biologically appropriate
frequencies is challenging in analog designs due primarily to
capacitor sizing limitations. An analysis of the limitations of low

power neural models is given and future alternative solutions to
this pr
oblem are suggested for the creation of CPGs in low
power CMOS circuits for micro

robotic control.
I.
I
NTRODUCTION
The rhythmic behavior of animals is mediated by central
pattern generator (CPG) circuits i
n the central nervous system
[1
]. A CPG is a network o
f neurons and synapses that controls
the underlying patterns of walking, swimming, breathing and
other motor functions [2]. These patterns can be generated in
the absence of sensory feedback and patterned neuronal input
from the brain [3]. The biological m
echanisms are limited to
endogenous pacemaker, half center, recurrent cyclic inhibition
and bursting eletrotonic syncitial models [4]. Invertebrate
CPG networks are relatively simple and technically accessible
in vitro
and thus subject t
o detailed cellular
analysis [5
].
A.
Central Pattern Generators in Robotics
Utilizing central pattern generators for control of robotic
locomotion has been an active research topic [6]. Mim
icking
the locomotion of animal
models allows a robot to robustly
deal with obstacles and
collisions in a rapidly changing
environment [7]. Researchers have created several iterations
of CPG based Lobster and Lamprey robots for aquatic mine
and object detection [8][9]. Neuromorphic sensors were used
as inputs and nitinol wires were used as art
ificial muscles
which could be controlled similarly to the way live muscles
are in natural organisms [10]. The above mentioned examples
share a similar control method: a high level finite state
machine sending commands to various CPGs for locomotion.
B.
The
Cyberplasm Research
This paper investigates the scaling issues about
biologically accurate neurons and central pattern generation
for the Cyberplasm program that is an effort to apply
principles of synthetic biology to the development of
biomimetic micro

r
obots through a collaboration of specialists
at several institutions
[
11
]
. The robot will use synthetic
muscles that have channelrhodopsin genes inserted to render
them sensitive to blue light, grown on an organic LED to
mediate excitation/contraction coup
ling. Engineered sensor
cells responsive to rampamiacin or light will guide locomotion
direction and behavior. An analog CPG network will act as the
central nervous system while a chemical
b
attery powers the
entire robot.
Figure 1.
Figure 1.
Diagram of the Cyberp
lasm robot. A:Synthic muscles,
B:Electronic Nervous System CPG, C:Environment sensors, D:Battery, E:
Kapton chassis.
II.
N
EURAL
M
ODELS
A.
Overview and Lower Order Models
The goal of the present work is to form a micro central
pattern generator for swimming [9]. O
ur alternatives are to
form a CPG of computed neurons, or to utilize a CPG based
on aVLSI analog computer based on nonlinear dynamical
models of bursting neurons [
12
].
Izhikevich outlines in [
13
]
the differences between various neural models
and the 20
ide
ntified firing outputs of each
model
. The simplest model is
the one dimension
al “Integrate and Fire” model.
A number of
currents charge and discharge a capacitor to obtain the
integrat
ed output voltage. The firing and
resetting of the
neuron occurs when a
certain threshold voltage
, V
th
is reached.
The current voltage equation
of a capacitor
is shown in (
1
)
while a leaky integrate and fire models equation is shown in
(
2
).
Parameter
u
is the
leakage coefficient.
(
)
This project was supported
by the US Nation
al Science Foundation under
g
rant CBET

0943345
B.
The Hindmarsh

Rose Neural Model
The “Hindmarsh

Rose” neural model describes the action
potential of a biological realistic neuron. This mo
del consists
of three coupled differential equations, one of which models
the membrane potential (x) with the other two considered as
the spiking (recovery current, y) and bursting (ada
ption
current, z) variables
[
1
4
]. The addition of a fourth equation
models even slower calcium exchange dynamics which give
rise to increased regions of chaoti
c operation
and is covered in
[15
].
Figure 2 is an example of output of the HR neural
equations when I=3.024 given in (3

5).
(
(
)
)
TABLE I.
H
INDMARSH
R
OSE
C
OEFFICIENTS
a
b
c
d
e
1
3
1
0.99
1.01
f
µ
S
h
I
5.0128
0.0021
3.966
1.605
0

3.024
This model has been constructed util
i
zing discrete
components in [15] and proposed in CMOS [16
]. An
alternative com
p
uted method using a discrete time two

dimensional map obtains similar dynamics to the Hindmarsh

Rose model and is the basis o
f our macro swimming robot [9
]
.
The model in its simplest form uses only 3 multiplies and 5
additions per update wh
ich is computationally simpler than
numerical integration of the differential equations listed
previously
[17
]
. This allows map based neurons to be
massively scaled on simple hardware. Another advantage is
that highly complex maps require annealing of the
synaptic
weights which can be done ea
sily in software [12
].
Figure 2.
Matlab simulation of t
he Hindmarsh Rose neuron with I
=3.024
III.
S
CALLING
C
HALLENGES
A.
Capacitor Sizing and Time Scales
Time scales seen in neurobiology are much slower than
those seen in most CMOS app
lications. Burst
length
times are
on the order of 0.3
–
10.0
seconds are common while fast
spiking neurons are on the order of
1
–
10
milliseconds [
18
].
A
capacitor is used to store the state variable
in analog designs
.
The speed at which this capacitor charges and discharges sets
the neurons overall output time constant. A 1 pF capacitor
being charged by a 10 nA current charges to 1 V in 0.0001
seconds, much faster than the desired spike frequency.
Reference [
19
] creat
es a spiking neuron in CMOS at a realistic
output frequency of 33 Hz. This was accomplished using
subthreshold operation and
by
locating the state capacitor off

chip. This allows a larger capacitor to be used than what is
available (and costly in terms of
area) in standard CMOS
process.
Many proposed CPG models simply operate too fast to
control an electromechanical system such
as a micro

robot.
For example, a
CPG circuit for rhy
thmic chewing is proposed
in [20
]. The time between chewing is shown to be 0.2
µS
; this
is orders of magnitude faster than its biological equivalent due
in part to the sizing of th
e 60 pF capacitor. Reference [21
]
proposes a neuron based on the Izhikevich model. The burst
length reported is on the order of a few microseconds
,
which
is much faster than the hundreds of milliseconds of its
biological counterpart. This increase in speed is suitable for
computational neural networks such as machine vision or
learning but operates too quickly for operation of a physical
electromechanical d
evice. It is evident that capacitor sizing is
the main limiting factor for biologically accurate analog
CMOS implementations.
B.
Analog Computer Scaling
The Hindmarsh

Rose implementations in [
15] and [16
] are
both based on the principles of analog computers a
nd solve the
coupled differential equations using integration. The basic
building blocks of analog computers are summing junctions
and integrators constructed
with operational amplifiers [22
].
Figure 3 and equation (6) show an integrator op

amp
configurati
on and governing equation; V
o
is the initial state
voltage of the system.
Figure 3.
A standard operational amplifier based integrator.
∫
A particular challenge of designing analog computers was
insuring
the solution did not saturate any op

amps to the
supply rails and a solution was found in a timely manner. For
example, solving problems that use large values or long time
periods such as predator

prey models require scaling of the
equations to be solved w
ithin the limits of an analog
computer. There are two types of scaling
;
one is
output
magnitude
scaling
and
the other
is
time
scaling
. Scaling is
accomplished by replacing a variable with a coefficient and
new representation variable [22
].
Plugging in
t=T/
T
s
and
x=X∙x
m
(similarly for
variables
y and z)
into (3

5
)
yields
the
magnitude and time scaled HR equations (7

9)
.
Values less
than one reduce the magnitudes or time scale, the opposite for
values greater than one.
(
)
(
)
(
(
(
)
)
)
Looking at equations (8) the only coefficient in front of the
Y variable is 1/Ts, this allows a simple explanation of the RC
ratio
issue. Implementing this single term using the op

amp
integrator
,
shown in figure 3
,
yields the ratio shown in (10). If
C=1pF and T
s
=2.2E

3
,
R must be 2.2 G
Ω but only
5 MΩ if
T
s
=5E

6.
The heavier the time scaling,
the
more reasonable
RC ratios
become
but
at the expense of not running at
biological speeds.
Figure 4.
Comparasion of time scaling factors, the first with no scaling,
seco
n
d set to the scaling used in [15
], the third
set to that used in [16
].
Implementation [16
] is operating
roughly 400 times faster
than [
15
] due completely to the time scaling involved. This is
another limitation of capacitors sizing in CMOS. Because the
capacitor was fixed to 3 pF, the time had to be scaled heavily
to make the resistor inputs to the integrato
r reasonable to
implement (in the range of a few mega

ohms). This limitation
is not seen in the discrete component version as leaded
ceramic capacitors come in a large range of values
.
Figure 4
outlines the difference between the given implementations
.
IV.
F
UTURE
R
ESEARCH
D
IRECTIONS
A.
Ulitizing Lower Order Models and Oscillators
Actual swimming systems involve multiple CPGs in
several body segments. The CPGs on the two sides of the
midline are typically coordinated among themselves by
reciprocal inhibitory con
nections to generate a rigid
antagonistic oscillation while adjacent segments on the same
side exhibit a phase delay that varies wit
h period [9].
This
simplifies the creation of complex patterns by loosely
following the pacemaker model using simple voltage
controlled oscillators
and phase delay oscillators
. Integrate and
fire neurons will be inhibited by these oscillators and sensors
acts as the excitatory inputs. The DC av
e
rage is taken as the
output [23
]. Figure 5 shows the possible layout for a simple
swimming pattern generator. Neurons A

D are inhibited
(shown as
a
bubble at the inputs) by the oscillator. The phase
delay propagates the motion down the spine of the robot. Not
shown are
the
environmental inputs from sensors to speed up /
slow down neuron
spiking thus altering the DC output.
Figure 5.
An oscillator example for a simple swimming pattern
generator
.
B.
Model Simplification
A novel approach to implementation of the Hindmarsh
Rose neuron equa
t
ions in CMOS was proposed by [24
]. The
group performed an in

de
pth analysis of 2D and 3D neuron
bursting structure and proposed a method to simplify the
i
mplementation of the HR neuron.
Modeling of a 2D neuron
in CMOS was accomplished with two types of voltage to
current loads. One was a current output Schmitt trigger
and
the other was a quadratic load, both of which charge a
capacitor. This structure represents the x and y variables in the
original equations and only requires a single capacitor. The z
or adaption term was implemented with an integrator circuit.
Anothe
r advantage is that the capacitors all have a common
connection for easier off

chip placement.
Also because there is
more control over the currents involved, deep subthreshold
design can reduce the size of capacitances needed by
operating in the low nano

a
mp regime.
Figure 6 shows the
Simulink model while figure 7 compares the model to solved
HR equations at differing inputs.
The
updating and
implementing
in low voltage CMOS
is currently
being
investigated.
Figure 6.
Simulink simulation of
the updated model propose
d in [24
].
Figure 7.
Comparasion of numericaly solved HR equations to the
simulation
model shown in figure
6
for severial inputs.
V.
C
ONCLUSION
A general introduction to neural models and CPG control
being used in robotics is presented. Behavioral time constants
can be quite long and therefore require the use of large
capacitors. This temporal scaling aspect is often overlooked in
many papers in l
iterature but is important for accurate
locomotion control. Utilizing analog computers to solve
differential equations also requires scaling in magnitude and
time. The small capacitances allowed in CMOS limit the
application to fast running neurons unless
they are placed off
chip. Reduced order oscillators and models are the future
direction as subthreshold design can be employed to possibly
reduce the capacitance sizes needed
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