Design and Microcontroller Implementation of a Three Phase SCR Power Converter

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Nov 15, 2013 (3 years and 11 months ago)

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Design and Microcontroller Implementation of a Three Phase SCR Power Co
n
verter


Richard W. Wall

Herbert L. Hess

Department of Electrical Enginee
r
ing

University of Idaho

Department of Electrical Enginee
r
ing

University of Idaho

Boise, ID 83712

Moscow, ID 8
3844



Abstract
-
A single processor controls a three phase silicon co
n-
trolled rectifier (SCR) power converter. An inexpensive, dual o
p
to
i-
solator interface to the power line provides noise rejection and an
improved measure of the zero crossing. A dynamic
digital phase
-
locked loop (PLL) algorithm implemented in an Intel 87C196KD
-
20 processor achieves frequency tracking, dynamically changing
characteristics for improved performance. Dynamically modifying
the PLL characteristics permits independent capture
and locked
dynamics. A feedforward method provides command trac
k
ing for
improved response without loss of performance. This three
-
component design (processor, optoisolator, and SCR gate drivers)
represents a minimal implementation with potential for closed

loop
voltage and current control. High speed input and output resources
included on the 87C196KD processor make an efficient single
-
device implementation possible. The processor is less than 1%
utilized allowing for additional functions to be added in t
he future.
This system operates on both 50 Hz and 60 Hz power systems wit
h-
out modification or loss of perfor
m
ance.

I. INTRODUCTION


The Phase Controlled Rectifier, employing Silicon Co
n-
trolled Rectifier (SCR) devices, is a reliable technology
common to a
host of electric machine drives, High Voltage
Direct Current (HVDC) systems, and other power conve
r
sion
systems. Though the rectifier has been employed for a very
long time, it has been continuously improved.[1] For exa
m-
ple, to solve a harmonic instabil
ity problem, in which firing
instants determined directly from voltage zero cros
s
ings b
e-
come susceptible to line noise, Ainsworth proposed using a
Phase
-
Locked Loop.[2] Several improvements on his idea
followed, including digital implementations of his al
g
o-
rithm[3
-
5] and sophisticated control and optimizing tec
h-
niques.[6,7] Control of delay or extinction angles, cu
r
rent
regulation, and other functions common to outer control
loops became possible. Simple, reliable gate drives for i
n
te
r-
facing logic to pow
er devices enhanced the control of large
amounts of power.[8] Soon microprocessor impl
e
mentation
of rectifier control [9,10] and of an entire HVDC system
were proposed.[11] Much of the recent research has i
m-
proved upon the less desirable aspects of a con
trolled re
c
tif
i-
er, for example, its input current harmonic behavior[12], di
s-
placement factor[13], effects of dc ripple[14], its topology
and commutation[15], minimizing its hardware[16], and o
p-
timizing its control[17] and losses[18]. Usually these i
m-
prove
ments come through pulse width modulation (PWM)
techniques and advanced power devices, such as the Insula
t-
ed Gate Bipolar Transistor (IGBT).[13
-
15,17
-
21] Quite s
o-
phisticated controllers, such as digital signal proce
s
sors[18,
21], neural networks[22], and
other hardware have also been
proposed. In this paper, the phase controlled t
o
pology, with
its economical silicon controlled rectifiers, is retained and its
control implemented through innovative analog and digital
signal pro
c
essing.


Recently, advances i
n microcontroller technology have
led to self
-
contained systems capable of performing much
more than mere computation. Peripheral tasks so necessary
to high speed, real time control can now be incorporated with
a microprocessor onto a single controller ch
ip. These include
high speed data collection, analog
-
to
-
digital data conversion,
timing (including sampling rates), multiplexing, and high
speed output of digital data. Microcontrollers perform such
high speed control functions plus microproce
s
sor comput
a-
tion at reasonable cost and as an easily inte
r
faced part of a
larger control sy
s
tem.[12]


In this paper, a microcontroller application to a phase
controlled rectifier is reported. Optoisolators digitize the
voltage polarity and the microcontroller digitiz
es the voltage
zero crossing time using high speed inputs, mitigating some
of the effect of line noise. On
-
board timers control sampling
rates and delay times. Though interface signals to an outer
loop may be the product of sophisticated control algorithm
s,
they are intentionally kept simple in this particular invest
i
g
a-
tion to keep the focus on the microcontroller’s impl
e
ment
a-
tion of an all digital PLL and gate signal generator. The r
e-
sult is a low cost implementation of a three phase SCR power
converter.

II. HARDWARE REQUIR
E
MENTS


The general hardware requirements for this impleme
n
t
a-
tion are shown in Fig. 1. Since the 87C196KD
-
20 proce
s
sor
has sufficient internal Read
-
Only Memory (ROM) and Ra
n-
dom Access Memory (RAM), no other digital electro
n
ics are
neces
sary. The total cost for the electronic parts is less than
$50! For prototype development, the power circuits are
mounted on a separate PC board and connected to an MCS
-
96 board via a 40 pin ribbon wire cable. (The MCS
-
96 board
is one of the Intel evalua
tion boards for this family of micr
o-
controllers.) The processor generates the digital signals for
the gate drive circuit. A 386
-
based host PC d
e
velopment
platform uses a serial interface to manage the MCS
-
96 board
with the ECM96 monitor software. A sep
a
rate AC power
supply is required for the MCS
-
96 board.


2


The 87C196KD microcontroller is one of a family of pr
o-
cessors which has on
-
chip resources that allow efficient
phase
-
locked loop (PLL) implementation.[12] The two most
critical resources for this des
ign are high speed outputs
(HSO) and high speed inputs (HSI). Output resources allow
up to eight independent events to be scheduled based upon
one of two timers with a maximum time resolution of 0.8

s
for a 87C196KD operating at 20 MHz. These events incl
ude
setting output pins high or low. High speed input allows the
relative time of specific events on input pins to be captured.
The time resolution is the same for output and input events.
These two processor resources allow for a minimal impl
e-
mentatio
n of a three phase power converter: high speed i
n
put
and output capabilities are not generally available on lower
performance microcontrollers.

Phase A
Phase B
Phase C
High Speed Outputs
High Speed
Inputs
RUN -
STOP
Increase
Delay
Decrease
Delay
ON/OFF
Indication
Converter
Power
Load
Output
SCR Gate Dri vers
i80C196KD uP
S1
S3
S5
S4
S6
S2
H11L1QT
Opto-
isolator

Fig.
1
. Simplified schematic diagram for an i87C196KD co
ntrolled
power converter
.



III. DESCRIPTION OF I/O


Two classes of inputs for this system are the real
-
time
instrumentation and the user control interface. As shown in
Fig. 1, the phase instrumentation hardware consists of two
H11L1QT optoisolators conn
ected to two of the processor’s
input pins. The user control consists of three inputs: RUN
-
STOP, INCREASE DELAY, and DECREASE DELAY.
These inputs are push buttons connected to the processor
input/output (I/O) port 2 pins. Outputs generated by the m
i-
croco
ntroller are for user display and real
-
time control. An
LED indicator on a processor output pin shows when the
program is operating in phase lock and generating pulses to
the SCR gates. The signals used to control the SCR firing
sequence are generated wi
th six output pins, one for each
SCR gate. The INCREASE DELAY or DECREASE D
E
LAY

buttons simulate the commands normally generated by an
outer control loop. Direct input of DELAY commands is
possible but was not done for reasons relating to the env
i-
ronment
in which the particular rectifier at hand will be
placed.

IV. PHASE DETECTION


The first step in implementing a phase locked loop based
control is to establish a reference phase for timing of the
power device’s gate pulses. In order to determine the phase

of the input signal, it is necessary to repeatedly and reliably
determine a fixed point on the sine wave. One of the more
readily identifiable points is either the positive or negative
zero crossing. The implementation used in this design ident
i-
fies two

points on the sine wave: the first just before the pos
i-
tive going zero crossing and the second just after the same
zero cros
s
ing.


Using two optoisolators, one can compensate for vari
a-
tions in level sensitivity and switching time delays. Co
n
stant
frequ
ency (60 Hz input) makes delays due to switching time
indistinguishable from delays due to threshhold levels. The
processor is programmed to capture the time of the i
n
ternal
16 bit, 2.5 MHz clock at the rising edge of the
Neg
a
tive
-
On
optoisolator output a
nd at the falling edge of the
Positive
-
On
optoisolator output. The true zero crossing is computed by
linear interpolation between the sampled
Negative
-
On
going
high value and the sampled
Positive
-
On
going low value.
Fig. 2 shows that this method results
in an improved degree
of accuracy. The
Est. Zero

shown in Fig. 2 is computed
from the phase
-
locked loop algorithm that estimates the next
zero crossing time. This algorithm is discussed in greater
detail in Section VI.

-0.5
0
0.5
-6
-4
-2
0
2
4
6
Input Sine Signal
-0.5
0
0.5
-6
-4
-2
0
2
4
6
Negative On
Positive On
Est. Zero
Time - ms
Volts

Fi
g.
2
. Oscilloscope capture of the sine wave signal, optoisolator
outputs and computed zero crossing.


Using optoisolators provides electrical isolation and si
g-
nal conditioning. This method eliminates the need for signal
transform
ers and comparators to convert the 60 Hz AC power

signal to a suitable level and to provide a fast trans
i
tion at the
zero cros
s
ing.


3

V. PHASE FILTERING



Most amplitude phase detection schemes, including thoes
described above, are subject to errors from pow
er sy
s
tem
harmonics and random amplitude noise. Power system ha
r-
monics are the predominant cause of premature or d
e
layed
zero crossing detection. Random noise may also cause mu
l-
tiple zero crossings.

The dual optoisolator method can effe
c-
tively reject noi
se which generates multiple zero cros
s
ings by
using only the times recorded for a negative trans
i
tion of the
Negative
-
On

followed by a positive transition of the
Positive
-
On

signal. The SPICE model output shown in Figure 3 illu
s-
trates this operation for a

10 kHz signal s
u
perimposed on a
480 Volt RMS AC 60 Hertz signal. This algorithm, as di
s-
cussed in greater detail in Section IV, will compute the zero
crossing at 0.8325 ms, resulting in the computation of 63.15
Hertz to the most recent period. If the zer
o crossing is co
r-
rectly determined for the next period, 57.14 Hertz will then
be computed, correctly compensating but introducing an u
n-
acceptably large deviation between consecutive comput
a-
tions: Amplitude noise used for this illustration results in a
3.0
Hertz frequency measurement error. This requires further
filtering as discussed in the fo
l
lowing paragraph. Additional
noise reduction is acco
m
plished by Schmitt
-
triggered opto
i-
solators which have TTL
-
compatible outputs. The method
works well for a range

of ac inputs but is most accurate for
inputs lacking a phase shift between harmonics and fund
a-
mental and without dc offset. These conditions are common
to every commericial power distribution system. This method
takes advantage of such conditions.


0
0.5
1
1.5
2
- 6
- 4
- 2
0
2
4
6
Negative On
Positive On
Input signal
Time - ms
Volts

Fi
g 3. Optoisolator simulatedd outputs with 10% amplitude noise
at 10 kHz. The input signal is scaled 1/40 for clarity
.



Since the power system frequency is usually quite co
n-
stant, fluctuating at most a tenth of a Hertz under normal o
p-
erating conditions,

bandpass filtering helps to further reduce
sensitivity to noise. Analog filtering the 60 Hz input to r
e-
duce noise and harmonics generates a phase shift; for exa
m-
ple, a second order RLC lowpass filter designed for 7.5 Hertz
cutoff results in 0.55 degrees
phase lag at 60 Hertz. This is
unacceptable, being considered large for the system at hand.
Bandpass analog filtering can achieve zero degree phase shift
but does so at only one frequency by delaying the input signal
one or more integer cycles. Conventio
nal sy
s
tems use a
phase
-
locked loop to track the small variations in frequency
and identify the zero crossing for a phase refe
r
ence.[2] This
synchronous filtering technique is not fr
e
quency dependent
due to its bandpass characteristics. Hence, it does n
ot gene
r-
ate the phase lag and is therefore more effective than lowpass
filtering for reducing measur
e
ment errors in the presence of
harmonic distortion. Ban
d
pass filtering using a phase
-
locked
loop to further reduce sensitivity to the noise described abov
e
is dicsussed in Se
c
tions VI and VII.


VI. SOFTWARE IMPLEMENTATION OF A PHASE
-
LOCKED LOOP


The voltage controlled oscillator (VCO) is the weakest
link in an analog or semi
-
analog phase
-
locked loop.[25]
Changes of supply voltage and temperature affect th
e stabi
l-
ity and operating performance of these phase
-
locked loop
implementations. Both hardware and software all
-
digital
phase
-
locked loop implementations are immune to these
problems. Fig. 3 shows a block diagram of the phase
-
locked
loop algorithm impl
emented in 80C196 assembler code. The
output from this control loop is a predicted zero cros
s
ing,
T
zcn
, as computed from the last predicted zero crossing and a
computed period,
P
d
.

The measured zero crossing,
T
zcm
, is
obtained from the input event algo
rithm described in IV. The
zero crossing error,
T
zce
,

is actually the phase error for the
PLL.

1/z
Error
Period
adjust
n+1
Lowpass
Filter
Divide
by 6
Tcm
Pde
Pd
Pd
Tzc
Pd/6
Tzc
Pd
Predicted next
zero crossing
Tzc
time
n
n
n
0
Measured
zero crossing
time
n
n
n
Period
period
Fixed
bias
Filtered
period
outputs

Fig. 4. Block diagram of a digital PLL implemented in processor
code.



The output from the lowpass filter is an offset level
w
hich, when added to a fixed bias corresponding to a nom
i-
nal period,
P
d0
, generates the synthesized signal with period,
P
d
. Adding a nominal fixed bias to the filter output is a fee
d-
forward technique to reduce the time required for initial ca
p-
ture and for c
apture after relatively large, rapid changes in
nominal period. Nominal bias also reduces windup pro
b-
lems. These advantages are accomplished by reducing the
offset level to which the integrating lowpass filter must in
i-

4

tially ramp up. When lock is achieve
d,
P
d

is “locked” or
synchronized to the input signal in both frequency and phase.


The lowpass filter algorithm is arbitrary and may be tuned
to meet control objectives as will be discussed below. Typ
i-
cally, the loop filter for an analog PLL is a first
order lag
-
lead low pass filter with a transferfunction expressed by (1).
Use of such a filter resuls in steady state error for a step input
and may be warrented for some applications. Appl
i
cations
and effects of higher order loop filters are the subject
of on
-
going investigations.[26] For this particular invest
i
gation, we
have choosen a first order filter based upon a common pr
o-
portional plus integral (PI) algorithm that has the continuous
time Laplace transfer function as shown in (2).[5] The co
m-
plexit
y of the loop filter algorithm is, in a sense, only limited
by processor speed. Using a filter based upon the PI alg
o-
rithm results in loop filter with a transfer function as e
x-
pressed in (2). The discrete transfer function for the PI alg
o-
rithm described b
y (3) is derived from (2) using the bilinear
transform
a
tion.


Although the theoretical steady state error for an analog
PLL using a loop filter with a transfer functions expressed by
(2) is zero, the discrete realization expressed by (3) can result
in fini
te steady state errors due in part to the sampling speed.
The demonstration system has a finite resolution of 0.0172
degrees based upon the 2.5 MHz sampling rate and 60 Hz
nominal frequency. Using 16 bit integer math results in tru
n-
cation error which co
ntribute less significantly to the steady
state errors..


H
s
K
f
s
s
(
)















(1)

H
s
K
p
K
i
s
(
)












(2)

H
z
K
i
T
K
p
K
i
T
K
p
z
z
(
)































2
2
1
1
1


(3)


Although a PLL using the PI algorithm for the loop filter
guarantees zero steady s
tate error for a step input change, its
dynamic behavior can be very different depending upon
choices of integral gain,
K
i
,
and the proportional gain,
K
p
.
Since the sampling interval,
T,

is also the measured period,
the value of
T

used in (3) will chan
ge depending upon the
variance in system frequency. This is usually not a problem
because the power system frequency normally changes less
than a tenth of a Hertz and does so at a typical rate on the
order of hundredths of a Hertz per se
c
ond.



The di
screte transfer function expressed in (4) is for the
phase error,
T
zce
. This transfer function uses the PI lowpass
filter algorithm expressed by (3) while K
a

and K
b

are defined
by
K
i

and
K
p

as shown in (5) and (6). (4) has a zero a

=0
on the unit cir
cle and two poles which must lie inside the
unit circle to insure PLL stability. Adjusting these poles can
attenuate the the higher frequencies making the control loop
less responsive to fast changes of the frequency of the input
signal as well as making

the filter more stable.


T
zce
z
z
K
a
z
K
b







1
2
2
1
(
)
(
)



(4)

K
K
T
K
a
i
p


2










(5)

K
K
T
K
b
i
p


2









(6)


Experimentally, variations in control response are o
b-
served by monitoring the phase error, T
zce
, as shown in Fig.
5.
These plots agree well with simulation results for the fi
l
ter
types using MATLAB. The four cases are generated using
the values of
K
i

and
K
p

shown in Table I with
T

set to 1/60 s.
All four algorithms achieve zero steady state error for a step
change

of the frequency on the input signal thus confirming
earlier observations about the PLL using PI a
l
gorithm for the
loop filter.


TABLE I. Chart of constants used in Fig. 5 simulations.

Type

K
i

K
p

K
a

K
b

A

0.0025

0.5

0.8

-
0.2

B

0.0012

0.7555

0.9

-
0.610

C

0.0006

0.8315

0.9

-
0.763

D

0.00006

0.8925

0.9

-
0.885






-1
0
1
2
3
4
53 Hz
69 Hz
Zero
Crossing
Error - Hz
Filter type "A"
Filter type "B"
Filter type "C"
Filter type "D"
Signal Frequency
Time - seconds

Fig. 5. Four experimental dynamic responses of the phase
-
locked
loop control system shown in Fig. 3 to a step change of input fr
e-
quency of 69 to 53 Hz.


5


A filte
r with slightly underdamped characteristics sim
i
lar
to the “Type B” filter is used for the pre
-
lock lowpass filter to
obtain phase lock quickly, within 0.5 seconds as demonstra
t-
ed by the zero phase error. A similar filter to the “Type D”
filter, with sign
ificantly overdamped characteri
s
tics, is used
after phase lock because this filter rejects higher frequencies
and has a high degree of momentum. Math
e
matically, a crit
i-
cally damped response can be achieved u
s
ing
K
a

= 0.9 and
K
b

=
-
0.6975. As mentioned prev
iously, the power system will
vary by at most 0.1 Hertz from its 60 Hertz nominal value
and these variations occur at a rate of hundredths of Hertz per
second or slower. The noise spe
c
trum is known to exist at
somewhat higher frequencies. Therefore, a fi
lter of the
“Type D” nature, designed for its slow response, rejects the
noise while retaining sufficient bandwidth to effectively track
the desired system frequency. (The feedforward aspect of the
control loop provides a wide bandwidth for the commanded

period, overcoming what may appear as a very sluggish co
n-
trol loop response. Fee
d
forward also overcomes windup
problems.) In other words, this algorithm takes advantage of
known system behavior in applying appropriate filtering.
Hence, frequency measu
r
e
ment noise such as that illustrated
in Fig. 3 does little to change the computed locked period.
The mechanism to achieve the dynamic filter is discussed in
Section VII. An important observation from Table I and
Figure 5 is that lower integral gains r
esult in a slower r
e-
sponding sy
s
tem.


When choosing the PI algorithm constants or even the
order of the lowpass filter algorithm, one must consider the
performance criteria for a given application. This is beyond
the scope of this discussion. The reader
is referred to [6] for
additional information. The processing power of the
87C196KD
-
20 allows implementation of high order lowpass
filter algorithms or li
m
ited change
-
rate algorithms.


VII. PHASE LOCK DETECTOR


When the PLL control system in Fig. 4 h
as obtained
lock, the
Phase error, T
zce
,
is nominally zero. A lock dete
c-
tor is implemented which tracks the sum of squares of the
T
zce

over a finite length window of past values as expressed by
(7). From experimentation, the sum squared term, S
2
, for a
w
indow of 20, is less than 1000 when the system has
achieved phase lock. The pulse generation for the SCR gates
is inhibited unless operating in phase lock. The pro
c
essor
code to implement thic control will be discussed in greater
detail in Se
c
tion IX.


S
Tzce
i
i
n
k
i
n
2
2





(
)










(7)


The lock detection circuit is also used to adjust the p
a-
rameters of the PI loop switching from a fast response alg
o-
rithm before lock is achieved to a slow response algorithm
after becoming locked. During operati
ons, if the lock dete
c-
tion algorithm indicates a loss of lock, the phase
-
locked loop
is switched back to the fast response filter algorithm until
lock is acquired again.

VIII. OUTPUT CONTROL


Fig. 6 illustrates the feedforward method to determine the
SCR
gate firing times. The closed
-
loop portion of Fig. 6 is
described by (8) and the open
-
loop portion by (9). In
i
tially,
the zero phase reference,
T
ref
,

is set to zero phase, T
zcn
,

shown
in Fig. 4.
T
ref

updates after a delay equal to six times
Pd/6

plus the

delay control variable
T
D
.
T
ref


updates using the
most recent value of
Pd

computed in the PLL. Hence
T
ref

and
T
zcn

are both phase
-
locked to the input signal but are not
necessarily equal: The update timing of
T
ref

depends upon
the delay control wher
eas
T
zcn

depends upon the PLL input
signal. The locked period,
Pd
, computed in the PLL contains
the disturbance rejection inform
a
tion.


To obtain command tracking as a separate matter, the
firing times are computed according to (9). The variable,
K,
ser
ves as the HSO output pin sequence table pointer as well
as the multiplier for
Pd/6

in (9).
K

is incremented each
Pd/6

period from zero to five.



T
ref
n
T
ref
n
Pd



1









(8)

T
HSO
K
T
ref
n
K
Pd
T
D




6







(9)

T
Pd
HSO
T
HSO
T
HSO
T
HSO
T
HSO
T
HSO
T
1
2
3
4
5
6
Tref
n



Pd/6

Pd/6

Pd/6

Pd/6

Pd/6
1/z
D

Fig. 6. Control diagram for SCR firing timing.

IX. PROCESSOR SOFTWARE


The 87C196KD processor operates in one of three ro
u-
tines: A main routine containing the processor default code
and two real
-
time interrupts routines shown in Fig. 7 and
Fig. 8. Up
on power up, the code begins execution by setting
all initial conditions and allocating the various microproce
s-
sor resources for this particular application.


6

Clear Start Flag
Start HSO
from ISR
Return
Save
Event
Time
Tzcm
S<=Limit?
Yes
No
No
Start Flag
Set?
Reset
Run & Lock
Flags
Set
Tref=Tzc
Phase Control
S,
Tzc, Pd,
Pd/6
Compute filtered
and
from PLL
algorithm
Compute
zero crossing
time -
Compute
sum squared,
of
Event?
Capture
time
HSI ISR
pos. on
neg. on
Yes
from ISR
Return

Fig. 7. High speed input interrupt service routine flow di
a
gram.



T
wo HSI interrupts are generated per cycle of the power
system voltage and processed to determine the measured zero
crossing as explained in IV. After the second, or
Positive
-
on,

generated interrupt, the measured zero crossing time,
T
zcm,

is calculated,

becoming an input to the the phase filtering
algorithm, explained in V and VI. Three variables set by this
routine for use in the high speed output interrupt service ro
u-
tine are as follows: the zero phase time

T
zc
, the period of the
locked frequency

Pd
,

and the period of a signal correspon
d-
ing to six times the locked frequency

Pd/6
. At the expense of
a few more optoisolators, the sampling inte
r
val could be d
e-
fined as one
-
sixth of a period, with an atte
n
dant improvement
in command tracking. This improve
ment comes at the add
i-
tional expense of a sixfold increase in computation burden
which is still within the microcontro
l
ler's capability as
demonstrated in Section X of this paper. Other methods for
dividing the period are di
s
cussed in [23].


During the
H
SO

interrupt service routine shown in Fig. 8,
the processor determines which outputs are to be set high
during the next sixth of the cycle by retrieving data from two
gate firing sequence tables. Three timed events are sche
d-
uled during the output interru
pt service routine: the first two
events pulse two of the six gate signals high and specify at
what time the events occur. The third event, an arbitrary
fixed delay after the first two events, resets all HSO pins low.
The third event is also programmed
to generate the next
HSO

interrupt thus making the interrupts self perpet
u
ating while
generating gate firing pulses. By disabling HSO interrupts,
this process for generating gate pulses is term
i
nated.


Run Flag
None set
Tref, Pd,
T
and
Compute HSO pin
from firing table
Determine
HSO pin states
high event times
Flags?
HSO ISR
from
Determine HSO pins
from sequence table
Schedule pin high
and pin low events
Pd/6,
from ISR
Return
from ISR
Return
d,

Fig. 8. High speed o
utput interrupt service routine flow di
a
gram.


Only when a signal from the operator first initiates the
generation of the gate firing pulses, the actual zero crossing
time,
T
zc
, is copied into the gate firing reference variable,
T
ref

which subsequently s
tays synchronized with the actual zero
crossing by using the periods,
Pd
and
Pd/6,

computed in the
HSI
interrupt service routine. Although (8) specifies that
T
ref

is incremented by
Pd
, the actual time when this update occurs
may shift forward and back in

relation to the corresponding
actual zero crossing by the amount specified by the operator
for
T
D
, the delay time. Hence, for a negative delay time
T
D
,
T
ref

will update before
T
zc
. Thus it is nece
s
sary to maintain
two zero crossing time references,
T
zc


for the PI algorithm
and
T
ref

for scheduling the gate firing pulses.


7

X. OPERATIONS


Fig. 9 shows the six experimental outputs to the SCR
gates for a zero phase delay. The pulse widths are exagge
r
a
t-
ed for illustrative purposes and are programmable in pr
o
c
e
s-
sor code. The second firing pulse overcomes discontinuous
conduction, for example, at startup, and is ordinarily deleted
in continuous conduction. The range of delay is zero to 52.4
ms or from zero to over 1000 degrees for 60 Hz nominal i
n-
put. The up
per restriction is imposed by the crystal fr
e
que
n-
cy used with the 87C196KD processor and the 16 bit timer
used to schedule output events. Since the delay is i
n
corp
o-
rated on a feedforward command outside the PLL alg
o
rithm,
there are no restrictions on the
size of step in phase delay.
The advantage of a feedforward command for delay is its
improved tracking performance: Any change in the desired
firing angle is implemented in its entirety at the very next
instant that a new command is applied without aff
ec
t
ing the
disturbance reje
c
tion of the PLL.


The waveforms generated by experimental data shown in
Fig. 9 are independent of frequency within the range of 40 to
70 Hz. No changes in code or hardware are required to ope
r-
ate on a 50 Hz power system. The
re is sufficient dynamic
range in the mathematics of the PLL algorithm to accomm
o-
date the period offset to 50 Hz without loss of pe
r
formance.

-20
-10
0
10
20
30
Time - ms
S3
S2
S1
S4
S5
S6
A
B
C
Gate
Pulses
Input
Voltage
Fig. 9. Experimental results of HSO outputs to the SCR gate co
n-
trols for a zero deg
ree phase delay. Dual pulses are for illustration
purposes.


The execution time for the
HSI
interrupt service routine is
less than 40

s and the execution time for the
HSO

inte
r
rupt
service routine is 18

s. This represent a 0.34% util
i
zation.
Fixed poi
nt math was used in the control algorithms with 32
bit precision. The program required 650 bytes of the poss
i-
ble 32K bytes of internal ROM and 75 bytes of the possible
2K bytes of internal RAM. None of the 8 analog input cha
n-
nels were used as well as num
erous other r
e
sources provided
by the 87C196KD processor. In other words, there remains a
great deal of opportunity for incorp
o
rating sophisticated ou
t-
er control loops using the same pro
c
essor.




XI. CONCLUSION


An embedded microcontroller produces a m
inimal parts
implementation of a Phase Controlled Rectifier with phase
-
locked loop
-
based generation of gate signals. Two inexpe
n-
sive optoisolators used for the phase detector reduce instr
u-
mentation requirements. Innovative analog and digital si
g
nal
proces
sing improve the accuracy of the zero crossing time.
Dynamic digital phase
-
locked loop characteristics provide
improved capture and lock performance. A fee
d
forward
method separates disturbance rejection from co
m
mand trac
k-
ing: Rapid, accurate response to
commands o
c
curs while r
e-
jecting a wide range of disturbances, including disturbances
both faster and slower than the command. The flexibility and
simplicity of the processor based design makes this converter
extremely efficient and reliable. The processo
r’s capabilities
will permit expansion of the control algorithms to include, for
example, protective algorithms, closed loop constant voltage
control, or closed loop constant current output control.

XII. BIOGRAPHY

Richard W. Wall born 1946 received his BS
EE from the
Pennsylvania State University (‘68) and MEEE and PhD EE
from the University of Idaho(‘80, ‘89). He worked for Idaho
Power Co. for 18 years in the communications, protective
relaying and R&D departments before joining the University
of Idaho De
partment of Electrical Engineering. He teaches
Embedded Microcontrollers and Senior Design. His r
e
search
interests include protective relaying and networked distri
b
u
t-
ed control.


Herbert L. Hess received his BS from the US Military Aca
d-
emy ('77), MS from

the Massachusetts Institute of Techno
l
o-
gy ('82), and PhD from the University of Wisconsin
-
Madison
('93), where he held a Hertz Fellowship. He served on the
faculty of the US Military Academy from ‘83
-
’88. In ‘93, he
joined the University of Idaho, where

he is an A
s
sistant Pr
o-
fessor of Electrical Engineering. His research interests i
n-
clude analysis, design, and control of electric machines, drive
systems, and power converters and their effects on the quality
of electric power.


XIII. ACKNOWLEDGMENT

This
research was supported in part by a grant from Unive
r
s
i-
ty of Idaho Instructional Media Services entitled "Power
Electronic Converters for Hands
-
on Investigation in the
Classroom."

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