VLSI Design Intended Audience Automation Algorithms

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Jul 18, 2012 (5 years and 3 months ago)

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CS680 : VLSI Design
Intended Audience
Automation Algorithms
• VLSI CAD (also known as EDA – electronic design
automation) students, in particular for chip
implementation (physical design)
Lecture 1 : Introduction
• Circuit designers to understand how tools work
behind the scene
• Process engineers to tune process that is more
circuit/physical design friendly
• Mathematical/Computer Science majors who want to
find tough problems to solve
Shankar Balachandran
– Lots of VLSI physical design problems can be
formulated into combinatorial optimization or
Dept. of CSE, IIT Madras
mathematical programming problems.
shankar@cse.iitm.ac.in
– Actually, most CAD problems are NP-complete ->
heuristics
WHAT IS THIS COURSE ABOUT? Goals
• Computer Aided Design of Integrated Circuits. • Obtain a general understanding of IC design.
– Instead of focusing on design, we look at design of tools for
• Understand the process of VLSI layout design
designing next generation ICs.
• Study the basic algorithms used in layout design of VLSI
• which means we must understand the complexity of designing ICs.
• which also means we must understand formal processes that are involved circuits.
in the IC design.
• Learn about the physical design automation techniques
• and, finally, we must be able to represent and program these processes to
implement tools that can assist us in the IC design.
used in the best-known academic and commercial
– tools are methods and formal steps which can be represented by algorithms.
layout systems.
– algorithms can be programmed.
• Get to know research topics and problems.
– One final word: Even though we do not carry out design, an
understanding of design process, complexity analysis, and ability
to build automation tools gives us an insight that helps us become
better designer.Course Logistics Textbooks & References
• Lecture Hours: R&T Slot (Wed. and Fri. afternoons, • Two text books are recommended
Thur??)
– S. M. Sait and H. Youssef, VLSI Physical Design
Automation: Theory and Practice, World Scientific, 1999.
• Instructor: Shankar Balachandran
– Naveed A. Sherwani, Algorithms for VLSI Physical Design
– Email: shankar@cse.iitm.ac.in
Automation, Kluwer Academic Publishers, 1999.
– Office: BSB 349
• Algorithm book (for your reference)
• Class web page
– T. H. Cormen, C. E. Leiserson, R. L. Rivest, “Introduction
– http://www.cse.iitm.ac.in/~shankar/teaching/cs680/
to Algorithms”, MIT Press, 1999 (2nd edition) (optional)
– Prerequisites
• Selected papers from the literature.
• Basic understanding of algorithms
• Basic understanding of VLSI
• or consent of instructor
Grading Policy Course Outline
• Homework and In-class Quizzes: 10% • Introduction
– Paper and pencil • Partitioning
– Simple 15 min quizzes
• Floorplanning
• Programming Assignments & Project: 50%
• Placement
– 3-4 programming assignments
• Global Routing
• Will span a couple of weeks
• Detailed Routing
– Project assigned in beginning of March
• Clock and Power Routing
– 2 or 3 person teams
• Emerging topics
• Midterm: 35%
– Around end of March
• Another 5% buffer – Against Project or ExamPhysical Design Automation Basic Components In VLSI
Interlock Circuits
Pad Metal1 Via Metal2
Automation Techniques VLSI Physical Design
• Devices
– Transistors
Graph algorithms Partition
– Logic gates and cells
Data Path
Graph algorithms mathematical Placement
– Function blocks
PLA I/O
programming
• Interconnects
Shortest path Routing
– Local signals
ROM/
Mathematical programming
RAM
– Global signals
Greedy algorithm
– Clock signals
Random
A/D
logic
Converter
– Power/ground nets
The most important thing often is to find the right problem formulation
VLSI Design Cycle VLSI Design Cycle
Manual
System Specification
System
Chip
Specification
Automation
Functional Design
X=(AB*CD)+(A+D)+(A(B+C))
• Large number of devices
Y=(A(B+C))+AC+D+A(BC+D))
Logic Design
• Optimization requirements for high performance
• Time-to-market competition Circuit Design
• Power (and other) constraints VLSI Design Cycle (cont.) Physical Design
Physical design converts a circuit description into
a geometric description. This description is used to
manufacture a chip. The physical design cycle
consists of
Physical Design
1 Partitioning
2 Floorplanning and Placement
Fabrication
3 Routing
4 Compaction
Packaging
Physical Design Process Physical Design Cycle
Circuit Design
Physical Design
cutline 1
Design Steps: (a) Partitioning
cutline 2
Partition & Clustering
Floorplan & Placement
Pin Assignment a
Floorplanning
clk
clk (b)
G Gllo ob ba all R Ro ou uttiin ng g &
Detailed Routing clk
Placement
a
Methodology:
a
(c) Routing
Divide-and-Conquer
(d) Compaction
FabricationComplexities of Physical Design History 101 of Physical Design
a More than 100 million transistors
• Born in early 60’s (board layout)
a Performance driven designs
• Passed teenage in 70’s (standard cell place and
a Power-constrained designs
route)
a Time-to-Market
• Entered early adulthood in 80’s (over-the-cell
routing)
Design cycle
• Declared dead in late 80’s !!!
• Found alive and kicking in 90’s
• Physical Design (PD) has become a dominant force
…...
in overall design cycle,
– thanks to the deep submicron scaling
High performance, high cost – expand vertically with logic synthesis and interconnect
optimization, analysis…. => Design closure!
Why Physical Design is still
Moore’s Law
HOT?
• The minimum transistor feature size decreases by 0.7X
• Many existing solutions are still very suboptimal
every three years (Electronics Magazine, Vol. 38, April
– E.g., placement
1965)
• Interconnect dominates
– No physical layout, no accurate interconnect
• Consequences of smaller transistors:
• More new physical and manufacturing effects pop
– Faster transistor switching
up
– Crosstalk noise, … – More transistors per chip
– OPC (manufacturability), etc.
• True for 40+ years!
• More vertical integration needed
• And it will be true in at least another 10 years, but now
• Physical design is the KEY linking step between
is facing lots of red brick walls
higher level planning/optimization and lower level
modeling
– Need smarter and more powerful CAD tools than everTechnology Roadmap: ITRS
Technology Trend and Challenges
2001
Year 2001 2003 2006 2010 2013 2016
Source: Feature size (nm) 130 90 53 32 22 16
ITRS’03
2
Mtrans/cm 38 61 122 309 617 1235
DRAM bits (Gbits) 0.512
1 2 8 32 64
2
Chip size (mm ) 280 280 280 280 280 280
Signal pins / chip 1024 1024 1024 1280 1408 1472
Clock rate (GHz) 1.7 3.1 5.6 11.5 19.3 28.8
Wiring levels 7 8 9 10 10 10
Power supply (V) 1.1
1.0 0.9 0.6 0.5 0.4
• Interconnect determines the overall performance
High-perf power (W) 130 150 180 218 251 288
• In addition: noise, power => Design closure
Battery power (W) 2.4 2.8 3.5 3.0 3.0 3.0
• Furthermore: manufacturability => Manufacturing
closure
How to Manage Design
Major Design Challenges
Complexity
• Ultra-high speeds required by applications like
• Obviously, hand-crafting is not appropriate to design
communications and multimedia.
chips with > million devices.
• Power dissipation and ultra-low voltage design.
• Adhere to rigid design methodologies and strategies.
• Dominance of interconnect, noise, crosstalk issues.
• Use hierarchical approach, design reuse.
• Clock distribution and on-chip timing issues.
• Exploit CAD tools for design automation.
• Systems on a Chip (SoC), integration of logic and
memory, mixed-signal design, …
• Reliability, manufacturability and testing.
• How to manage ever-growing design complexity and
deal with time-to-market.
• Reuse of IP.Design Abstraction Levels Design Domains
• A complex digital system can be subdivided in a
hierarchical manner using abstraction. Internal
details of a complex block at each level is replaced
by a black box or model which contains the
• Hierarchical design
sufficient details to deal with the block at the next
abstraction can be
done in each of the
level of hierarchy.
three design
domains:
– Behavioral
– Structural
– Physical
IC Design Steps (cont.)
Evolution of the EDA Industry
Results
High-level Functional
What’s next?
(design productivity)
Specifications
Description Description
Behavioral
Structural
Synthesis – Cadence, Synopsys
VHDL, C VHDL
Schematic entry – Daisy, Mentor, Valid
Transistor entry – Calma, Computervision, Magic
Effort
(EDA tool effort)
McKinsey S-Curve
[©Keutzer]I/O
PLA
The Big Picture: IC Design
IC Design Steps (cont.)
Methods
C C C Co o o os s s st t t t / / / /
D D D De e e es s s siiiig g g gn n n n Q Q Q Qu u u ua a a alllliiiit t t ty y y y # # # # C C C Co o o om m m mp p p pa a a an n n niiiie e e es s s s
High-level Functional
D De ev ve ello op pm me en nt t
D De ev ve ello op pm me en nt t
M Me et th ho od ds s iin nv vo ollv ve ed d
M Me et th ho od ds s iin nv vo ollv ve ed d
Specifications
Description Description
T T T Tiiiim m m me e e e
Full Custom
S Sy yn ntthheessiiss
S Sy yn ntthheessiiss
P P P Ph hh hy y y yssssiiiiccccaaaallll
T T T Teeeecccch hh hn n n noooolllloooog g g gy y y y
Standard Cell
D D D Deeeessssiiiig g g gn n n n
M M M Maaaappppppppiiiin n n ng g g g
Library Design
Placed
Logic
Gate-level
& Routed
Description
Design
Design
ASIC – Standard
Cell Design
F F F Faaaabbbbrrrriiii----
X=(AB*CD)+
P P P Paaaacccck k k kaaaag g g giiiin n n ng g g g
ccccaaaattttiiiioooon n n n (A+D)+(A(B+C))
Y = (A(B+C)+AC+
RTL-Level Design
D+A(BC+D))
Figs. [©Sherwani]
Full Custom Design Full Custom Design Example
I/O Pad
Structural/RTL Description Component Design
Via
Ctrl
comp
Metal2
Mem Reg Comp. PLA
I/O
File Unit
Metal1
Macro
Place & Route RAM
cell
design
Glue logic
comp
(standard
cell design)
RAM A/D
............
A/D
Floorplan [©Sherwani]
Layouts [© Prentice Hall] [©Sherwani]ASIC (Standard Cell) Design
ASIC Design
Example
Cell Feedthrough
Structural/
VDD GND
Metal1
Metal2
RTL Description HDL Programming
Ctrl
P P P P_ _ _ _IIIIn n n np p p p:::: p p p pr r r ro o o oc c c ce e e es s s ss s s s ( (( (R R R Re e e es s s se e e et tt t,,,, C C C Cllllo o o oc c c ck k k k) )) )
b be eg giin n
b be eg giin n
iiiif ff f ( (( (R R R Re e e es s s se e e et tt t = = = = ''''1 1 1 1'''') )) ) t tt th h h he e e en n n n D C C B
s s s su u u um m m m < < < <= = = = ( (( ( o o o ot tt th h h he e e er r r rs s s s = = = => > > > ''''0 0 0 0'''' ) )) );;;;
Reg Comp.
iiiin n n np p p pu u u ut tt t_ _ _ _n n n nu u u um m m ms s s s_ _ _ _r r r re e e ea a a ad d d d < < < <= = = = ''''0 0 0 0'''';;;;
Mem
File s su um m_ _r re ea ad dy y < <= = ''0 0'';;
Unit s su um m_ _r re ea ad dy y < <= = ''0 0'';;
A C C
a ad dd d8 82 2 :: k ka ad dd d8 8 p po or rt t m ma ap p ((
a ad dd d8 82 2 :: k ka ad dd d8 8 p po or rtt m ma ap p ((
Cell library
a a a a = = = => > > > a a a ad d d dd d d d_ _ _ _iiii1 1 1 1,,,, b b b b = = = => > > > a a a ad d d dd d d d_ _ _ _iiii2 2 2 2,,,,
c c c ciiii = = = => > > > c c c ca a a ar r r rr r r ry y y y,,,, s s s s = = = => > > > s s s su u u um m m m_ _ _ _o o o o) )) );;;;
M M M Mu u u ullllt tt t_ _ _ _iiii1 1 1 1 < < < <= = = = s s s su u u um m m m_ _ _ _o o o o( (( (7 7 7 7 d d d do o o ow w w wn n n nt tt to o o o 0 0 0 0) )) );;;; A B
D C C B
D C D B
C D
A C C
D C D B
Cell library
C C C B
A B
C C C B
C D
Floorplan [©Sherwani]
Roadmap Technology
Roadmap Technology Characteristics (Cont’d)
Characteristics
YEAR OF FIRST PRODUCT SHIPMENT 1997 1999 2002 2005 2008 2011 2014 YEAR OF FIRST PRODUCT SHIPMENT 1997 1999 2002 2005 2008 2011 2014
TECHNOLOGY NODE TECHNOLOGY NODE
250 180 130 100 70 50 35
250 180 130 100 70 50 35
DENSE LINES (DRAM HALF-PITCH) (nm)
DENSE LINES (DRAM HALF-PITCH) (nm)
ISOLATED LINES (MPU GATES) (nm) 200 140 100 70 50 35 25
Chip Frequency (MHz)
Logic (Low-Volume—ASIC)‡
On-chip local clock
750 1250 2100 3500 6000 10000 16903
Usable transistors/cm2 (auto layout) 8M 14M 24M 40M 64M 100M 160M
(high-performance)
Nonrecurring engineering cost
50 25 15 10 5 2.5 1.3 On-chip, across-chip clock
/usable transistor (microcents) 375 1200 1600 2000 2500 3000 3674
(high-performance)
Number of Chip I/Os – Maximum
On-chip, across-chip clock
Chip-to-package (pads)
300 500 700 900 1200 1500 1936
1515 1867 2553 3492 4776 6532 8935
(high-performance ASIC)
(high-performance)
On-chip, across-chip clock
Chip-to-package (pads)
400 600 800 1100 1400 1800 2303
758 934 1277 1747 2386 3268 4470
(cost-performance)
(cost-performance)
Chip-to-board (off-chip) speed
Number of Package Pins/Balls – Maximum
(high-performance, reduced-width, 375 1200 1600 2000 2500 3000 3674
Microprocessor/controller
568 700 957 1309 1791 2449 3350
(cost-performance) multiplexed bus)
ASIC Chip-to-board (off-chip) speed
1136 1400 1915 2619 3581 4898 6700
250 480 885 1035 1285 1540 1878
(high-performance) (high-performance, peripheral buses)
Package cost (cents/pin)
Chip Size (mm2) (@sample/introduction)
0.78-2.71 0.70-2.52 0.60-2.16 0.51-1.85 0.44-1.59 0.38-1.36 0.33-1.17
(cost-performance)
DRAM 280 400 560 790 1120 1580 2240
Power Supply Voltage (V)
Microprocessor 300 340 430 520 620 750 901
Minimum logic Vdd (V) 1.8–2.5 1.5–1.8 1.2–1.5 0.9–1.2 0.6–0.9 0.5–0.6 0.37-0.42
ASIC [max litho field area] 480 800 900 1000 1100 1300 1482
Maximum Power
Lithographic Field Size (mm2) 22 x 22 25 x 32 25 x 36 25 x 40 25 x 44 25 x 52 25 x 59
High-performance with heat sink (W) 70 90 130 160 170 175 183
484 800 900 1000 1100 1300 1482
Battery (W)—(Hand-held) 1.2 1.4 2 2.4 2.8 3.2 3.7
Maximum Number Wiring Levels 6 6–7 7 7–8 8–9 9 10“The Design Productivity Gap”
S So ou ur rc ce e: : S SE EM MAT ATE ECH CH