Final Year Project

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Nov 24, 2013 (3 years and 8 months ago)

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Final Year Project


Progress Report


Sean Kelly



Final Year Project




SEAN KELLY

Electronic Engineering





Design of voltage regulator module (VRM) circuit for testing of
magnetic components







Supervisor: Dr. Maeve Duffy


Jan 2005




Final Year Project


Progress Report

Sean Kelly

2

Contents


Acknowledgements

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................................
.............

3

References

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...........................

3

Project Outline

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................................
....................

4

Project Description
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..........

4

Background

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.....................

4

Buck Converter

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................................
...................

6

Description

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......................

6

Operation
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.........................

8

Multiphase Topologies
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................................
....

9

Proposals for tackling project

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...........................

11

Research

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................................
................................
........................

11

Ordering

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................................
................................
........................

11

Pspice

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................................
................................
............................

11

Progression to date

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................................
............

12

VRM 10.1 Specification

................................
................................
...............................

12

Initial Design Spec

................................
................................
................................
........

12

Design Procedure

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................................
..........

13

Component Selection

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................................
........

21

Output Capacitance

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................................
................................
.......

21

Output Inductance

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................................
................................
.........

21

Power Switch

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................................
................

22

Pspice

................................
................................
................................
............................

23

Detailed Task List and Project Plan

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..................

25











Final Year Project


Progress Report

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3

A
cknowledgements


I would like to thank my supervisor Dr. Maeve Duffy for the time and effort
she put into
helping me throughout the year.


I would

also

like to thank the lab technicians Myles, Martin and Aodh for all their
help
.


References


Intel’s website was used to get Intel VRM 10.1 Specification and the Xeon p
rocessor
datasheet.


Analog Devices website used to get datasheets for the controller ICs and MOSFET
drivers.


The ORCad website was used to gain knowledge of pspice.


N
otes in ‘Electrical Power and Machines’ and ‘Power Electronics’ were used throughout
th
is project.

















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1.

Project Outline


1.1

Project Description


The aim of this project is to design, build and test a voltage regulator module circuit
(VRM) that can be used to

compare the performance of different magnetic component
designs. The VRM will be used to convert the input voltage (typically 12V) to a
lower level which will supply a microprocessor load e.g. the Intel Pentium.

The work will include circuit design and si
mulation, component modeling and design
and circuit testing.


1.2

Background


Voltage regulator modules are a special class of power converter circuits used to
supply microprocessor loads e.g. the Intel Pentium. The VRM converts
the system
bus voltage (typically 12 V) to a lower level.


While current operating voltages are in the range of 1
-

1.5 V, it is expected that the
required operating voltages in the next few years will decrease below 1 V while
increasing the drawn current

(the required current can easily exceed 100A) from the
power supply in order
to reduce the power consumption

while increasing the
microprocessor speed.


With such low voltage levels, one of the main challenges of VRM design is to
maintain the constant o
utput voltage under varying and transient load (current)
conditions, when the microprocessor switches from one state to the other, voltage
drop spikes occur, these spikes must be limited.


Final Year Project


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5

The main limit is caused by the large inductance values required t
o maintain ripple
levels for steady
-
state operation. The standard industry solution is a multi
-
phase buck
converter, in which the inductance is distributed between several phases that are
controlled in parallel.


A buck derived voltage regulator module (VR
M) will be designed to satisfy these
requirements.



















Final Year Project


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6

2.

Buck Converter


2.1

Description


The most common power converter

topology is the buck
power converter
, sometim
es
called a s
tep down power converter
. Power supply designers choose the

buck power
converter

because the output voltage is always
less than the input voltage in the same
polarity and is not isolated from the input.


The buck regulator circuit is a switching regulator.

It uses an inductor and a capacitor
as energy storage elements so that energy can be transferred from the input to the
output in discrete packets. The advantage of using switching regulators is that they
offer higher efficiency than linear regulators. The

one disadvantage is noise or ripple,
the ripple will need to be minimized through careful component selection.


A requirement of the design is to have high current slew rate

(up to 930 A/
μs)

to
increase switching speed of microprocessor from one state to the other but this causes
voltage drop spikes at the processor power supply. To achieve high current slew rate
the inductor L
o

should be as small as possible. This in turn while achieving
faster
transient response will cause the output voltage ripple to increase.


To reduce output voltage ripple, the switching frequency should be increased but this
lowers efficiency. This means that the selection of the switching devices will be an
importan
t issue. The output voltage ripple can also be reduced by increasing the
output capacitance, this means a large capacitor in practical design.


The input current for a buck power converter is discontinu
ous due to the power
switch
, the current pulses from 0

to Io every switching cycle. The output current for a
buck power converter is continuous because the output current is supplied by the
Final Year Project


Progress Report

Sean Kelly

7

output inductor/capacitor combination; the output capacitor never su
pplies the entire
load current
for continuous i
nduct
or current mode operation.



Buck Converter


Buck Waveforms



Final Year Project


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8

2.2

Operation


This circuit can operate in 3 ways.



Mode 1

The first st
ate corresponds to the case when the switch is ON. In this state, the current
through the inductor rises, and the energy stored in it increases, during this state the
inductor acquires energy.

Vo
DT
I
Lo
Vo
dt
di
Lo
Vi
L








I


When the switch is closed, the diod
e is in the OFF state. The diode is there so there
will always be a current source for the inductor.


Mode 2

The second state is when the switch is OFF and the diode is ON. In this state, the
inductor current free
-
wheels through the diode and the inducto
r supplies energy to
the RC network at the output. The energy in the inductor falls in this state.




T
D
I
Lo
Vo
dt
di
Lo
Vo
L
)
1
(
0










II


When the switch is open, the inductor discharges its energy. When all of its energy
has discharged, the current falls to zer
o and tends to reverse, but the diode blocks
conduction in the reverse direction. In the third state both the diode and the switch are
OFF, in this state the capacitor discharges its energy and the inductor is at rest with
no energy stored in it.


There ca
nnot be a net change in flux in the inductor or it would saturate over a
number of cycles. The increase in current while the switch is on must exactly equal
the decrease in current while the switch is open.


Final Year Project


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9

Combining I and II:




T
D
Lo
Vo
DT
Lo
Vo
Vi
)
1
(







Vo = DVi


Average output voltage is determined by the duty cycle D of the switch and is less
than the input voltage.


2.3

Multiphase Topologies


While
there is no real

limit for a single phase buck regulator, the ad
vantages of
designing with multiphase converters become apparent as load currents
increase to
their

current large values
.


These adv
antages include:




R
educed input
-
ripple current
.




S
ubstantially decreasing the
number of input capacitors
.



R
educed output
-
rip
ple voltage due to an effective multiplication of the ripple
frequency
.



R
educed component temperature achieved by distributing t
he losses over
more components



R
educed
-
height external components.


Final Year Project


Progress Report

Sean Kelly

10


Mu
ltiphase Interleaved Buck Conve
rter


Multiphase converte
rs are essentially multiple buck regulators operated in parallel
with their switching frequencies synchronized and phase shifted by 360/n degrees,
(
where n
identifies each

phase
)
. Paralleling converters makes output regulation
slightly more

complex. This p
roblem is

solved with a current
-
mode control IC that
regulates each inductor current in addition to the output voltage.







Final Year Project


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11

3.


Proposals for tackling project


3.1

Research


Review
of buck converter
to
understand the modes of operation.

Review of VRM circuit topologies for Intel VRM 10.1 specification.

Once these are understood initial circuit design can be undertaken.


3.2

Ordering


Once all circuit values
have been calculated and components chosen they will have to
be ordered. This will include Controller IC, MOSFET drivers, MOSFETs, capacitors
etc.


3.3

Pspice


Pspice is a software package used to simulate power electronic circuits.


The student version is available on the ORCAD website, this was downloaded and
can be used for simulation of the circuits once design procedure is completed.









Final Year Project


Progress Report

Sean Kelly

12

4.

Progression to date


4.1

VRM 10.1 Specification


The Voltage Regulator Module (VRM) 10.1 Design guidelines defines DC
-
to
-
DC
converters to help meet the power requirements of computer

systems using Intel®
Xeon™ processor with 800 MHz system bus
.


The document defines electrical, thermal and mechanical specifications for VRM
10.1.


The voltage regulator is plugged into a baseboard, where the baseboard is designed to
support more than one

processor.


4.2

Initial Design Spec

The design parameters for a typical Intel VRM 10.1 compliant CPU application are:




Input Voltage





=

12 V



VID setting voltage (V
VID
)



=

1.3 V



Duty Cycle (D)





=

0.108



Nominal out
put voltage at no load (V
ONL
)

=

1.28 V



Nominal output voltage at 120A load (V
OFL
)

=

1.13 V



Static output voltage drop based on a 125m
Ω

load line (R
O
) from no load to
full load



V
D

= V
ONL

-

V
OFL





=

150 mV





Maximum output Current (I
O
)



=

120 A




Maximum output current step (d I
O
)


=

105 A



Number of phases (n)




=

4



Switching frequency per phase (f
SW
)


=

500 kHz

Final Year Project


Progress Report

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13

4.3

Design Procedure




Setting clock frequency





R
T

=





k
pF
f
n
SW
27
7
.
4
1






=






k
pF
k
27
7
.
4
500
4
1






=

79.4kΩ




Soft Start & Current Limit Latch off delay times


C
DLY


=


42nF


Choosing the closest 1 % standard capacit
or

C
DLY


=


39nF



R
DLY


=



DLY
DELAY
C
t

96
.
1



=



452kΩ


Choosing the closest 5 % standard resistor




R
DLY

=

470kΩ





Inductor Selection


L



RIPPLE
SW
O
VID
V
f
D
n
R
V





))
(
1
(





mV
kHz
m
V
10
500
))
108
.
0
4
(
1
(
25
.
1
3
.
1













184 nH


Choose inductor value




L

=

320 nH

Final Year Project


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Sean Kelly

14




I
R

=

L
f
D
V
SW
VID



)
1
(





=

7.25 A




I
R

50% of max DC current in inductor




Inductor should no
t saturate at peak current of 33.6
25 A





DCR (DC Resistance)




1
-

1½ times droop resistance (R
O
)




use DCR of 1.4mΩ




Output Droop Resis
tance


R
O

=

L
X
PH
CS
R
R
R

)
(

R
PH(X)

=





k
m
m
100
25
.
1
4
.
1


=

112 kΩ




Inductor DCR temperature correction


Inductor’s DCR used as sense element and copper wire is source of the DCR,
need to compensate for temperature changes of the inductors wind
ing.


Temperature coefficient of copper = 0.39 % /
0
C = 0.0039




A

=

)
25
(
)
50
(
0
0
C
TH
C
TH
R
R


B

=

)
25
(
)
90
(
0
0
C
TH
C
TH
R
R


Relative values of RCS for each temperature 50
0
C & 90
0
C



r
1
=


))
25
(
(
1
1
1



T
TC


r
2
=

))
25
(
(
1
1
2



T
TC




=

0.9112





=

0.7978



Final Year Project


Progress Report

Sean Kelly

15



Relative values for R
CS1
, R
CS2

and R
TH




r
CS2

=

)
(
)
1
(
)
1
(
)
1
(
)
1
(
)
(
2
1
1
2
2
1
B
A
r
A
B
r
B
A
r
A
B
r
B
A
r
r
B
A




















=

0.7195




r
CS1

=

2
2
1
1
1
)
1
(
CS
CS
r
r
A
r
A




=

0.3795




r
TH

=

1
2
1
1
1
1
CS
CS
r
r



=

1.075




R
TH

=

CS
TH
R
r


=

118.28k
Ω




k

=

)
(
)
(
CALCULATED
TH
ACTUAL
TH
R
R

=

0.8455


Calculate R
CS1

and R
CS2




R
CS1

=

1
CS
CS
r
k
R


R

=

35.3kΩ




R
CS2

=

))
(
)
1
((
2
CS
CS
r
k
k
R





=

83.9kΩ



Choosing closest 1 % resistor gives:




R
CS1

= 35.7 k
Ω




R
CS2

= 84.5 k
Ω




Final Year Project


Progress Report

Sean Kelly

16



Output Offset


The
Intel specification requires tha
t at no load the nominal output voltage of the
regulator be offset to a value lower than the nominal voltage corresponding to the
VID code.

Offset set by constant current source from FB pin through R
B




R
B

=

FB
ONL
VID
I
V
V


=

A
V
V

5
.
15
28
.
1
3
.
1


=

1.29k
Ω

Choosing closest 1 % standard resistor gives

R
B


=

1.3 k
Ω




C
OUT

Selection


Ceramic Capacitance

Use 18 X 10μ
F 1206 capacitors



Cz

=

180 μ
F


Bulk Capacitance



Cx
(MIN)



Z
VID
O
rl
O
O
C
V
I
V
R
n
I
L








)
(






F
V
A
mV
m
A
nH

180
3
.
1
)
100
50
25
.
1
(
4
100
320










=

3.25 mF




Cx
(MAX)


Z
O
V
VID
V
VID
V
O
C
L
nKR
V
V
t
V
V
R
nK
L






)
1
)
(
1
(
2
2
2




Where k

=

-
ln
)
(
V
ERR
V
V

=

5.2

Final Year Project


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Sean Kelly

17


*

The VRM must be capable of accepting voltage level changes of 1
2.5 mV
steps every 5 μ
s,
up to 36 steps (450 mV) in 180 μ
s

V
V

= 450 mV,

t
V

= 180 μ
s,

V
ERR

= 2.5 mV.


Cx
(MAX)



F
nH
mV
m
V
s
V
m
mV
nH


180
)
1
)
320
450
25
.
1
2
.
5
4
3
.
1
180
(
1
(
3
.
1
25
.
1
2
.
5
4
450
320
2
2
2

















Cx
(MAX)


26.9mF


Use eight 560 μ
F Al
-
Poly capacitors with a typical ESR of 5m
Ω

each yields Cx =
4.48 mF with an Rx = 0.63m
Ω




Lx



2
2
Q
R
C
O
Z








2
25
.
1
180
2



m
F




563pF


Where Q is limited

to
2
t
o ensure a critically damped system.





Power MOSFETS


Guideline is to limit power dissipation to 1 W per MOSFET


Synchronous MOSFETs

With conduction losses being dominant

The power dissipated in each synchronous MOSFET




P
SF


=

)
(
2
2
]
)
(
12
1
)
[(
)
1
(
SF
DS
SF
R
SF
O
R
n
I
n
n
I
D










=








m
A
A
8
.
4
]
)
8
25
.
7
4
(
12
1
)
8
120
[(
)
108
.
0
1
(
2
2

Final Year Project


Progress Report

Sean Kelly

18



P
SF

=

968 mW


Main MOSFETs

There are two main power dissipation components in main MOSFETs

Switching loss per main MOSFET:




P
S(MF)

=

ISS
MF
G
MF
O
CC
SW
C
n
n
R
n
I
V
f






2




=

pF
V
kHz
584
4
8
3
8
120
12
500
2











=

315 mW


Conduction loss per main MO
SFET:




P
C(MF)

=

)
(
2
2
]
)
(
12
1
)
[(
MF
DS
MF
R
MF
O
R
n
I
n
n
I
D









=







m
19
]
)
8
25
.
7
4
(
12
1
)
8
120
[(
108
.
0
2
2




=

460 mW


The power dissipated in each main MOSFET




P
MF

=

775 mW



Used ONSEMICONDUCTOR NTD40N02 as the main MOSFET (eight total n
MF

= 8) with a C
ISS

= 584 pF and R
DS(MF)

= 19 m
Ω
.


Used ONSEMICONDUCTOR NTD110N02 as the synchronous MOSFET (eight
total n
SF

= 8) with a C
ISS

= 2710 pF and R
DS(SF)

= 4.8 m
Ω
.


Power dissipation in the driver per phase

Final Year Project


Progress Report

Sean Kelly

19





P
DRV

=

CC
CC
GSF
SF
GMF
MF
SW
V
I
Q
n
Q
n
n
f







]
)
(
2
[





=

V
mA
nC
nC
kHz
12
]
6
)
28
8
78
.
5
8
(
4
2
500
[











=

275 mW




in each d
river which is below 400mW dissipation limit





Ramp Resistor Selection


R
R

=

R
DS
D
R
C
R
A
L
A




3


=

pF
m
nH
5
4
.
2
5
3
320
2
.
0







=

356 kΩ


Choosing closest 1 % standard resistor gives

R
R


=


357 k
Ω



Internal ramp voltage magnitude determined by:





V
R


=

SW
R
R
VID
R
f
C
R
V
D
A





)
1
(






=

kHz
pF
k
V
500
5
357
3
.
1
)
108
.
0
1
(
2
.
0











=

0.26

=

260 mV







Comp Pin Ramp


V
RT

=

O
X
SW
R
R
C
f
n
D
n
V







)
1
(
2
1

Final Year Project


Progress Report

Sean Kelly

20


=









m
mF
kHz
mV
25
.
1
48
.
4
500
4
)
108
.
0
4
1
(
2
1
260


=

274 mV




Current Limit Set Point


R
LIM

=

O
LIM
LIM
LIM
R
I
V
A




=




m
A
V
A
mV
25
.
1
120
3
/
4
.
10



=

208 kΩ


Choosing closest 1 % standard resistor gives

R
LIM


=

205 k
Ω






I
PHLIM

=

2
)
(
)
(
R
MAX
DS
D
BIAS
R
MAX
COMP
I
R
A
V
V
V










=

2
25
.
7
3
5
2
.
1
260
3
.
3
A
m
V
mV
V










=

126 A



The per phase initial duty cycle is determined by:





D
MAX

=

RT
BIAS
MAX
COMP
V
V
V
D


)
(





=

mV
V
V
274
2
.
1
3
.
3
108
.
0







=

0.82





Final Year Project


Progress Report

Sean Kelly

21

5.

Component Selection


5.1

Output Capacitance


In switching power supply power stages, the function of output capacitance is to store
energy. The energy is stored
in the capacitor’s electric field due to the voltage
applied.
T
he function of a capacitor is to attempt to maintain a constant voltage.

Ceramic capacitors have excellent high frequency characteristics so will be used in
this case.

Ceramic capacitance of 18
0
μ
F is used made up of 18 10
μ
F MLC capacitors.

The bulk capacitors help determine the output ripple voltage and its transient
response, selection is dominated by ESR.

Bulk capacitance of 4.48 mF is used made up of
8 560
μ
F Al
-
Poly capacitors.


5.2

Output Ind
uctance


In switching power supply power stages, the function of inductors is to store energy.
The energy is stored in their magnetic field due to the current flowing.

The function of an inductor is usually to attempt
to maintain a constant current or
sometimes to limit the rate of change of current flow.

Inductor value of 320 nH is chosen.







Final Year Project


Progress Report

Sean Kelly

22

5.3

Power Switch


Main MOSFET

In switching power supply power stages, the function of the

main

p
ower switch is to
control the flow of energy from the input power source to the output voltage.

As switching losses dominate, need a device with

low gate charge and gate
-
drain
capacitance.

Chose ONSEMICONDUCTOR NTD40N02 for main MOSFET.



Synchronous MOSFE
T

The
synchronous MOSFET

conducts when the power switch turns off and provides a
path

for

the inductor current.

Conduction losses dominate switching losses so operating two MOSFETs in parallel
reduces R
DS(ON)

and lowers conduction losses.

Chose ONSEMICONDU
CTOR NTD110N02 for synchronous MOSFET.

















Final Year Project


Progress Report

Sean Kelly

23

5.4

Pspice


Pspice is a software package used to simulate power electronic circuits.


The model of a multi
-
phase interleaving buck converter can be simplified as a single
-
phase b
uck converter. The equivalent inductance in the simplified model is 1/n

of the
inductance in each phase. The equivalent switching frequency of the simplified model
is n

times the switching frequency in each phase. So the multi
-
phase interleaving
buck conve
rter can be analyzed in the same way as a single
-
phase buck converter.


The MOSFET pspice models, NTD40N03R (upper MOSFET) and NTD110N02R
(synchronous MOSFET), were downloaded from the ONSEMICONDUCTOR
website for more accurate testing.


Output voltage is

found to be 1V. This deviation from the expected 1.3V is mainly
due to power losses in the MOSFETs
,

as when more MOSFETs are added to the
circuit in parallel the output voltage tends to

1.3V. There will also be discrepancies

due to the fact that the equi
valent series resistance (ESR) and equivalent series
Final Year Project


Progress Report

Sean Kelly

24

inductance (ESL) of the output capacitance has not been taken into account at this
stage
.



Output Voltage Waveform



Inductor & Capacitor Waveform
s
Final Year Project


Progress Report

Sean Kelly

25

6.

Detailed Task List and Project Plan


This is a list of tasks to be completed during the project:



Complete simulation of circuit in SPICE.



Analysis of the circuit design and redesign to allow for non
-
ideal aspects of
components.



Design and simulation of circuit under transient load changes, build and test
circuit. Analyse using SPICE



Design, build and test circuit using commercial components.




















Final Year Project


Progress Report

Sean Kelly

26