AuSn - 2,000hrs@400C Ti/TiW/AuAu(20 m)/Ni/Cu

learnedbawledElectronics - Devices

Nov 24, 2013 (3 years and 8 months ago)

118 views

Extreme
Environment

Electronics Assembly and Packaging



Packaging of
SOI,
SiC

and GaN

components and
circuits

for High
Temperature
: Silicon
C
arbide
and Gallium
Nitride
based electronics
can operate at temperatures
of 500
-
600
o
C, while
silicon
-
on
-
insulato
r (SOI)
technology can be used up
to 300
o
C, providing high
levels of integration for
analog, digital control
and
power electronics.

However, to build
functional electronic
products, the devices must be packaged and interconnected. This
research area

is
ev
aluating materials and processes for interconnect substrate fabrication, die attach, wire
bonding and packaging.
Liquid phase transient

and thermocompression bonding are
being explored for traditional die attach as well as for a sandwich approach where
sub
strates are bonded to both sides of the
device
,

eliminating the need for wire bonding.


Substrates


For power modules, direct bond copper on Al
2
O
3

and AlN and active metal
braze copper on Si
3
N
4

substrates are being evaluated. A key issue is the thermal c
ycle
performance over a wide temperature range due to the coefficient of thermal expansion
(CTE) mismatch between the copper and the ceramics.

Surface

finishes for the copper
compatible with high temperatures in air are also an issue.

For low power applica
tions
(digital, analog, control), thick film on AlN, Al
2
O
3
and SiN
4

is being investigated.


Die attach


AuGe and AuSi


are

being studied for SOI die attach, while liquid phase
transient (LPT) bonding using Au
-
Sn and Au
-
In is being developed for applicati
ons
above 300
o
C. No degradation in die shear strength after 2000 hours at 400
o
C has been
achieved with Au
-
Sn LTP bonding. Thermocompression bonding

of patterned bumps

is
also being used to achieve even higher temperature capability.


Wire bonding


Au and
Pt wire (1 mil for SOI and 10 mil for SiC power die) are being
investigated.
The normal Al bond pads on the SOI are electroless Ni/electroless
Au
plated, providing a monometallic interface for Au wire bonding. SiC and GaN are
typically fabricated with Au w
ire bond pads. Au wire has better electrical conductivity
than Pt, but Pt has better high temperature mechanical strength.


Packaging


Individual and multichip packaging is being developed for high temperature
applications. These packages are ceramic bas
ed

to avoid issues with glass
-
to
-
metal seals
in metal packages
.

97%Au, 3%Cu
53%Sn, 35%Ni, 12%Au
72%Au, 26%Cu, 2%Ni
55%Ni, 41%Sn, 4%Cu
32%Cu,
28%Ni, 26%Au,
14%Sn
All compositions are
in weight percent
97%Au, 3%Cu
53%Sn, 35%Ni, 12%Au
72%Au, 26%Cu, 2%Ni
55%Ni, 41%Sn, 4%Cu
32%Cu,
28%Ni, 26%Au,
14%Sn
All compositions are
in weight percent
97%Au, 3%Cu
97%Au, 3%Cu
53%Sn, 35%Ni, 12%Au
53%Sn, 35%Ni, 12%Au
72%Au, 26%Cu, 2%Ni
72%Au, 26%Cu, 2%Ni
55%Ni, 41%Sn, 4%Cu
55%Ni, 41%Sn, 4%Cu
32%Cu,
28%Ni, 26%Au,
14%Sn
32%Cu,
28%Ni, 26%Au,
14%Sn
All compositions are
in weight percent
AuSn
-
2,000hrs@400C
Ti/
TiW
/Au

Au(20

m)/Ni/Cu
97%Au, 3%Cu
53%Sn, 35%Ni, 12%Au
72%Au, 26%Cu, 2%Ni
55%Ni, 41%Sn, 4%Cu
32%Cu,
28%Ni, 26%Au,
14%Sn
All compositions are
in weight percent
97%Au, 3%Cu
97%Au, 3%Cu
53%Sn, 35%Ni, 12%Au
53%Sn, 35%Ni, 12%Au
72%Au, 26%Cu, 2%Ni
72%Au, 26%Cu, 2%Ni
55%Ni, 41%Sn, 4%Cu
55%Ni, 41%Sn, 4%Cu
32%Cu,
28%Ni, 26%Au,
14%Sn
32%Cu,
28%Ni, 26%Au,
14%Sn
All compositions are
in weight percent
97%Au, 3%Cu
97%Au, 3%Cu
53%Sn, 35%Ni, 12%Au
53%Sn, 35%Ni, 12%Au
72%Au, 26%Cu, 2%Ni
72%Au, 26%Cu, 2%Ni
55%Ni, 41%Sn, 4%Cu
55%Ni, 41%Sn, 4%Cu
32%Cu,
28%Ni, 26%Au,
14%Sn
32%Cu,
28%Ni, 26%Au,
14%Sn
All compositions are
in weight percent
97%Au, 3%Cu
97%Au, 3%Cu
53%Sn, 35%Ni, 12%Au
53%Sn, 35%Ni, 12%Au
72%Au, 26%Cu, 2%Ni
72%Au, 26%Cu, 2%Ni
55%Ni, 41%Sn, 4%Cu
55%Ni, 41%Sn, 4%Cu
32%Cu,
28%Ni, 26%Au,
14%Sn
32%Cu,
28%Ni, 26%Au,
14%Sn
All compositions are
in weight percent
AuSn
-
2,000hrs@400C
Ti/
TiW
/Au

Au(20

m)/Ni/Cu

Packaging of Si and SiGe components and circuits
for Low Temperature:
SiGe devices have been
demonstrated to operate at 10
o
K.
The current
activities center around developing single and
mult
ichip packages that operate over the temperature
range from
-
230
o
C to +120
o
C for lunar applications.


Substrates


M
ultilayer copper/polyimide on Si
, AlN

and Si
3
N
4

substrates are being fabricated and tested
for use down to
-
230
o
C. A key issue is the CTE
ma
tch of the
material

set o
ver the wide temperature
range
required for the lunar environment.


Die attach, wire bonding and flip chip


Indium based
die attach is being used with thermosonic gold wire
bonding for chip & wire assembly. Indium based
solders a
re also being used for flip chip assembly.
Indium remains malleable down to cryogenic
temperatures. With a CTE match between the die and
the substrate, underfill will not be required.


Packaging


Commercially available Al
2
O
3

ceramic
packages are being us
ed. AlN packages would
provide a better CTE match, but only a very limited
number of packages are available as open tooling. A
metallized

Al
2
O
3

lid has been developed to matcht he
CTE of the package. The lid is solder sealed with
Pb/In.