Types of RAM

jumentousklipitiklopSoftware and s/w Development

Oct 30, 2013 (3 years and 8 months ago)

231 views


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
1


ame of faulty:sayyada mubeen & chaitanya

page no
1




LORDS INSTITUTE OF ENGINEERING AND TECHNOLOGY

Himayathsagar, Hyderabad
-
8


COURSE FILE




NAME OF THE FACULTY:
K.P.CHAITANYA & SA
Y
Y
ADA M
UBEEN

DEPARTMENT:

CSE

SUBJECT:
COMPUTER
ORGANIZATION

YEAR(SEMESTER)/BRANCH:

II YR AND III YR CSE













LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
2


ame of faulty:sayyada mubeen & chaitanya

page no
2




LORDS INSTITUTE OF ENGINEERING AND TECHNOLOGY

Himayathsagar, Hyderabad
-
8




CERTIFICATE


This is to certify that Mr./Ms.__
K.P.CHAITANYA ,SAYYADA MUBEEN

Asst.Prof./Assoc.Prof./Prof. of
CSE

department has completed all the
requirement of the Course file of
COMPUTER ORGANIZATION
_
B.Tech/M.Tech,______Semester as per the University requirement.


Head of the Department





PRINCIPAL









LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
3


ame of faulty:sayyada mubeen & chaitanya

page no
3







LORDS INSTITUTE OF ENGINEERING AND TECHNOLOGY

Himayathsagar, Hyderabad
-
8



CONTENTS OF COURSE FILE

S.No

CONTENT

Page No.

1.

Syllabus


2.

Academic Calender


3.

Plan of Syllabus Coverage


4.

Teaching Diary


5.

Class work Time
Table


6.

Hard Copy of Course Material Subjective (Unit Wise)


7.

Soft Copy of Course Material Subjective (Unit Wise)


8.

Hard Copy of Objective Type Questions(Multiple choice/Fill
in the blanks/True or False/Match the following etc.)


9.

Soft Copy of
Objective Type Questions(Multiple choice/Fill in
the blanks/True or False/Match the following etc.)


10.

OHP Sheets (Slides if any)


11.

Power Point Presentations Soft and Hard Copy (if any)


12.

Mid Term Exam Question Papers (Objective and Subjective)


13.

Solution to Mid Term Exam Question papers


14.

University End Exam Question Papers


15.

Solution to University End Exam Question Papers


16.

Assignments (Unit Wise) Question Papers and Answer
Scripts of Students


17.

Unit Test(Unit Wise) Question Papers and Answer Scripts of
Students


18.

Additional Solved Problems


19.

Add
-
on Course Material






LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
4


ame of faulty:sayyada mubeen & chaitanya

page no
4




JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY

HYDERABAD

II Year B.Tech. CSE
-
II Sem






T

P

C

4+1*

0

4

COMPUTER
ORGANIZATION


UNIT I :

BASIC STRUCTURE OF COMPUTERS :
Computer Types, Functional unit, Basic OPERATIONAL concepts, Bus
structures, Software, Performance, multiprocessors and multi computers. Data Representation. Fixed Point
Representation. Floating


Point

Representation. Error Detection codes.


UNIT II :

REGISTER TRANSFER LANGUAGE AND MICROOPERATIONS :
Register Transfer language.Register Transfer
Bus and memory transfers, Arithmetic Mircrooperatiaons, logic micro operations, shift micro operations, Arithme
tic
logic shift unit.
Instruction codes. Computer Registers Computer instructions



Instruction cycle.

Memory


Reference Instructions. Input


Output and Interrupt. STACK organization. Instruction formats. Addressing
modes. DATA Transfer and manipulation.

Program control. Reduced Instruction set computer.


UNIT III :

MICRO PROGRAMMED CONTROL :
Control memory, Address sequencing, microprogram example, design of
control unit Hard wired control. Microprogrammed control


UNIT IV :

COMPUTER ARITHMETIC :
Additio
n and subtraction, multiplication Algorithms, Division Algorithms, Floating


point
Arithmetic operations. Decimal Arithmetic unit Decimal Arithmetic operations.


UNIT V :

THE MEMORY SYSTEM :
Basic concepts semiconductor RAM memories. Read
-
only memories Ca
che memories
performance considerations, Virtual memories secondary storage. Introduction to RAID.





LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
5


ame of faulty:sayyada mubeen & chaitanya

page no
5




UNIT
-
VI

INPUT
-
OUTPUT ORGANIZATION :
Peripheral Devices, Input
-
Output Interface, Asynchronous data transfer Modes
of Transfer, Priority Interrupt Direct
memory Access, Input

Output Processor (IOP) Serial communication;
Introduction to peripheral component, Interconnect (PCI) bus. Introduction to

standard serial communication protocols like RS232, USB, IEEE1394.


UNIT VII :

PIPELINE AND VECTOR PROCESSING :

Parallel Processing, Pipelining, Arithmetic Pipeline, Instruction Pipeline,
RISC Pipeline Vector Processing, Array Processors.


UNIT VIII :

MULTI PROCESSORS :
Characteristics or Multiprocessors, Interconnection Structures, Interprocessor Arbitration.
Inte
rProcessor Communication and Synchronization Cache Coherance. Shared Memory Multiprocessors.


TEXT BOOKS :

1. Computer Organization


Carl Hamacher, Zvonks Vranesic, SafeaZaky, Vth Edition, McGraw Hill.

2. Computer Systems Architecture


M.Moris Mano,
IIIrd Edition, Pearson/PHI



REFERENCES :

1. Computer Organization and Architecture


William Stallings Sixth Edition, Pearson/PHI

2. Structured Computer Organization


Andrew S. Tanenbaum, 4th Edition PHI/Pearson

3. Fundamentals or Computer Organization a
nd Design,
-

Sivaraama Dandamudi Springer Int. Edition.

4. Computer Architecture a quantitative approach, John L. Hennessy and David A. Patterson, Fourth Edition Elsevier

5.Computer Architecture: Fundamentals and principles of Computer Design, Joseph D. D
umas II, BS Publication.




LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
6


ame of faulty:sayyada mubeen & chaitanya

page no
6





LORDS INSTITUTE OF ENGINEERING AND TECHNOLOGY

Himayathsagar, Hyderabad
-
8


PLAN OF SYLLABUS COVERAGE

SUBJECT:

YEAR/SEMESTER/BRANCH:

TOTAL NO. OF WEEKS AS PER ACADEMIC CALENDER:

S.No.

Unit

Syllabus to be Covered

Period

Week

1

1

Basic structure of computer





Computer types and introduction





Functional units and basic concepts





Bus structure





s/w performance





Multiprocers and Multicomputer





Data types complements





Data representation and fixed point





Error Detection codes



2

2

RTL and Microoperatins





Register transfer language





Bus and Memory transfer





Arthemetic Micro operations





Logic micro operations





ALU shift Instruction codes





Computer Instruction





Input Output
Interupt





Stack Organisation





Micro program ,Micro program control



3

3

Micro pragramed control





Control Memory





Address sequence





Adressing modes





Data transfer and manipulation





Reduced instruction set of computer



4

4

Computer Arthemmetic






LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
7


ame of faulty:sayyada mubeen & chaitanya

page no
7




Sign of the Concerned Faculty Head of

the Department

LORDS INSTITUTE OF ENGINEERING AND TECHNOLOGY

Himayathsagar, Hyderabad
-
8


PLAN OF
SYLLABUS COVERAGE

SUBJECT:

YEAR/SEMESTER/BRANCH:

TOTAL NO. OF WEEKS AS PER ACADEMIC CALENDER:

S.No.

Unit

Syllabus to be Covered

Period

Week


4

Multipling alogarithim,Addition





Subtraction alogarithim





Division algorithim





Floating point
algorithim





Division problems



5

5

Memory hierarchy system





Auxilary Associative





Cache memory





Virtual Memory management



6

6

Peripheral Devices input output





Data transmission mode





Priority DMA





Serial Communication





Data Modes



7

7

Parallel processing





Pipeline Arithmetic





Instructing pipeline





RISC pipeline





Vector processing features





Array processing



8

8

Multiprocessors





Structures





IPC





Synchronization





Cache coherence









Sign of the Concerned Faculty Head of

the Department


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
8


ame of faulty:sayyada mubeen & chaitanya

page no
8




LORDS INSTITUTE OF ENGINEERING AND TECHNOLOGY

Himayathsagar, Hyderabad
-
8



TEACHING DIARY

S.No

Date

No.of
Periods

Cumulative
Periods

Syllabus Covered

Sign

1

21/7

2

2

Basic structure of computer


2

23/7

2

4

Computer types and introduction


3

26/7

1

5

Functional units and basic concepts


4

27/7

1

6

Bus structure


5

28/7

1

7

s/w performance


6

29/7

1

8

Multiprocers and Multicomputer


7

31/7

1

9

Data types complements


8

3/8

1

10

Data representation and fixed point


9

4/8

1

11

Error Detection codes


10

5/8

2

13

RTL and Microoperatins


11

6/8

1

14

Register transfer language


12

9/8

1

15

Bus and
Memory transfer


13

10/8

1

16

Arthemetic Micro operations


14

16/8

1

17

Logic micro operations


15

17/8

1

18

ALU shift Instruction codes


16

18/8

1

19

Computer Instruction


17

19/8

1

20

Input Output Interupt


18

21/8

2

22

Stack Organisation


19

23/8

2

24

Micro program ,Micro program control


20

24/8

1

25

Micro pragramed control


21

24/8

1

26

Control Memory


22

25/8

1

27

Address sequence


23

25/8

1

28

Adressing modes


24

26/8

1

29

Computer Arthemmetic



Head of the Department







PRINCIPAL




LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
9


ame of faulty:sayyada mubeen & chaitanya

page no
9




LORDS INSTITUTE OF ENGINEERING AND TECHNOLOGY

Himayathsagar, Hyderabad
-
8



TEACHING DIARY

S.No

Date

No.of
Perio
ds

Cumulative
Periods

Syllabus Covered

Sign

25

28/8

1

30

Multipling alogarithim,Addition


26

28/8

1

31

Subtraction alogarithim


27

2/9

2

33

Division algorithim


28

3/9

2

35

Floating point algorithim


29

6/9

2

37

Memory hierarchy system


30

7/9

1

38

Auxilary Associative


31

8/9

1

39

Cache memory


32

8/9

1

40

Virtual Memory management


33

16/9

1

41

Peripheral Devices input
output


34

17/9

1

42

Data transmission mode


35

18/9

1

43

Priority DMA


36

20/9

1

44

Serial Communication


37

21/9

2

45

Data Modes


38

28/9

1

46

Parallel processing


39

29/9

2

48

Pipeline Arithmetic


40

30/9

1

49

Instructing pipeline


41

4/10

1

50

RISC pipeline and vector processing


42

5/10

1

51

Array processing


43

8/10

1

52

Multiprocessors


44

9/10

2

54

Structures


45

11/10

2

56

IPC


46

12/10

2

58

Synchronization


47

14/10

1

59

Cache coherence


48

18/10

1

60

cache



Head of the Department







PRINCIPAL



LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
10


ame of faulty:sayyada mubeen & chaitanya

page no
10




LORDS INSTITUTE OF ENGINEERING AND TECHNOLOGY

Himayathsagar, Hyderabad
-
8



TEACHING DIARY

S.No

Date

No.of
Period
s

Cumulative
Periods

Syllabus Covered

Sign

49

20/10

1

61

Revision on 1, 2


50

21/10

2

63

Revision
of 3,4


51

25/10

2

65

Revision of 5


52

27/10

3

68

Revision of 6,7


53

27/10

2

70

Revision of 8


55

28/10

3

73

Revision Test





















































































































Head of the Department







PRINCIPAL


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
11


ame of faulty:sayyada mubeen & chaitanya

page no
11




LORDS INSTITUTE OF ENGINEERING AND TECHNOLOGY

Himayathsagar, Hyderabad
-
8


TIME TABLE

Day/Period

I

II

III

IV


V

VI

VII

VIII

Monday





L

co





Tuesday





U

co





Wednesday





N



co



Thursday

co




C





Co(tut)

Friday





H






Saturday


co





















COURSE FILE


LORDS INSTITUTE OF
ENGINEERING

&

TECHNOLOGY PAGE NO:


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
12


ame of faulty:sayyada mubeen & chaitanya

page no
12





SUBJECT:




YEAR/SEMESTER:

B
RANCH:

NAME OF THE FACULTY:

UNIT
-
1









BASIC STRUCTURE OF COMPUTERS

Computer Types



Digital Computer is a fast electronic calculating machine that




accepts digitized input information,



processes it according to a list of internally stored instructions,



and produces the resulting output information.



Many types of computers exist that differ widely in Size, Cost,Computational Power and
intended Use



Personal Computer/ Desktop computers



Por
table Notebook Computers



Work Stations



Enterprise System Servers



Super Computers




Figure 1.1

Block diagram of a digital computer.

Functional Units




LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
13


ame of faulty:sayyada mubeen & chaitanya

page no
13





Functional

Units



A digital computer consists of five functionally independent parts.



Input



Output



Memory Unit



Arithmetic and Logic Unit



Control Unit



INPUT UNIT: computers accept coded information through input units, which reads the
data.




Ex: Keyboard, Mouse, joy sticks.



Output Units:


Table (1.1)

Basic identities of Boolean Algebra.


BUS STRUCTURES

There are different types of buses

They are

a)controll bus

b)data bus

A bus structure comprises a plurality of driver circuits, each driver circuit comprising an input
for a first signal and a terminal for an output signal wherein each driver circuit is
capable of
providing the output signal at the terminal upon receipt of the first signal, a parallel bus
comprising a plurality of output signal lines at a receiving end, being connectable to a target
component, each of the signal lines extending at least f
rom the receiving end to the terminal of a
different one of the plurality of driver circuits, such that a length of the output signal line
between the receiving end and the respective driver circuits decreases in a connection order
among the plurality of d
river circuits, and a signal line coupled to each of the


inputs of the driver
circuits in the connection order.


MULTIPROCESSORS AND MULTICOMPUTERS


multicomputer
--

A computer made up of several computers. The term generally refers to an
architecture in w
hich each processor has its own memory rather than multiple processors with a
shared memory.


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
14


ame of faulty:sayyada mubeen & chaitanya

page no
14





Something similiar to parallel computing.

Distributed computing deals with hardware and software systems containing more than one
processing

element or storage
element, concurrent processes, or multiple programs, running under a loosely
or tightly controlled regime. A multicomputer may be considered to be either a loosely coupled
NUMA computer or a tightly coupled

cluster. Multicomputers are commonly used when strong
computer power is required in an environment with restricted physical space or electrical power.


Common suppliers include Mercury Computer Systems, CSPI, and SKY Computers.


Common uses include 3D me
dical imaging devices and mobile radar.


In distributed computing a program is split up into parts that run simultaneously on multiple
computers communicating over a network. Distributed computing is a form of parallel
computing, but parallel


computing i
s most commonly used to describe program parts running
simultaneously on multiple processors in the same computer. Both types of processing require
dividing a program into parts thatcan run simultaneously, but distributed programs often must
deal with hete
rogeneous environments, network links of varying latencies, and unpredictable
failures in the network or the computers.


multiprocessor
--

A multiprocessor system is simply a computer that has more than one CPU on
its motherboard. If the operating system i
s built to take advantage of this, it can run different
processes(or different threads belonging to the same process) on different CPUs.

Multiprocessing is the use of two or more central processing units (CPUs) within a single
computer system. The term al
so refers to the ability of a system to support more than one
processor and/or the ability to allocate tasks between them.[1] There are many variations on this
basic theme, and the definition of multiprocessing can vary with context, mostly as a function o
f
how CPUs are defined (multiple cores on one die, multiple chips in one package, multiple
packages in one system unit, etc.).



BASIC OPERATONAL CONCEPTS


DATA REPRESENTATION

Information that a Computer is dealing with


* Data


-

Nume
ric Data


Numbers( Integer, real)


-

Non
-
numeric Data


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
15


ame of faulty:sayyada mubeen & chaitanya

page no
15





Letters, Symbols


* Relationship between data elements


-

Data Structures


Linear Lists, Trees, Rings, etc




NUMERIC DATA REPRESENTATION

R = 10 Decimal number system,

R = 2 Binary

R = 8 Octal,




R = 16 Hexadecimal

Radix point(.) separates the integer

portion and the fractional portion

Data



Numeric data
-

numbers(integer, real)



Non
-
numeric data
-

symbols, letters


Number System


Nonpositional number system




-

Roman number system


Positional number system




-

Each digit position has a value called a
weight

associated with it




-

Decimal, Octal,
Hexadecimal, Binary

Base (or radix) R number


-

Uses R distinct symbols for each digit


-

Example A
R

= a
n
-
1
a
n
-
2

...

a
1
a
0
.a
-
1
…a
-
m



Table for addition is infinite


--
> Impossible to build, very expensive even


i
f it can be built


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
16


ame of faulty:sayyada mubeen & chaitanya

page no
16





* Positional Number System


-

Table for Addition is finite


--
> Physically realizable, but cost wise


the smaller the table size, the less


expensive
--
>

Binary is favorable to Decimal

0 1 2 3 4 5 6 7 8 9

0 0 1 2 3 4 5 6 7 8 9

1 1 2 3 4 5 6 7 8 9 10

2 2 3 4 5 6 7 8 9 1011

3 3 4 5 6 7 8 9 101112

4 4 5 6 7 8 9 10111213

5 5 6 7 8 9
1011121314

6 6 7 8 9 101112131415

7 7 8 9 10111213141516

8 8 9 1011121314151617

9 9 101112131415161718


REPRESENTATION OF NUMBERS
-

POSITIONAL NUMBERS

Decimal Binary Octal Hexadecimal


00 0000 00

0


01 0001 01 1


02 0010 02 2


03 0011 03 3


04 0100 04 4


05 0101

05 5


06 0110 06 6


07 0111 07 7


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
17


ame of faulty:sayyada mubeen & chaitanya

page no
17





08 1000 10 8


09 1001 11 9



10 1010 12 A


11 1011 13 B


12 1100 14 C


13 1101 15 D


14 1110

16 E


15 1111 17 F



CONVERSION OF BASES

Decimal to Base R number

Base R to Decimal Conversion

V(A) =


a
k
k

A = a
n
-
1

a
n
-
2

a
n
-
3

… a
0

. a
-
1

… a
-
m

(736.4)
8

= 7 x 8
2

+ 3 x 8
1

+ 6 x 8
0

+ 4 x 8
-
1


= 7 x 64 + 3 x 8 + 6 x 1 + 4/8 = (478.5)
10

(110110)
2

= ... = (54)
10

(110.111)
2

= ... = (6.785)
10

(F3)
16

= ... = (243)
10

(0.325)
6

= ... = (0.578703703 .................)
10

-

Separate the number into its
integer

and

fraction

parts and convert


each part
separately.

-

Convert
integer part
into the base R number




successive divisions by R and accumulation of the remainders.

-

Convert
fraction part
into the base R number


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
18


ame of faulty:sayyada mubeen & chaitanya

page no
18







successive multiplications by R and acc
umulation of integer


digits


EXAMPLE

Convert 41.6875
10

to base 2.

Integer = 41

41

20 1

10 0


5 0


2 1


1 0


0 1

Fraction = 0.6875

0.6875

x 2

1.3750

x 2

0.7500

x 2

1.5000


x 2

1.0000

(41)
10

= (101001)
2

(0.6875)
10

=
(0.1011)
2

(41.6875)
10

= (101001.1011)
2

Convert (63)
10

to base 5:


(223)
5

Convert (1863)
10

to base 8:


(3507)
8


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
19


ame of faulty:sayyada mubeen & chaitanya

page no
19




Convert (0.63671875)
10

to hexadecimal:

(0.A3)
16


COMPLEMENT OF NUMBERS

Two types of complements for base R number system:


-

R's complement and (R
-
1)'s complement

The (R
-
1)'s Complement



Subtract each digit of a number from (R
-
1)


Example


-

9's complement of 835
10

is 164
10




-

1's complement of 1010
2

is 0101
2
(bit by bit complement operation)

The R's Complement



Add 1 to the low
-
order digit of its (R
-
1)'s complement


Example


-

10's complement of 835
10

is 164
10

+ 1 = 165
10


-

2's complement of 1010
2

is 0101
2

+ 1 = 0110
2


FIXED POINT REPRESENTATION

Binary Fixed
-
Point Representation


X = x
n
x
n
-
1
x
n
-
2

... x
1
x
0
. x
-
1
x
-
2

... x
-
m


Sign Bit(x
n
):


0 for positive
-

1 for negative


Remaining Bits(x
n
-
1
x
n
-
2

... x
1
x
0
. x
-
1
x
-
2

... x
-
m
)

Numbers:

Fixed
Point Numbers and Floating Point Numbers

SIGNED NUMBERS

Signed magnitude representation


Signed 1's complement representation


Signed 2's complement representation


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
20


ame of faulty:sayyada mubeen & chaitanya

page no
20




Example: Represent +9 and
-
9 in 7 bit
-
binary number



Only one way to represent +9 ==> 0 001001


Three different ways to represent
-
9:



In signed
-
magnitude: 1 001001



In signed
-
1's complement: 1 110110



In signed
-
2's complement: 1 110111

In
general, in computers, fixed point numbers are represented


either integer part only or fractional part only.

Need to be able to represent both
positive

and
negative

numbers



CHARACTERISTICS OF 3 DIFFERENT REPRESENTATIONS

Complement


Signed magnitude:

Complement
only

the sign bit


Signed 1's complement:

Complement
all

the bits including sign bit


Signed 2's complement:

Take the 2's complement of the number,










Maximum and Minimum Representable Numbers and Representation of Zero

X = x
n

x
n
-
1

... x
0

. x
-
1

... x
-
m

Signed Magnitude


Max: 2
n

-

2
-
m

011 ... 11.11 ... 1


Min:
-
(2
n
-

2
-
m
) 111 ... 11.11 ... 1


Zero: +0 000 ... 00.00 ... 0


-
0
100 ... 00.00 ... 0


Signed 1’s Complement


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
21


ame of faulty:sayyada mubeen & chaitanya

page no
21





Max: 2
n

-

2
-
m

011 ... 11.11 ... 1


Min:
-
(2
n

-

2
-
m
) 100 ... 00.00 ... 0


Zero: +0 000 ... 00.00 ... 0


-
0 111 ... 11.11 ... 1

s
igned 2’s Complement


Max: 2
n

-

2
-
m

011 ... 11.11 ... 1


Min:
-
2
n

100 ... 00.00 ... 0


Zero: 0 000 ... 00.00 ... 0


2’s COMPLEMENT REPRESENTATION WEIGHTS



Signed 2’s complement representation follows a “weight” scheme similar to that of
unsigned numbers



Sign bit has negative weight



Other bits have regular weights

X = x
n

x
n
-
1

... x
0



LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
22


ame of faulty:sayyada mubeen & chaitanya

page no
22






ERROR DETECTING CODES

Simplest
is the Parity System


Simplest method for error detection


-

One
parity

bit attached to the information


-

Even Parity
and

Odd Parity


Even Parity


-

One bit is attached to the information so that


the total number o
f 1 bits is an even number


1011001 0


1010010 1


Odd Parity

One bit is attached to the information so that the total number of 1 bits is an odd number





LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
23


ame of faulty:sayyada mubeen & chaitanya

page no
23






COURSE FILE


LORDS INSTITUTE OF
ENGINEERING

& TECHNOLOGY PAGE NO:


SUBJECT:




YEAR/SEMESTER:

BRANCH:

NAME OF THE FACULTY:

UNIT2


REGISTER TRANSFER LANGUAGE

Combinational and sequential circuits can be used to create simple digital systems.



These are the low
-
level building blocks of a digital computer.



Simple digital systems are frequently characterized in terms of



the registers they contain, and



the operations that they perform.



Typically,



What operations are performed on the data in the
registers



What information is passed between registers


MICROOPERATIONS (1)



The operations executed on data stored in registers are called microoperations.



Examples of microoperations



Shift



Load



Clear



Increment



Count


MICROOPERATION (2)


An elementary operation performed (during one clock pulse), on the information stored in one
or more registers.

R


f(R, R)

f: shift, load, clear, increment, add, subtract, complement,




LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
24


ame of faulty:sayyada mubeen & chaitanya

page no
24





and, or, xor, …




INTERNAL HARDWAREORGANIZATION OF A DIGITAL
SYSTEM

-

Set of registers it contains and their function


-

The sequence of microoperations performed on the binary information stored in the registers

-

Control signals that initiate the sequence of


microoperations (to perform the functions)



Definition

of the internal hardware organization of a computer


REGISTER TRANSFER LANGUAGE



The symbolic notation used to describe the microoperation transfers among registers is
called a


Register transfer language.



Register transfer language



A symbolic language



A convenient tool for describing the internal organization of digital computers



Can also be used to facilitate the design process of digital systems.




LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
25


ame of faulty:sayyada mubeen & chaitanya

page no
25







Often we want the transfer to occur only under a predetermined control condition.





if (p=1) then (R
2


R1)


where p is a control signal generated in the control section.



In digital systems, this is often done via a control signal, called a control function



If the signal is 1, the action takes place



This is represented as:



P: R2


R1

Which means “if P = 1, then load the contents of register R1 into register R2”, i.e., if (P = 1)
then


(R2


R1)

Register Transfer



Registers are designated by capital letters, sometimes followed by numbers (e.g., A, R13,
IR).



Often the names indicate fu
nction:



MAR

-

memory address register



PC

-

program counter



IR

-

instruction register





Often we want the transfer to occur only under a predetermined control condition.





if (p=1) then (R2


R1)


where p is a control signal generated in the control section.


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
26


ame of faulty:sayyada mubeen & chaitanya

page no
26






In digital systems, this is often done via a
control signal
, called a
control function



If the signal is 1, the action takes place



This is represented as:



P: R2


R1

Which means “if P = 1, then load the contents of register R1 into register R2”, i.e., if (P = 1)
then


(R2


R1)


SIMULTANEOUS OPERATIONS



If two or more operations are to occur simultaneously, they are separated with commas


P: R3


R5
,
MAR


IR



Here, if the control function P = 1, load the contents of R5 into R3, and at the same time
(clock),

load the contents of register IR into register MAR


BUS AND MEMORY TRANSFERS



LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
27


ame of faulty:sayyada mubeen & chaitanya

page no
27




Bus is a path(of a group of wires) over which information is transferred,
from any of several
sources to any of several destinations.

From a register to bus BUS


R




Bus and Memory Transfers

BUS TRANSFER IN RTL




Depending on whether the bus is to be mentioned explicitly or not, register transfer can
be indicated.



In the
former case the bus is implicit, but in the latter, it is explicitly indicated

R2


R1

BUS


R1, R2


BUS

MEMORY (RAM)

Memory (RAM) can be thought as a sequential circuits containing some number of registers



These registers hold the
words

of memory



Each of the r registers is indicated by an
address



These addresses range from 0 to r
-
1


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
28


ame of faulty:sayyada mubeen & chaitanya

page no
28






Each register (word) can hold n bits of data



Assume the RAM contains r = 2k words. It needs the following



n data input lines



n data output lines



k address lines



A Read c
ontrol line



A Write control line


MEMORY TRANSFER



Collectively, the memory is viewed at the register level as a device, M.



Since it contains multiple locations, we must specify which address in memory we will
be using



This is done by indexing memory
references



Memory is usually accessed in computer systems by putting the desired address in a
special register, the
Memory Address Register

(
MAR
, or
AR
)



When memory is accessed, the contents of the MAR get sent to the memory unit’s
address lines


M


MEMORY READ


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
29


ame of faulty:sayyada mubeen & chaitanya

page no
29






To read a value from a location in memory and load it into a register, the register transfer
language


notation looks like this:




This causes the following to occur



The contents of the MAR get sent to the memory address lines



A Read (= 1) gets

sent to the memory unit



The contents of the specified address are put on the memory’s output data lines



These get sent over the bus to be loaded into register R1

R1


M[MAR]

MEMORY WRITE



To write a value from a register to a location in memory looks like

this in register transfer
language:




This causes the following to occur



The contents of the MAR get sent to the memory address lines



A Write (= 1) gets sent to the memory unit



The values in register R1 get sent over the bus to the data input lines of the
memory



The values get loaded into the specified address in the memory


ARITHMETIC MICROOPERATIONS

Computer system microoperations are of four types
:

1.
Register transfer microoperations
transfer binary information from one register to another

2.
Arithmetic

microoperations
perform arithmetic operations on numeric data stored in registers.

3.

Logic microoperations
perform bit manipulation operations on non numeric data stored in
registers.

4.

Shift microoperations
perform shift operations on data stored in
registers.

Table: Arithmetic Micro
-
Operations


R3



R1 + R2

Contents of R1 plus R2 transferred to R3

R3



R1
-

R2

Contents of R1 minus R2 transferred to R3

R2



R2’


Complement the contents of R2


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
30


ame of faulty:sayyada mubeen & chaitanya

page no
30




R2



R2’+ 1

2's complement the contents of R2 (negate)

R3



R1 + R2’+ 1

subtraction

R1



R1 + 1

Increment

R1



R1
-

1

Decrement

The basic arithmetic microoperations are



Addition



Subtraction



Increment



Decrement



The additional arithmetic microoperations are



Add with carry



Subtract with borrow



Transfer/Load



etc. …


BINARY ADDER / SUBTRACTOR / INCREMENTER


Binary Adder
-
Subtractor

Binary
Incrementer


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
31


ame of faulty:sayyada mubeen & chaitanya

page no
31




Binary Adder


LOGIC MICROOPERATIONS



It specifies binary operations on the strings of bits stored in registers



Logic microoperations are bit
-
wise operations,
i.e., they work on the individual
bits of data



useful for bit manipulations on binary data



useful for making logical decisions based on the bit value




There are, in principle, 16 different logic functions that can be defined over two binary
input
variables




However, most systems only implement four of these



AND (

), OR (

), XOR (

), Complement/NOT



The others can be created from combination of these



LIST OF LOGIC MICROOPERATIONS


0 0 0 0


F0 = 0


F


0


Clear


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
32


ame of faulty:sayyada mubeen & chaitanya

page no
32




0 0 0

1


F1 = xy F


A


B


AND

0 0 1 0


F2 = xy' F


A


B’

0 0 1 1


F3 = x


F


A


Transfer A

0 1 0 0


F4 = x'y F


A’


B

0 1 0 1


F5 = y


F


B


Transfer

B

0 1 1 0


F6 = x


y F


A


B Exclusive
-
OR

0 1 1 1


F7 = x + y F


A


B OR

1 0 0 0


F8 = (x + y)' F




A


B)’ NOR

1 0 0 1


F9 = (x


y)' F


(A


B)’ Exclusive
-
NOR

1 0 1 0


F10 = y' F


B’ Complement B


HARDWARE IMPLEMENTATION OF LOGIC MICROOPERATIONS

0 0 F = A


B AND

0 1 F = A



B OR

1 0 F = A


B XOR

1 1 F = A’ Complement

APPLICATIONS OF LOGIC MICROOPERATIONS



Logic microoperations can be used to manipulate individual bits or a portions of a word in a
registerConsider the data in a register A. In another register, B, is bit data that will be used to
modify the contents of A






Selective
-
set



A


A + B



Selective
-
complement

A


A


B




Selective
-
clear


A


A • B’




Mask (Delete)




A


A • B



Clear





A


A


B



Insert





A


(A • B) + C



Compare



A


A


B



LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
33


ame of faulty:sayyada mubeen & chaitanya

page no
33




SELECTIVE SET



In a selective set operation, the bit pattern in B is used to
set

certain bits in A






1 1 0 0

A
t




1 0 1 0

B




1 1 1 0

A
t+1


(A


A + B)



If a bit in B is set to 1, that same position in A gets set to 1, otherwise that bit in A keeps
its previous


value


SELECTIVE COMPLEMENT



In a selective complement operation, the bit pattern in B is used to
complement

certain
bits in A






1 1 0 0

A
t




1 0 1 0

B




0 1 1 0

A
t+1


(A


A


B)



If a bit in B is set to 1, that same position in A gets complemented
from its original value,
otherwise


it is unchanged


SELECTIVE CLEAR



In a selective clear operation, the bit pattern in B is used to
clear

certain bits in A






1 1 0 0

A
t




1 0 1 0

B




0 1 0 0

A
t+1


(A


A


B’)



If a bit in B is set to 1, that same
position in A gets set to 0, otherwise it is unchanged




MASK OPERATION



In a mask operation, the bit pattern in B is used to
clear

certain bits in A





1 1 0 0

A
t


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
34


ame of faulty:sayyada mubeen & chaitanya

page no
34







1 0 1 0

B




1 0 0 0

A
t+1


(A


A


B)



If a bit in B is set to 0, that same position in A
gets set to 0, otherwise it is unchanged




CLEAR OPERATION



In a clear operation, if the bits in the same position in A and B are the same, they are
cleared in A,


otherwise they are set in A






1 1 0 0

A
t




1 0 1 0

B




0 1 1 0

A
t+1


(A


A


B)


INSERT
OPERATION



An insert operation is used to introduce a specific bit pattern into A register, leaving the
other bit

positions unchanged



This is done as



A mask operation to clear the desired bit positions, followed by



An OR operation to introduce the new bits

into the desired positions




Example



Suppose you wanted to introduce 1010 into the low order four bits of A:




1101 1000 1011 0001

A (Original)






1101 1000 1011
1010

A (Desired)




1101 1000 1011 0001


A (Original)


1111 1111 1111 0000


Mask


1101 1000 1011
0000


A (Intermediate)


0000 0000 0000
1010


Added bits



1101 1000 1011
1010


A (Desired)



LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
35


ame of faulty:sayyada mubeen & chaitanya

page no
35




SHIFT MICROOPERATIONS



Shift microoperations are used for serial transfer of data.



The information transferred through the serial input determines the type of
shift. There
are three


types of shifts



Logical shift



Circular shift



Arithmetic shift



LOGICAL SHIFT



In a logical shift the serial input to the shift is a 0.



A right logical shift operation:



A left logical shift operation:



In a Register Transfer Language,

the following notation is used



shl


for a logical shift left



shr

for a logical shift right




Examples:



R2


shr

R2



R3


shl

R3




CIRCULAR SHIFT



In a circular shift the serial input is the bit that is shifted out of the other end of the
register.




A
right circular shift operation:



A left circular shift operation:



In a RTL, the following notation is used



cil


for a circular shift left



cir

for a circular shift right




Examples:



R2


cir

R2


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
36


ame of faulty:sayyada mubeen & chaitanya

page no
36






R3


cil

R3



ARITHMETIC SHIFT



An arithmetic shift is
meant for signed binary numbers (integer)



An arithmetic left shift
multiplies

a signed number
by two



An arithmetic right shift
divides

a signed number
by two



The main distinction of an arithmetic shift is that it must keep the sign of the number the
same a
s it

performs the multiplication or division




A left arithmetic shift operation:






LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
37


ame of faulty:sayyada mubeen & chaitanya

page no
37














AR
ITHMETIC LOGIC SHIFT UNIT

S3 S2 S1


S0

Cin

Operation


Function

0 0 0


0

0

F = A


Transfer A

0 0 0 0

1

F = A + 1


Increment A

0 0
0 1

0

F = A + B


Addition

0 0 0


1

1

F = A + B + 1 Add with carry


INSTRUCTION CODES



Every different processor type has its own design (different registers, buses,
microoperations,


machine instructions, etc)



Modern processor
is a very complex device



It contain
Many registers



Multiple arithmetic units, for both integer and floating point calculations



The ability to pipeline several consecutive instructions to speed execution


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
38


ame of faulty:sayyada mubeen & chaitanya

page no
38






However, to understand how processors work, we will st
art with a simplified processor
model

This is similar to what real processors were like ~25 years ago



M. Morris Mano introduces a simple processor model he calls the
Basic Computer



We will use this to introduce processor organization and the relationship o
f the RTL model to


the higher level computer processor




INSTRUCTION CYCLE



In Basic Computer, a machine instruction is executed in the following cycle:

1.

Fetch an instruction from memory

2.

Decode the instruction

3.

Read the effective address from memory if
the instruction has an indirect address

4.

Execute the instruction



After an instruction is executed, the cycle starts again at step 1, for the next instruction



Note
: Every different processor has its own (different) instruction cycle



LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
39


ame of faulty:sayyada mubeen & chaitanya

page no
39







LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
40


ame of faulty:sayyada mubeen & chaitanya

page no
40





ARITHMETIC LOGIC

SHIFT UNIT

S3 S2 S1


S0

Cin

Operation


Function

0 0 0


0

0

F = A


Transfer A

0 0 0 0

1

F = A + 1


Increment A

0 0 0 1

0

F = A + B


Addition

0 0 0


1

1

F =
A + B + 1 Add with carry

0 0 1


0

0

F = A + B’ Subtract with borrow

0 0 1


0

1

F = A + B’+ 1 Subtraction

0 0 1


1

0

F = A
-

1


Decrement A

1 0 X


X

X

F = shr A


Shift rig
ht A into F

1 1 X


X

X

F = shl A


Shift left A into F



LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
41


ame of faulty:sayyada mubeen & chaitanya

page no
41







LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
42


ame of faulty:sayyada mubeen & chaitanya

page no
42












LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
43


ame of faulty:sayyada mubeen & chaitanya

page no
43





STACK ORGANIZATON





LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
44


ame of faulty:sayyada mubeen & chaitanya

page no
44




INSTRUCTION FORMATS

A computer instruction is often divided into two parts

An
opcode

(Operation Code) that specifies
the operation for that instruction

An
address

that specifies the registers and/or locations in
memory to use for that operation
In the Basic Computer, since the memory contains 4096 (= 212)
words, we needs 12 bit to specify
which memory address this instruction will use In the Basic
Computer, bit 15 of the instruction specifies the
addressing mode

(0: direct addressing, 1:
indirect addressing)Since the memory words, and hence the instructions, are 16 bits long, that
leaves 3
bits for the instruction’s opcode

The address field of an instruction can represent either

Direct address: the address in memory of
the data to use (the address of the operand), or

Indirect address: the address in memory of the
address in memory of the dat
a to use

ADDRESSING MODES

The address field of an instruction can represent either

Direct address: the address in memory of
the data to use (the address of the operand), orIndirect address: the address in memory of the
address in memory of the data to use


Effective Address (EA)
:
The address, that can be directly used without modification to access an
operand for a


computation
-
type instruction, or as the target address for a branch
-
type instruction




LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
45


ame of faulty:sayyada mubeen & chaitanya

page no
45








Effective Address (EA)

The address, that can be directly used without modification to access an operand for a
computation
-
type instruction, or as the target address for a branch
-
type instruction

DATA TRANSFER AND MANIPU
LATION

When collecting data locally, institutions can customize their collection and delivery systems to
produce the precise formats and data structure necessary for their needs. This section therefore
focuses on vendor
-
provided statistics only. Of the ven
dors that do provide usage data, some offer
the option to receive/review the data in HTML, TXT, XLS, CSV, or even XML (currently rare).
This diversity is not bad in itself. The problem is lodged in the fact that not every vendor
provides all of the same op
tions.

In order to deposit all e
-
resource usage data into a single
location (be it a spreadsheet or database), vendor
-
provided


data must be manipulated to varying
degrees. Different delivery formats (HTML, CSV, etc.) must be normalized through unique
pro
cessing protocols for each format. The data must be cleaned to liminate extraneous
presentation elements (like report titles, footnotes or blank lines). T

T
he raw data itself may need to be further aggregated, disaggregated, or transposed to normalize
cont
ent increments that may be inconsistent with those of the repository (e.g. data provided in
daily or weekly increments may need to be aggregated to monthly totals


prior to


deposit). In
0

AD
D

45
7

2
2

Operan
d

45
7

1

AD
D

30
0

3
5

135
0

30
0

Operand

135
0


+


A
C


+


A
C

Direct
addressing

Indirect
addressing


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
46


ame of faulty:sayyada mubeen & chaitanya

page no
46




many cases the raw data is not sufficiently meaningful and local cate
gories must be assigned to
columns/groups of data to ensure that the data gets into the right place in the repository. It is
clear that some sort of XML
-
based data transfer protocol standard would facilitate faster and
more meaningful data transfer and int
egration, which would in turn enable easier local repository
design.

RISC(REDUCED INSTRUCTION SET COMPUTERS)

Reduced instruction set computing
, or
RISC

(pronounced
/ˈr
ɪ
sk/
), is a
CPU design

strategy
based on the insight that simplified (as opposed
to complex) instructions can provide higher
performance if this simplicity enables much faster execution of each instruction. A computer
based on this strategy is a
reduced instruction set computer

(also
RISC
). There are many
proposals for precise definiti
ons, but the term is slowly being replaced by the more descriptive
load
-
store architecture
. Well known RISC families include
, and
SPARC
.
Some aspects
attributed to the first RISC
-
labeled

designs
around 1975 include the observations that the
memory
-
restricted
compilers

of the time were often unable to take advantageof features intended
to facilitate
manual

assembly coding, and that

complex
addressing modes

take many cycles to
perform due to the required additional memory accesses.

It was argued that such functions would be better performed by sequenc
es of simpler instructions
if this could yield implementations small enough to leave room for many registers, reducing the
number of slow memory accesses. In these simple designs, most instructions are of uniform
length and similar structure, arithmetic op
erations are restricted to CPU registers and only
separate
load

and
store

instructions access memory. These properties enable a better balancing of
pipeline stages

than before, making RISC pipelines significantly more efficient and allowing

Typical characteristics of RISC

For any given level of general performance, a RISC chip will typically have far fewer
t
ransistors

dedicated

to the core logic which originally allowed designers to increase the size of the register set and
increase internal parallelism.

Other features, which are typicall
y found in RISC architectures are:



Uniform instruction format, using a single word with the opcode in the same bit positions in
every instruction, demanding less decoding;



Identical
general purpose registers
, allowing any register to be used in any context,
simplifying compiler design (although normally there are separate
floati
ng point

registers);



Simple
addressing modes
. Complex addressing performed via sequences of arithmetic and/or
load
-
store operations;



LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
47


ame of faulty:sayyada mubeen & chaitanya

page no
47






Fe

data types in hardware, some CISCs ha
ve
byte

string

instructions, or support
complex
numbers
; this is so far unlikely to be found on a RISC.Exceptions abound, of course, within
both CISC and RISC.RISC designs are also more likely to feature a
Harvard memory model
,
where the instruction stream and the data stream are conceptually separated; this means that
modifying the memory where code is held might not have any ef
fect on the instructions
executed by the processor (because the CPU has a separate instruction and data
cache
), at
least until a special synchronization instruction is issued. On the upside, thi
s allows both
caches to be accessed simultaneously, which can often improve performanceMany early
RISC designs also shared the characteristic of having a
branch delay slo
t
.



A branch delay slot is an instruction space immediately following a jump or branch. The
instruction in this space is executed,whether or not the branch is taken (in other words the
effect of the branch is delayed).

This instruction keeps the
ALU

of the CPU busy for the extra time normally needed to perform a
branch. Nowadays the branch delay slot is considered an unfortunate side effect of a partic
ular
strategy for


implementing some RISC designs, and modern RISC designs generally do away
with it
.

















LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
48


ame of faulty:sayyada mubeen & chaitanya

page no
48





COURSE FILE


LORDS INSTITUTE OF
ENGINEERING

&

TECHNOLOGY PAGE NO:


SUBJECT:




YEAR/SEMESTER:

BRANCH:

NAME OF THE FACULTY:

UNIT3


MICROPROGRAMMED CONTROL

Control Memory

Microprogram


Program stored in memory that generates all the control signals required to execute the
instruction set Correctly
.

Consists of microinstructions
.it

Contains a control word and a
sequencing word

Control Word
-

All the control information required for one clock cycle

Sequencing Word
-

Information needed to decide

the next microinstruction address


-

Vocabulary to write a microprogram

Control Memor
y(Control Storage: CS) Storage in the microprogrammed control unit to store the
microprogramWriteable Control Memory(Writeable Control Storage:WCS)

CS whose contents
can be modified
,

Allows the microprogram can be changed
,

Instruction set can be changed or

modified

ADDRESS SEQUENSING

Sequencer (Microprogram Sequencer)



A Microprogram Control Unit that determines
t
he Microinstruction Address to be executed n
the next clock cycle



LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
49


ame of faulty:sayyada mubeen & chaitanya

page no
49





CONDITIONAL BRANCHING

Unconditional Branch


Fixing the value of one status bit at the input of the multiplexer to 1

Conditional Branch


If
Condition

is true, then
Branch
(address from




the next address field of the current microinstruction)




else
Fall Through


Conditions to Test: O(overflow), N(negative),


Z(zero), C(carry), etc.

LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
50


ame of faulty:sayyada mubeen & chaitanya

page no
50






MICROPROGRAMMED CONTROL



LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
51


ame of faulty:sayyada mubeen & chaitanya

page no
51




MICROINSTRUCTION FORMAT


-

Control Information
,

Sequencing Information
,

Constant


Information which is useful
when feeding into the system
.

These information needs to be organized in some way for Efficient use of the microinstruction
bits


Fast decoding

Field Encoding


-

Encoding the microinstruction bits


-

E
ncoding slows down the execution speed


due to the decoding delay


-

Encoding also reduces the flexibility due to


the decoding hardware



SYMBOLIC MICROINSTRUCTIONS


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
52


ame of faulty:sayyada mubeen & chaitanya

page no
52







Symbols are used in
microinstructions as in assembly language




A symbolic microprogram can be translated into its
binary equivalent
by a microprogram

assembler.

Sample Format


five fields:

label; micro
-
ops; CD; BR; AD






CD:

one of {U, I, S, Z}, where

U: Unconditional Branch





I: Indirect address bit





S: Sign of AC






Z: Zero value in AC

BR:

one of {JMP, CALL, RET, MAP}


AD:

one of {Symbolic address, NEXT,
empty}

SYMBOLIC MICROPROGRAM
-

FETCH ROUTINE

During FETCH, Read an instruction from memory

and decode the instruction and update PC

Sequence of microoperations in the fetch cycle:AR




PC

DR



M[AR], PC


PC + 1
,
AR


DR(0
-
10), CAR(2
-
5)


DR(11
-
14), CAR
(0,1,6)


0

SYMBOLIC MICROPROGRAM



Control Storage: 128 20
-
bit words




The first 64 words: Routines for the 16 machine instructions




The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)




Mapping: OP
-
code X
XXX into 0XXXX00, the first address for the 16 routines


LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
53


ame of faulty:sayyada mubeen & chaitanya

page no
53







LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
54


ame of faulty:sayyada mubeen & chaitanya

page no
54






NANOSTORAGE AND NANOINSTRUCTION


The decoder circuits in a vertical microprogram storage organization can be replaced by a ROM


=> Two levels of control storage

First level
-

Control Storage




Second level
-

Nano Storage


Two
-
level microprogram First level
Vertical

format Microprogram Second level


-
Horizontal

format Nanoprogram
,

Interprets the microinstruction fi
elds, thus converts
a vertical
microinstruction format into a

horizontal
nanoinstruction format.



LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
55


ame of faulty:sayyada mubeen & chaitanya

page no
55




TWO
-
LEVEL MICROPROGRAMMING
-

EXAMPLE



Microprogram: 2048 microinstructions of 200 bits each With 1
-
Level Control Storage: 2048 x
200 = 409,600 bits


Assumption:256 distinct microinstructions among 2048

* With 2
-
Level Control Storage:


Nano Storage: 256 x 200 bits to store 256 distinct nanoinstructions


Control storage: 2048 x 8 bits


To address

256 nano storage locations 8 bits are needed

* Total 1
-
Level control storage: 409,600 bits


Total 2
-
Level control storage: 67,584 bits (256 x 200 + 2048 x 8)





























LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
56


ame of faulty:sayyada mubeen & chaitanya

page no
56




COURSE FILE


LORDS INSTITUTE OF
ENGINEERING

& TECHNOLOGY PAGE NO:


SUBJECT:





YEAR/SEMESTER:

BRANCH:

NAME OF THE FACULTY:

UNIT
-
V



THE MEMORY SYSTEM


Basic concepts semiconductor RAM memories

A semiconductor random access memory system for use in a processor system is adapted to
operate


with a magnetic disc storage device, such as the so
-
called floppy
-
disc store. A
semiconductor RAM has data input/output terminals and address terminals for writing data into
or reading data out of a storage location that is addressed by an address signal
supplied to the
address terminals. Track and sector address


registers are coupled to the processor system for
receiving and storing the typical track and sector


address signals normally generated in the
system. A counter counts timing pulses to produce a

count

signal, which timing pulses are
generated by a timing control circuit. An address synthesizer is coupled to the track and sector
address registers and also to the counter for synthesizing a RAM address signal from


the stored
track and sector addre
ss signals as well as the count signal and for supplying this RAM address


signal to the RAM address terminals to access the RAM storage location which is addressed
thereby.

Thus, when the processor system generates the typical track and sector address si
gnals normally
used with a


floppy disc store, such track and sector address signals are used to address a typical
semiconductor RAM.

Random
-
access memory

(
RAM
) is a form of
computer data storage
. Today, it takes the form of
integrated circuits

that
allow stored
data

to be accessed in any order (that is, at
random
).

"Random" refers to the idea that any piece of data

can be returned in a
constant time
, regardless
of its physical location and whether it is related to the previous piece of data.

The word "RAM" is often associated with
volatile

types of memory (such as
DRAM

memory
modules
), where

the information is lost after the power is switched off. Many other types of
memory are RAM as well, including most types of
ROM

and a type of
flash memory

called
NOR
-
Flash
.

Types of RAM



LORDS
INSTITUTE OF ENGINEERING AND TECHNOLGY

PAGE NO
57


ame of faulty:sayyada mubeen & chaitanya

page no
57






Top L
-
R,
DDR2

with heat
-
spreader, DDR2 without heat
-
spreader, Laptop DDR2, DDR, Laptop
DDR


1 Megabit chip
-

one of the last models developed by
VEB Carl Zeiss Jena

in 1989

Modern types of
writable

RAM generally store a
bit of data

in either the state of a
flip
-
flop
, as in
SRAM

(static RAM), or as a
charge

in a
capacitor

(or
transistor

gate)
, as in
DRAM

(dynamic
RAM),
EPROM
,
EEPROM

and
Flash
. Some types have circuitry to detect and/or correct random
faults called
memory errors

in the stored data, using
parity bits

or
error correction codes
. RAM
of the
read
-
only

type,
ROM
, instead uses a metal mask to permanently enable/disable selected