Dr. Kimberly E. Newman
Hybrid Embedded Systems
Textbook Chapter 5
II Processor Reference Handbook
Chapter 1 & 2
Homework Assignment #1 is available.
Assignment is due next week before class.
Submit through Blackboard since there will be code involved
that needs to be verified.
Turn in signed verification sheets for Lab #1 to Dan for
recording in Blackboard.
Lab #2 will cover the LCD peripheral and interfacing to
external memory (SDRAM).
Field Programmable Devices
The fundamental piece of a configurable logic device is a
Figure 5.20 on page 213 shows an overview of the
components in a simple configuration.
has a programmable register that an be either
a D, T, JK and SR flip
flop with individual clear and clock
Input to the
is configured through the logic array.
Eight product terms form a programmable AND array that
feeds an OR gate for combinatorial logic implementation.
And XOR gate is provided to allow for inversion of the output.
Routing and use of clocks and output signals are also
controlled through configuration.
Complex Programmable Logic
Multiple PLDs are placed in a single device as shown on page 214 in fig
Typically the CPLD has an EEPROM included so that the configuration is
not lost when power is removed.
Look at the Data Sheet for the MAX II
(from the data sheet on the last slide)
Logic Array Blocks (LAB)
CPLD Logic Element
Field Programmable Gate Arrays
(textbook section 5.4)
An FPGA is more flexible than a CPLD.
The logic blocks in an FPGA are connected by wiring
channels that are much smaller than those of a CPLD.
There are many more logic blocks available in the
Memory blocks are also available that can be
configured as general purpose RAM.
based that can be programmed through the
A serial PROM can be used to provide configuration
information on power up
The EPF10K70 has a total of 70,000 typical gates that
include logic and RAM.
The entire array contains 468 Logic Array Blocks
(LABs) arranged into 52 columns and 9 rows.
Cyclone FPGA (pg 223 )
This processor is based on a 1.5 V, 0.13µm all
copper SRAM process.
Densities can reach up to 20,060 logic elements and up
to 288 Kbits of RAM.
The devices supports the creation of phase
(PLLs) for clocking and a dedicated double data rate
(DDR) interface to meet DDR SDRAM and fast cycle
RAM (FCRAM) memory requirements.
We are using the EP2c35F672C6N with the DE2 board.
II Processor System basics
(info from the PRH)
General purpose RISC processor core
bit instruction set, data path, and address space
32 external interrupt sources
instruction 32x32 multiply and divide producing a 32
result (Dedicated instructions for computing 64
bit and 128
products of multiplication)
point instructions for single
Single Instruction barrel shifter
Interfaces to off
chip memories and peripherals
II Processor System basics
assisted debug module enabling processor
start, stop, step, and trace under integrated development
environment (IDE) control
II Embedded Logic Analyzer
Memory Management Unit (MMU)
Memory Protection Unit (MPU)
Performance up to 250 DMIPS
Example of a
II processor system
Pin locations on the FPGA layout can be moved to
make traces smaller for external access to the
Glue logic on the FPGA can be implemented.
On the larger
II processor system
consumes on the order of 5% of the on board resources.
Additional cores and peripherals can be included in a
design to enhance the system performance
II architecture describes an instruction set
architecture (ISA). The ISA in turn necessitates a set of
functional units that implement the instructions.
II processor core is a hardware design that
II instruction set and supports
the functional units described in this document.
The processor core does not include peripherals or the
connection logic to the outside world.
II Processor Core Block Diagram
Arithmetic logic unit (ALU)
Interface to custom
Memory management unit
Memory protection unit
Instruction and data cache
interfaces for instructions
JTAG debug module
II architecture supports a
There are thirty two 32
Up to thirty two 32
bit control registers with supervisor
and user modes to allow system code to protect control
registers from errant applications.
Allows for the future additional of floating
Arithmetic Logic Unit
Operates on data stored in general
Operations take one or two inputs from registers and stores a result
back in a register.
The ALU supports addition, subtraction, multiplication,
and division on signed and unsigned operations
The ALU supports
the equal, not
equal, and less
than relational operations (==, !=, >=, <) on
signed and unsigned operands.
The ALU supports AND, OR, NOR, and XOR logical
Shift and Rotate
The ALU supports shift and rotate operations,
shift/rotate data by 0 to 31 bit positions per instruction.
The ALU supports arithmetic shift right and logical shift
right/left. The ALU supports rotate left/right.
Some core implementations do not provide support for the entire
An exception is generated so that the instruction can be emulated
To determine a list of potentially unimplemented instructions refer
to the Programming Model chapter of the
defined custom instructions are allowed. The ALU connects
directly to the new instruction logic so that use and access are the same
as the native instructions.
For further information refer to the
II Custom Instruction User
Floating Point operations
floating point is
supported as specified
in the IEEE Std 754
Floating point operations do require many more
elements in the FPGA.
Designers should be aware of tradeoffs in the HW/SW
Speed vs. resource usage should be evaluated for a
Hybrid embedded systems are growing in need and facilitate the grand
challenges of tomorrow.
Transportation, environmental management and health care
applications are just a few examples of where better designs are
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