TCP/IP STACK VIP

hollowtabernacleNetworking and Communications

Oct 26, 2013 (4 years and 12 days ago)

106 views

Copyright @ 2002 ControlNet (I) Pvt. Ltd. All rights are reserved
1
www.controlnetindia.com

T
T
T
C
C
C
P
P
P
/
/
/
I
I
I
P
P
P



S
S
S
T
T
T
A
A
A
C
C
C
K
K
K



V
V
V
I
I
I
P
P
P
Verification Intellectual Property For OpenVera
TM
F
F
F
e
e
e
a
a
a
t
t
t
u
u
u
r
r
r
e
e
e
s
s
s
￿ Support for protocols based
on TCP, IP, UDP, ICMP
(echo and echo reply
packets)
￿ Randomized real network
packet traffic
g
eneration an
d
analysis
￿ Provision to induce various
error conditions
￿ Tested with silicon proven
DUT
￿ Extensive compliance test
suite available
￿ Unmatched support and
deployment
￿ Based on the modeling
architecture by Synopsys
F
F
F
o
o
o
r
r
r



M
M
M
o
o
o
r
r
r
e
e
e



I
I
I
n
n
n
f
f
f
o
o
o
r
r
r
m
m
m
a
a
a
t
t
t
i
i
i
o
o
o
n
n
n
ControlNet (India) Pvt. Ltd
Email: sales@controlnet.co.in
Tele: +91 832 2883601
Fax: +91 832 2783614
www.controlnetindia.com
S
S
S
p
p
p
e
e
e
e
e
e
d
d
d
s
s
s



u
u
u
p
p
p



V
V
V
e
e
e
r
r
r
i
i
i
f
f
f
i
i
i
c
c
c
a
a
a
t
t
t
i
i
i
o
o
o
n
n
n
ControlNet Verification Intellectual Property (IP) assists
users to speed up the verification process of their
ASIC/SOC. Verification IP combines the domain
knowledge with reusability, random verification
methodology, and other advanced capabilities of
OpenVera
TM
,

providing higher quality and increased
productivity in the design verification flow.
S
S
S
u
u
u
p
p
p
p
p
p
o
o
o
r
r
r
t
t
t



f
f
f
o
o
o
r
r
r



I
I
I
n
n
n
d
d
d
u
u
u
s
s
s
t
t
t
r
r
r
y
y
y



S
S
S
t
t
t
a
a
a
n
n
n
d
d
d
a
a
a
r
r
r
d
d
d
Verification IP are industry standard compliant and
tested with silicon proven DUT's. To use the verification
IP, in-depth knowledge of the particular standard is not
required. This helps the verification team to concentrate
their efforts on generating powerful test cases.
Verification IP is based on the OpenVera model
architecture, and is fully interoperable with user
testbenches and other third party IP.
Each verification IP package includes full documentation,
examples how to integrate in verification environments, a
compliance test suite, and full customer support.
DUT
D
D
U
U
T
T
T
T
C
C
P
P
/
/
I
I
P
P
S
S
T
T
A
A
C
C
K
K
I
I
n
n
t
t
e
e
r
r
f
f
a
a
c
c
e
e
T
T
C
C
P
P
/
/
I
I
P
P
T
T
r
r
a
a
f
f
f
f
i
i
c
c
G
G
e
e
n
n
e
e
r
r
a
a
t
t
o
o
r
r
T
T
C
C
P
P
/
/
I
I
P
P
T
T
r
r
a
a
f
f
f
f
i
i
c
c
M
M
o
o
n
n
i
i
t
t
o
o
r
r
T
T
e
e
s
s
t
t
S
S
u
u
i
i
t
t
e
e
A
A
n
n
d
d
C
C
o
o
n
n
s
s
t
t
r
r
a
a
i
i
n
n
t
t
s
s
Copyright @ 2002 ControlNet (I) Pvt. Ltd. All rights are reserved
2
www.controlnetindia.com
G
G
G
e
e
e
n
n
n
e
e
e
r
r
r
i
i
i
c
c
c



A
A
A
r
r
r
c
c
c
h
h
h
i
i
i
t
t
t
e
e
e
c
c
c
t
t
t
u
u
u
r
r
r
e
e
e
Verification IP architecture supports multiple instantiation in a testbench
environment with any other third party IP. With the use of various method
calls, users can create advanced robust test suites and scenarios. Output log
reports assist users in analyzing the results. High-level and abstract
randomization methods allow users to use stimulus generation without
intricate knowledge of underlying protocols.
ControlNet’s vast experience in TCP/IP technology ensures Verification IP
compliance to the standard. Our expertise in IP development and complete
understanding of the verification needs and flow, enable us to deliver a
highly robust and flexible test environment for today’s complex ASIC and
SOC.
This verification IP supports all major functionality of the TCP, IP, UDP and
ICMP protocol. Users can generate different packets including error injection.
All transmitted and received packets are monitored and recorded in log files.
All received packets are decoded and marked. The stimulus model can
generate automatic response to the incoming packets. Error conditions can be
induced at various layers of testing.
TCP/IP verification IP includes an extensive compliance test suite that
facilitates comprehensive debugging and robust protocol testing.
D
D
D
e
e
e
l
l
l
i
i
i
v
v
v
e
e
e
r
r
r
a
a
a
b
b
b
l
l
l
e
e
e
s
s
s
￿
Fully verified TCP/IP stack Verification IP in object form
￿
Documentation – Reference manual and quick reference guide
￿
Extensible compliance test suite with documentation.
￿
Technical support to integrate the Verification IP into the user’s test
environment
All trademarks are the property of their respective owners.

Verification Intellectual Property For OpenVera
T
M
T
T
T
C
C
C
P
P
P
/
/
/
I
I
I
P
P
P



S
S
S
T
T
T
A
A
A
C
C
C
K
K
K



V
V
V
I
I
I
P
P
P