ECE 463 Digital Communications Laboratory
February 20, 2012
Copyright 2012 University of Illinois
1
Lab 6: The PLL Controller (Filter)
Introduction
This week, we continue our investigation into Phase

Locked Loops. We use our knowledge of the
relationship between the Loop Controller (Filter),
, and the closed

loop transfer function,
, to
gain valuable insight into PLL design choices. With Software

Defined Radio, our PLL implementation
will be digital. We will generally design our loops in the Laplace domain (continuous

time assumption)
and carefully map them into the Z domain (discrete

t
ime).
Objectives
Understand the relationship between Loop Filter characteristics and those of the PLL's closed

loop transfer function.
Study these relationships using the linearized model coded in LabVIEW.
Measure theoretical dynamic properties of the PL
L including rise time, settling time, and
overshoot.
Make observations of the PLL in controlled operation including pull

in range, hold

in range, and
steady

state phase error.
Insert the PLL in an operable system and validate the simulated predictions.
Learn and understand the concept of false lock.
Reconcile parameters determined by theory, simulation and deployment. Form strong hypotheses
to explain any deviations.
Prelab
Reading: Handouts for PLLs from
Phase

Locked Loops: Overview
through
Digital
PLL, Loop Controller
Design
. As described in your notes, PLL "order" is the largest power of the Laplace variable
in the
denominator of the PLL's closed loop transfer function,
. PLL "type" is the number of poles at the
origin (
) in the open

l
oop gain of the PLL (that is, break the loop and find that the gain through the
loop is
). Type will always be at least 1 because of the VCO which has a pole at the origin. When
the loop controller,
, has poles at the origin, you must
add that number to get the type.
ECE 463 Digital Communications Laboratory
February 20, 2012
Copyright 2012 University of Illinois
2
Control
Design
Loop Filter,
F(s)
Loop Gain,
A(s)
System
Type
Loop Transfer Function,
H(s)
System
Order
Proportional
Type 1
1
st
order
PI
PID
2nd order
Lag

Lead
1.
For each Loop Control Filter listed in the table above, complete the table by
a.
comp
uting the open

loop gain A(s),
b.
stating the PLL
type
,
c.
computing the closed

loo
p transfer function, H(s), and
d.
stating the closed

loop
order
.
2.
Use the cou
rse notes to design an analog PLL with both a Proportional and a Proportional

plus

Integrator controller. Both should have 1 millisecond rise time and (less than) 5 milliseconds
settling time. Assume a damping factor of
for the PI

controlled syste
m.
3.
Assuming that the sampling rate is given by
Samples/sec,
discretize your analog
PLL designs.
4.
Specify the
filter coefficients for each of the
digital PLL controllers below
.
ECE 463 Digital Communications Laboratory
February 20, 2012
Copyright 2012 University of Illinois
3
Procedure
Download
ECE463.zip
, the once

again updated zipped library of code for ECE463. Remember that you
should rename any code that you
modify
from 463 filename.vi to
your_initials
filenam
e.vi.
ECE 463 Digital Communications Laboratory
February 20, 2012
Copyright 2012 University of Illinois
4
The Proportional

Controlled PLL
The mathematical model discussed above was based on the linearized models of the phase detector and
VCO. Now, we implement a real

life digital PLL that has non

ideal (non

linear) characteristics in the
phase detec
tor as well as discrete

time limitations on the NCO.
1.
Open and re

name
your VI from the previous lab. Call this lab
your_initials
Lab 6 PLL Loop
Control.vi
.
2.
Insert 463 PLL.vi. This is a polymorphic VI intended to replace 463 PLL full.vi from last time.
3.
Alter the VI so that it stops after the NCO mode is switched from Disabled to Normal. This will
allow us to freeze the reaction of the control voltage,
.
4.
Add a plot Post PLL to your observation tab.
5.
Set your Forward Coefficients to implement the P
roportional Loop controller discussed in the
pre

lab exercises.
6.
Start your transmitter, then start your receiver. Like last week, you should observe your AGC
adapt and you should see a static phase error. Use your control knob to change the static phase
ECE 463 Digital Communications Laboratory
February 20, 2012
Copyright 2012 University of Illinois
5
error to negative 45 degrees.
7.
Now change your NCO to Normal mode, watching the Post PLL constellation lock. The receiver
should stop on its own.
8.
Observe the control voltage,
, which will be proportional to the loop response for the
proportional (
P
) control. Does it appear to differ in any way from that of the loop response
observed earlier? Note that you can use your MATLAB© plots to visually compare the two
curves. Save the data in
so that you can compare it to theory in the post

lab
exer
cises
.
9.
What is the steady state phase error for this simulation?
10.
Change the initial offset frequency to 100 Hz
by setting the bias voltage to the proper amount
and
run the VI.
11.
Again, observe the loop response and record any deviations from the earlier pre
diction and record
the steady state phase error. Save your loop response data to a file, appropriately named, for use
in the
p
ost

lab
exercises
.
12.
Increase the initial frequency offset to 500 Hz and run the VI. Again, observe the loop response
and record an
y deviations from the earlier prediction. Does the loop obtain lock?
13.
Recode your VI so that it runs continuously. While observing the Post PLL graph, determine the
highest control

voltage bias that can be tolerated by this PLL while maintaining lock. Wh
at is the
steady

state phase error for this offset? What does this bias voltage equate to in Hz? What is the
significance of the value of the steady

state phase error for this worst

case frequency offset?
Hold

in and Pull

in Range
1.
The hold

in frequency,
, is the range over which the frequency difference between the
NCO and the reference can be increased (slowly, without losing lock) until PLL lock can no
longer be maintained. In the case of the Proportional controller, the hold

in range cor
responds to
the point when the steady

state phase error is beyond the linear, positive

sloped portion of the
phase detector’s “S

curve.” Measure
. Increment the
bias voltage
slowly (being careful
not to
step so large as to “slip lock
”
).
2.
The
highest offset frequency for which the loop locks
from an unlocked
this
. What is the
steady

state phase error for the locked PLL when the offset frequency is
?
3.
For the
PI

controlled loop:
A.
Observe the loop response for a 45
degree phase offset and zero frequency offset.
Comment on any unusual observations. Record the final phase error.
B.
Observe the loop response for a 45 degree phase offset
and
a 100 Hz frequency offset.
Comment on any unusual observations. Record the final
phase error.
C.
Find and record
.
ECE 463 Digital Communications Laboratory
February 20, 2012
Copyright 2012 University of Illinois
6
D.
Find and record
. Careful! For the PI controller, this is much different than for
the P controller.
4.
Consider the separate loop gain control,
. This gain is applied directly to the output of
the loop
filter. For the Proportional controller and the offset frequency set to
, increase
(in the
orange box) from 1 to 3. What happens?
5.
Discuss how
phase

plane portraits
might be empirically measured. Do this for
Extra Credit!
6.
Incrementally, set
(you don't necessarily have to do them all) and
observe the response. How does
affect the response? Comment both on the positive and on
the negative aspects of choosing a large loop gain.
R
eal

time PLL Investigation
1.
Open the 463 PSK
Transmitter
.
2.
Run t
he PSK
Transmitter
from a second machine
so that the generator operates using its own
on

b
oard. This modification results in asynchronous carrier LOs at the transmit and receive sides.
With as
ynchronous LOs, the received constellation is guaranteed to rotate giving us a prime
situation to test our PLL design.
3.
Start the PSK Gen
erator.
4.
Press Run and observe the received constellation with the NCO in
disabled
mode.
5.
Use this VI to investigate th
e pull

in and hold

in ranges of the PLL using each of the two loop
filters listed above in
bold
. Pull

in range refers to the ability of the PLL to acquire frequency lock
given a known frequency offset between the carrier of the received signal and the NCO.
This can
be accomplished by setting the NCO to
normal
closed loop
mode and typing in the desired
frequency offset and hitting return
.
Hold

in range assumes that the NCO is already frequency
locked to the reference and the offset is slowly increased until
the loop can no longer maintain the
lock.
6.
Measure the pull

in and hold

in ranges and explain the behavior. Also, record the steady state
frequency error for each controller measured at 100 Hz offset.
7.
Verify that your measurements agree with the predicti
ons of the earlier sections. If they are not in
agreement, see if you can rationalize what is different between the methods of obtaining them.
ECE 463 Digital Communications Laboratory
February 20, 2012
Copyright 2012 University of Illinois
7
Postlab
Linearized Model Investigation
For both the P and the PI controller, test your designs for
in MATLAB© by following the
instructions below.
1.
Record the rise time (
) defined as the time required for the Loop response to rise from 10%
to 90% of its steady state value.
2.
Record the settling time (
) of the loop response defined as th
e time for which the response has
settled indefinitely to within 1% of its steady state value.
3.
Record the amount of overshoot,
, as a percentage of the steady state value of the loop
response (eg. if it shoots 10% above the final value,
and
for no overshoot
).
4.
Repe
at your measurements for the PI
and 2
nd

order
controllers
.
Emperical
Investigation
1.
How does the discrete loop gain constant,
, enter into the equation for loop transfer function,
?
2.
Describe what factors affect the value of
. How about
?
3.
Plot the measured loop response against the theoretical response of
as measured by the
control voltage. Comment on the comparison and explain any deviations.
4.
Disc
uss the differences between the two control filters.
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