VLSI Design Lecture 4-b: Layout Extraction

heartlustElectronics - Devices

Nov 2, 2013 (3 years and 9 months ago)

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VLSI Design

Lecture 4
-
b: Layout Extraction

Mohammad Arjomand


CE Department

Sharif Univ. of Tech.



Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 50


Layout can be very time consuming


Design gates to fit together nicely


Build a library of standard cells


Must follow a technology rule



Standard cell design methodology


V
DD

and GND should abut (standard height)


Adjacent gates should satisfy design rules


nMOS at bottom and pMOS at top


All gates include well and substrate contacts

Gate Layout

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 50

Example: Inverter

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 50

Layout using Electric

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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Horizontal N
-
diffusion and p
-
diffusion strips


Vertical polysilicon gates


Metal1 V
DD

rail at top


Metal1 GND rail at bottom


32


by 40


Example: NAND3

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 50

Example: NAND3

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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Stick diagrams

help plan layout quickly


Need not be to scale


Draw with color pencils or dry
-
erase markers

Stick Diagrams

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

Slide
8

of 50


Stick diagrams

help plan layout quickly


Need not be to scale


Draw with color pencils or dry
-
erase markers

Vin

Vout

VDD

GND

Stick Diagrams

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

Slide
9

of 50


A
wiring track

is the space required for a wire


4


width, 4


spacing from neighbor = 8


pitch


Transistors also consume one wiring track


Wiring Tracks

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 50


Wells must surround transistors by 6



Implies 12


between opposite transistor flavors


Leaves room for one wire track

Well spacing

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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Estimate area by counting wiring tracks


Multiply by 8 to express in


Area Estimation

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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12

of 50


Sketch a stick diagram for O3AI and estimate area




Example: O3AI

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

Slide
13

of 50


Sketch a stick diagram for O3AI and estimate area




Example: O3AI

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

Slide
14

of 50


Sketch a stick diagram for O3AI and estimate area




Example: O3AI