Chapter 7
Differential Amplifiers and Integrated
Circuit (IC) Amplifiers
Discrete and Integrated Circuits
A discrete circuit is constructed of components that are manufactured separately.
Later, these components are connected together, by conductors like wires, in a
circuit board or a printed circuit board (PCB).
On the other hand, in an integrated circuit, the components and their inter

connections are manufactured concurrently by a sequence of processing steps.
The types of components that are available and their practical values depend
heavily on the approach taken for implementation. (for example, the capacitors in
discrete circuits can be in the range of 1pF to 1F, but only 1pF to 100pF in ICs. Also,
inductors are almost impractical in ICs. But in ICs, matching of components is much
easier)
See table 7.1 in page 412 for detail.
Applications of discrete circuits will persist especially for some special circuits that
are to be mass produced, but today the bulk of electronic systems are based on
ICs.
Processing steps in manufacturing ICs incur cost and failures and are usually
different for different technologies.
BJT technology are used more for high

quality analog circuits, while MOS are more
for general analog circuits and digital circuits. Today, semiconductor industry can
manufacture both BJT and MOS on the same chip, called BiCMOS technology.
Figure 7.1
The current mirror.
DC biasing for Integrated Circuits
Different from biasing of discrete circuits, resistors and capacitors are “expensive” in
terms of cost and chip area, are therefore avoided whenever possible.
For amplifier circuits, the BJT transistors operate in active region.
The following circuits show how matched transistors, when combined with a few
resistors, can act as current sources that are useful in biasing IC amplifiers.
Collector of Q1 is connected to its base. Thus , and Q1 is in the
active region. If is larger than 0.2V, Q2 is also in the active region.
See page 415

416, it can be shown that
Figure 7.1
The current mirror.
DC biasing for Integrated Circuits II
To a first

order approximation, the base current of Q2 is independent of the output
voltage , therefore the output characteristics is almost identical to one of the
collector characteristic curves for Q2.
An important specification of a current source is the range of output voltage for which
the output current is approximately constant, which is called
compliance range
.
Another important specification of a current source is its dynamic output resistance,
which is the ratio of the incremental voltage divided by the incremental output current
(ideally it should be infinite).
In small

signal equivalent circuit, the current source is replaced by its dynamic
resistance.
Figure 7.2
Emitter follower with bias current source.
Biasing an Emitter Follower
An example of how the current mirror can help establish the bias point of an IC
amplifier is shown below.
The current source is formed by R, Q1 and Q2, while Q3 is an emitter follower
amplifying the input signal and delivering it to the load.
Often, we can simplify the circuit diagram as in Figure7.2(b).
Note:
(1) the amplifier is direct

coupled
compared to AC

coupling in
discrete amplifiers
(2) Output voltage is

0.7V for input
voltage of zero. In this case, the
circuit displays a DC offset, which
is not desirable. This problem can
be solved or reduced by the circuit
shown in the next slide.
Figure 7.3
The offset voltage can be reduced by cascading a complementary (
pnp
) emitter follower.
Biasing an Emitter Follower: reducing offset
A simple way to reduce offset for this follower is to cascade a second stage
consisting of a pnp emitter follower as shown in the figure below.
Note that in discrete circuits, offset is not an issue as a coupling capacitor is used.
Figure 7.4
Doubling the junction
area of a BJT is equivalent to connecting
two of the original BJTs in parallel.
Effects of transistor area on current mirror
Doubling the area of a transistor is the same as
connecting two of the original transistors in parallel, as
shown in the Figure 7.4.
The output current of a current mirror for which the
relative junction areas of the transistors are A1 and A2
is given by
Study example 7.1 in page 418.
Figure 7.5
Current mirror for Examples 7.1.
Figure 7.9
Collector characteristic of
Q
2
, illustrating the Early voltage.
Figure 7.7
Output characteristic for the
current mirror of Figure 7.5.
Figure 7.8
Dynamic output resistance of the
current mirror of Figure 7.5.
Figure 7.10
The Wilson current source,
which has a high output resistance.
The Wilson current source
An improved circuit, called Wilson current source,
with higher output impedance that the previous
current mirror is shown in the Figure.
For the Wilson current source, the following holds:
A1, A3 are the relative junction areas of the Q1
and Q3 respectively. (see page 421)
Figure 7.11
The Widlar current source,
which is useful for small currents.
The Widlar current source
When the desired current is small, the Widlar current
source may be a better alternative, as shown in the
Figure.
For Widlar current source, the following holds (see
page 422):
See example 7.3 in page 423.
Figure 7.12
Typical biasing circuit for a bipolar IC.
The combined current sources
In an Integrated Circuit amplifier, several current sources use the same reference
current, as shown below.
The current through R1 is the reference current for all four current sources. Q1, Q2
forms a current mirror, and Q1, Q3 forms a Widlar source. Notice the pnp current
source by Q4, Q5 and Q6.
Figure 7.15
NMOS current mirror.
IC biasing with MOSFET
The BJT current sources have counterparts
constructed with MOSFET.
The shown MOSFET current mirror is very similar to
the BJT current mirror.
In typically cases, the MOSFET M1 operates in
saturation region, as drain

to

gate voltage is zero.
Assuming the transistors are identical and that the
output voltage is large enough so that M2 is in
saturation as well. The current
By using devices with different W/L ratios, circuits
having output current equal to a predetermined
constant times reference current can be designed.
Figure 7.16
NMOS Wilson current source.
IC biasing with MOSFET
An improved current source is shown below,
which has higher output resistance than the
simple current mirror.
The output current is related to the reference
current by the equation below as well (assuming
the transistors operating in saturation region):
The reference current
I
1
may be approximated by
Figure 7.22
Basic BJT differentiial amplifier.
Emitter

coupled differential pair
The emitter

coupled differential pair is a
very important circuit that is used many
bipolar analog integrate circuits.
The circuit is shown in the figure and the
two transistors are assumed identical. The
current source
I
EE
is typically implemented
as a current source circuit discussed
before (eg. Current mirror, wilson current
source).
The input voltages vi1 and vi2 can be
considered to be composed of a differential
signal vid and a common mode signal vicm
defined below:
Differential output voltage is defined as
Figure 7.23a
Basic BJT differential amplifier with waveforms.
Emitter

coupled differential pair II
First, consider the two input signal vi1 and vi2 are equal. Then the differential input
voltage vid is 0 and we have a pure common

mode input signal.
In this case, the current IEE splits equally between the Q1 and Q2, therefore vod=0.
In other words, the circuit does not respond to the common

mode component of the
input.
Figure 7.23b
Basic BJT differential amplifier with waveforms.
Emitter

coupled differential pair III
For a pure differential input (when vicm=0), it can be shown the a non

zero
differential output voltage vod is resulted, as a differential input signal steers
I
EE
twoard one side or the other.
In summary, the circuits rejects common

mode input and responds to the differential
input. In amplifiers, a small differential input signal is amplified to a differential output
signal.
Figure 7.24
pnp
emitter

coupled pair.
Emitter

coupled differential pair: pnp version
Figure 7.25
Collector currents versus differential input voltage.
Signal transfer characteristics I
See page 437 for derivation of the collector current for the emitter

coupled
differential pair.
The following collector current versus differential input voltage can be obtained.
Note that in the plot, when vid=0, ic1=ic2. For vid>5V
T
, the current is steered almost
entirely through Q1 and similarly when vid<

5V
T
, the current is entirely through Q2.
Figure 7.26
Voltage transfer characteristic of the BJT differential amplifier.
Using the previous equation of , one can find
A plot of this transfer characteristics is shown in the following figure. The curvature
Shows that the differential amplifier can distort a signal if the amplitude is too large.
For input voltage less V
T
, the characteristics is quite straight giving linear gain.
Signal transfer characteristics II
Figure 7.27
Differential amplifier with emitter
degeneration resistors.
Emitter degeneration
Sometimes it is advantageous to add emitter generation resistor R
EF
to the circuit,
as shown in the Figure.
There resistors have the disadvantage of reducing the differential voltage gain of
the circuit. However, two reasons for this is to increase input impedance and to
reduce distortion due to the nonlinearity of the BJTs.
The right figure shows the transfer characteristic of the differential amplifier
(R
EF
=40V
T
/I
EE
).
Figure 7.28
Voltage transfer characteristic with
emitter degeneration resistors. R
EF
= 40(
V
T
/
I
EE
).
Figure 7.29
Either a balanced or single

ended output is available
\
break from the differential amplifier.
Balanced versus single

ended outputs
The output of a differential amplifier can be balanced, in which case the output
voltages from both collectors are connected to the inputs of another differential
amplifier.
On the other hand, the output can be taken from one collector, in which case we
say the output is single

ended. If a single

ended output is desired, there is no
need for a resistor in the collector of the other resistor. (resistor at collector of Q1
omitted as shown).
Figure 7.30
Emitter

coupled pair
with current

mirror load.
The current mirror as a load
The following figure shows a variation of the
emitter

coupled pair in which the collector
resistors are replaced by a current mirror.
This circuit is particularly favored in ICs, as
transistors are much cheaper than resistors.
A simple analysis by assuming large so
that base currents of Q3 and Q4 are
neglected, results in the equation as follows:
For is approximately proportional
to vid. Notice furthermore that the common

mode input component does not affect the
output current.
Figure 7.33
Small

signal equivalent circuit
for the differential amplifier of Figure 7.27.
(
R
EB
is the output impedance of the current source
I
EE
.)
Small

signal analysis of the Emitter

coupled differential pairc
Using small

signal analysis, we can derive expressions for voltage gain, input
impedance and output impedance of the emitter

coupled differential pair.
The small

signal equivalent circuit for the differential pair is shown below by
replacing the transistors by their small

signal models.
Note that power supply has
been shorted to GND in
small

signal circuit.
Also note that the I
EE
current source is replaced
by a resistance R
EB
in the
small

signal circuit, as
practical current sources
has a finite output
impedance.
Figure 7.34
Half

circuit for a differential input signal.
Small

signal analysis: differential input
First, we analyze the circuit for a pure differential
input signal. Therefore the input voltage are
vi1=

vi2=vid/2.
The analysis can be simplified by observing that
the equivalent circuit is symmetrical. Due to this
symmetry and opposite polarity of the
independent sources, the voltage at point J is
zero. The circuit behavior would not change by
shorting point J to Ground.
We can then consider only the left

hand side
circuit as shown in the Figure. We need to
analyze only this half circuit as the right half is
the same except different polarity.
Figure 7.34
Half

circuit for a differential input signal.
Small

signal analysis: differential input II
The half circuit, we then find out the gain and
input impedance:
Notice that we have defined Rid as the ratio of
the entire differential voltage vid to the input
current. Thus, Rid is the input impedance
between the input terminals of the complete
circuit.
The voltage gain is:
For output impedance, we have:
Figure 7.35
Small

signal equivalent circuit with a pure common

mode input signal.
Small

signal analysis: common

mode input
When the input voltage are vi1=vi2=vicm, the equivalent circuit is depicted in the
figure. We have shown the output impedance of the current source as the parallel
combination of two resistors.
The equivalent circuit is symmetrical with respect to the dashed line including the
polarities of the signal sources. Therefore, we conclude that current
i
J
must be zero.
As such, we can open the connection and consider only left or right hand half
circuit.
Figure 7.36
Half

circuit for a pure common

mode input signal.
Small

signal analysis: common

mode input
From the half circuit, we can then
compute the gain, input impedance
and output impedance.
Note that we have defined the
common

mode input impedance to be
the voltage divided by the total current
the source must deliver to both
terminals.
The gain from a single

ended load to
common

mode input is:
As vo1=vo2=vocm.
For output impedance, we have:
Small

signal analysis: CMRR
In amplifier circuits, it is often desirable to reject common

mode signal while
amplifying the differential signal.
A measure of how well the amplifier rejects the common

mode signal relative to the
differential signal is the
common

mode rejection ratio
(CMRR). By definition, the
CMRR is ratio of the gain for the differential signal to the gain for common

mode
signal.
From results of previous results, the CMRR for the single

ended output and
balanced output can be defined respectively as follows:
It can be seen that CMRR is nearly independent of . To increase CMRR, it is
desired to select a larger value for
R
EB
and a small
R
EF
.
Figure 7.38
Addition of emitter followers to increase input impedance.
Amplifier design: how to increase input
impedance?
Figure 7.39
First attempt in Example 7.4.
An design example for high CMRR
Figure 7.40
Differential amplifier of
Example7.4 using the Wilson current source.
Figure 7.42a
Waveforms for
the differential amplifier of Example 7.4.
Figure 7.43
Source

coupled differential amplifier.
The source

coupled differential pair
Using MOSFET, we can construct an source

coupled differential pair, which is a
counterpart of the emitter

coupled differential pair using BJTs.
The main advantage of using MOSFET for a differential pair compared to BJTs is
the nearly infinite input impedance, while the disadvantage is lower gain magnitude.
The source

coupled differential pair II
Assuming the two MOSFETs are the same.
The analysis of the source

coupled differential pair proceeds in the same way as
the emitter

coupled differential pair for both common

mode signal and differential
input signal.
The transfer characteristics for drain current Id1 and Id2 are shown in the figure.
Figure 7.44
Drain currents versus
normalized input voltage.
Figure 7.45
Differential output voltage versus
normalized input voltage.
Figure 7.46
Small

signal equivalent circuit for the source

coupled amplifier of Figure 7.43.
(
Note:
R
SB
is the output resistance of the bias current source
I
.)
The source

coupled differential pair III
The small

signal equivalent circuit fir the source coupled differential pair is shown in
the figure.
The power supply is replaced by a short circuit and the resistance
R
SB
represents
the output impedance of the bias current source.
The circuit can be analyzed for differential and common

mode input signal in almost
the same way as the emitter

coupled differential pair discussed before.
Refer to results in Table 7.3 in page 462.
Figure 7.49
CMOS op amp.
An example of IC amplifier: MOS
The advantage of the amplifier is that it
can be fabricated on the same chip as
CMOS logic circuits.
The PMOS M8, M1 and M2 form a dual
current mirror that supplies bias currents
to the amplifier stages.
The resistor Rset is selected to yield the
desired reference current.
The input stage consists of transistors M3
and M4, which forms a source

coupled
differential pair. Note that Q

point currents
on M3 and M4 are approximately equal to
Iset.
Transistors M5 and M6 form a current
mirror load for the input stage.
Transistor M7 is a common

source
amplifier and M2 acts like a active load.
Figure 7.50
Small

signal equivalent circuit for the output stage consisting of
M
7
and
M
2
.
An example of IC amplifier II: MOS
The small

signal equivalent circuit for the output stage is shown below.
Note that the in the model we treated the
C
comp
as a open circuit and included the
drain

source small

signal resistance
r
d
.
Transistor M2 forms the output device of the a current mirror and its gate

to

source
voltage is pure DC with no signal component. In other words, the small signal
v
gs2
=0, therefore the current source
i
d2
=g
m2
v
gs2
is zero as well. Then we obtain
Figure 7.50
Small

signal equivalent circuit for the output stage consisting of
M
7
and
M
2
.
An example of IC amplifier III: MOS
Next, we need to analyze the source

coupled pair to find its differential voltage gain.
The small

signal equivalent circuit is shown below.
Note that source terminals of M3 and M4 are connected to ground as the circuit is
symmetrical.
Assuming the current on the small

signal rd resistors are small compared to the
current source, we can derive the following: (refer to page 467

468)
Figure 7.53
Open

loop gain versus frequency for the CMOS op amp.
Figure 7.55
A BJT op amp.
An example of IC amplifier: BJT
Q1, Q2 form a differential amplifier balanced outputs, Q3, Q4 form a differential
amplifier with single

ended outputs, Q5 is a pnp emitter amplifier an emitter
resistance R6, Q6 is an emitter follower, and finally Q7, Q8, Q9 form a double
current mirror.
Figure 7.56
R
EB
represents the output impedance of current sink
Q
8
.
Ri
= is the differential input impedance of the second stage.
Equivalent circuit for the first stage of Figure 7.55.
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