EE534 VLSI Design System Summer 2004 Lecture 11:Chapter 7

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Nov 2, 2013 (3 years and 7 months ago)

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EE534

VLSI Design System

Summer 2004



Lecture 11:Chapter 7



Layout and

Combinational MOS logic circuits design approaches


Review: Construction of PDN


NMOS devices in
series

implement a NAND function






NMOS devices in
parallel

implement a NOR function

A

B

A
• B

A

B

A
+ B

Review: Equivalent inverter: effective width to length
ratios (model I)

For the
NOR gate

the
effective
width of the drivers transistors

doubles.

That means the effective
aspect ratio is increased.

For the
NAND gate

the
effective
length of the driver transistors
doubles
. That means the effective
aspect ratio is decreased
.

.

Parallel combination

Series combination

Review: CMOS NAND gate and its inverter equivalent


Can we estimate switching
threshold of the NAND gate by
using CMOS inverter
expression for the switching
threshold?





W
N

W
N

W
P

W
P

2W
P

½ W
N

2K
P

K
n
/2

If Kn=Kp, Vth=?

Equivalent inverter:
Worse case delay design consideration


Represent complex gate as inverter for delay
estimation


Use worse
-
case delays


Example: NAND gate


Worse
-
case (slowest) pull
-
up: only 1 PMOS “on”


Pull
-
down: both NMOS “on”

W
N

W
N

W
P

W
P

W
P

½ W
N

K
P

K
n
/2

Review: CMOS NOR gate: design consideration

Two input

For N inputs

One input

Equivalent inverter


Problems with equivalent inverter method:


Need to take into account load capacitance C
L

-
Depends on number of transistors connected
to output (junction capacitances)

-
Even transistors which are off (
not included
in equivalent inverter
) contribute to
capacitance


Need to include capacitance in intermediate
stack nodes
. Worse
-
case: need to
charge/discharge all nodes


Body effect

of stacked transistors

Transistor Sizing

NAND gate

NOR gate

Transistor sizing: an approach


If MOSFET serially connected in a current path, the
overall current path resistance will be







All serially connected MOSFET can be replace with a
single MOSFET as




If the MOSFET are connected in parallel combination then,

Graph
-
based dual network


Draw network for PUN or PDN


Circuit nodes are vertexes


Transistors are edges


A

B

F

gnd

A

B

F

Graph
-
based dual network (2)


To derive dual network:


Create new node in each enclosed region of
graph


Draw new edge intersecting each original edge


Edge is controlled by inverted input


A

B

A

B

A

B

F

Stick Diagrams

Contains no dimensions

Represents relative positions of transistors

In

Out

V

DD

GND

Inverter

A

Out

V

DD

GND

B

NAND2

Dual Graph concept

C

A

B

X = C • (A + B)

B

A

C

i

j

j

V
DD

X

X

i

GND

A

B

C

PUN

PDN

A

B

C

Logic Graph

CMOS gate layout


Goal:

minimum area


Method


Minimize diffusion breaks (reduces capacitance
on internal nodes)


Align transistors with common gates above each
other in layout (minimizes poly length)


Group PMOS and NMOS transistors together


Approach:


Use Euler path method to find ordering of
transistors

in layout

Layout: Euler path method


Goal:

layout without diffusion breaks


Method for finding ordering of transistors
in layout


Euler path


Euler path


path through a graph that
traverses each edge only once


Find
common Euler path

in pullup and
pulldown graph


This gives the ordering of inputs in the
layout

Complex CMOS logic gates

Complex CMOS logic gates:
Euler path method


Layout: Euler path method

A

B

C

D

E

C

E

D

B

A

Euler path: B→A→C→E→D

B

A

C

E

D

Vcc

Gnd

F

F

1.
Order transistors gates according to
Euler path

2.
Connect Vcc and Gnd

3.
Make other connections according
to circuit diagram

Fan
-
In Considerations

D

C

B

A

D

C

B

A

C
L

C
3

C
2

C
1


Distributed RC model


(Elmore delay)

T
pHL
=0.69[R
1
C
1
+(R
1
+R
2
)C
2
+(R
1
+R
2
+R
3
)C
3
+(R
1
+R
2
+R
3
+R
4
)C
L
]


t
pHL

= 0.69 R
eqn
(C
1
+2C
2
+3C
3
+4C
L
)


Propagation delay deteriorates rapidly as
a function of fan
-
in


quadratically

in the
worst case
.

t
p

as a Function of Fan
-
In

t
pH
L

t
pL
H

t
p

(psec)

fan
-
in

quadratic
function of
fan
-
in

linear
function of
fan
-
in



Gates with a fan
-
in greater than 4 should be avoided.

t
p

t
p

as a Function of Fan
-
Out

t
p
NOR2

t
p

(psec)

eff. fan
-
out

All gates
have the
same drive
current.

t
p
NAND2

t
p
INV

Slope is a
function of
“driving
strength”

Influence of Fan
-
In and Fan
-
Out on Delay


V

DD

A

B

A

B

C

D

C

D


Fan
-
out
: Number of Gates
connected to the output


in static CMOS, there are
two gate capacitances per
Fan
-
out


Fan
-
in
: Number of independent
variables for the logic function,
which has a
quadratic

effect on
t
p

due to:


resistance increasing


capacitance increasing

t
p

as a Function of Fan
-
In and Fan
-
Out


Fan
-
in:
quadratic

due to increasing resistance and
capacitance


Fan
-
out: each additional fan
-
out gate adds
two

gate
capacitances to C
L




t
p

= a
1
FI + a
2
FI
2

+ a
3
FO

Fast Complex Gates: Design Technique 1


Transistor sizing


as long as fan
-
out capacitance dominates



Progressive sizing

In
N

C
L

C
3

C
2

C
1

In
1

In
2

In
3

M1

M2

M3

MN

Distributed RC line


M1 > M2 > M3 > … > MN


(the MOSFET closest to the
output

should be the
smallest)

Can reduce delay by more
than 20%; decreasing gains
as technology shrinks

Resistance of M
1
(R
1
) N times in the delay

Equation. The resistance of M
2
(R
2
) appears N
-
1 times etc.

Fast Complex Gates: Design Technique 2


Input re
-
ordering


when not all inputs arrive at the same time

C
2

C
1

In
1

In
2

In
3

M1

M2

M3

C
L

C
2

C
1

In
3

In
2

In
1

M1

M2

M3

C
L

critical path

critical path

charged

1

0

1

charged

charged

1

delay determined by time to
discharge C
L
, C
1

and C
2

delay determined by time to
discharge C
L

1

1

0

1

charged

discharged

discharged

Sizing and Ordering Effects

D

C

B

A

D

C

B

A

C
L

C
3

C
2

C
1

Progressive sizing

in pull
-
down
chain gives up to a 23%
improvement.


Input ordering saves 5%


critical path A


23%



3

3

3

3

4

4

4

4

4

5

6

7


= 100 fF

Fast Complex
-
Gate Design Techniques: Stages and Fan
-
in
Considerations

Fast Complex Gates: Design Technique 3


Alternative logic structures

F = ABCDEFGH

Fast Complex Gates: Design Technique 4


Reducing the voltage swing







linear reduction in delay


also reduces power consumption

t
pHL

= 0.69 (
C
L
V
DD
)/ I
DSATn
)



= 0.69
(
C
L
V
swing
)/ I
DSATn
)

CMOS disadvantages


For N
-
input CMOS gate, 2N transistors required


Each input connects to an NMOS and PMOS transistor


Large input capacitance: limits fanout


Large fan
-
in gates: always have long transistor stack
in PUN or PDN


Limits pullup or pulldown delay


Requires very large transistors


Ratioed Logic

Ratioed logic is an attempt to reduce

The number of transistors required to
implant a given logic function, often at the
cost of reduced robustness and extra
power dissipation

Ratioed Logic

Ratioed Logic

Active Loads

Pseudo
-
NMOS logic


Pseudo
-
NMOS: replace PMOS PUN with single
“always
-
on” PMOS device


Some problems as pseudo
-
NMOS inverter:


V
OL

larger than 0


static power when PDN is on


Advantages


Replace large PMOS stacks with single device


Reduces overall gate size, input capacitance


Especially useful for wide
-
NOR structures

Pseudo
-
NMOS


0

Overall functionality of
the gates depend on the
NMOS and PMOS size

Pseudo
-
NMOS VTC

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

V

in


[V]

V

o

u

t



[V]

W/L

p

= 4

W/L

p

= 2

W/L

p

= 1

W/L

p

= 0.25

W/L

p

= 0.5

Load Lines of Ratioed Gates