Distributed Sleep Transistor Network for Power Reduction*

heartlustElectronics - Devices

Nov 2, 2013 (3 years and 9 months ago)

62 views

Changbo Long


ECE Department, UW
-
Madison

clong@cae.wisc.edu


Lei He

EDA Research Group

EE Department, UCLA

lhe@ee.ucla.edu

Distributed Sleep Transistor Network
for Power Reduction*

*Partially sponsored by NSF CAREER Award 0093273, SRC grant HJ
-
1008 and Intel Corporation

Outline


Motivation



Background



Distributed sleep transistor network (
DSTN
)


Structure, advantages, modeling and sizing algorithm



Experiment results



Conclusion and future work

Motivation


Leakage power will become the dominant power component


Reduced feature size


Increased system integration


more idle modules



Leakage reduction techniques


To reduce leakage for active modules


Dual threshold voltage assignment for sub
-
threshold leakage
[Mahesh et
-
al, ICCAD’02]


Pin reordering for gate leakage [Lee et
-
al, DAC’03]


To reduce leakage for idle modules


Input vector control [Johnson et
-
al, DAC’99]


Power gating

[Kao et
-
al, DAC’98][Anis
-
et al, DAC’02]

Motivation


System level: use power management processor (
PMP
) to
generate control signals [Mutoh et
-
al, JSSC’96]


PMP

can be distributed


Gate level: use sleep transistors to turns off power supply


Concerned with performance loss and area overhead

PMP

Sleep



g
1


g
n

Virtual GND

V
dd

Sleep tr.

Sleep

Sleep

tr.

Performance Loss


Performance loss


Increase in the propagation delay


Performance loss is proportional to
V
st


i
st


Maximum Simultaneous Switching Current (
MSSC
)


g
1


g
n

V
dd

i
st

i
st

MSSC


MSSC:
maximum current in the time domain and the input
vector domain

g
1

g
2

g
3

g
1

g
2

g
3

i
g1

i
g2

i
g3

Input vector

Time

MSSC

t

t

t

t

t

t

t

t

i
total

+

+

=

Area Overhead


Area overhead: the sleep transistor area and the routing
area of virtual ground wires



Design convention: given performance loss

, minimize area
overhead




g
1


g
n

V
dd

MSSC

Related Work


Module
-
based design methodology [Mutoh
-
et al, JSSC’95
’96] [Kao
-
et al, DAC’98]


A
single

and
large

sleep transistor accommodates entire
module [JSSC’96]


Manual sizing


automatic sizing considering discharge

patterns
[Kao
-
et al, DAC’98]


Voltage drop on
long
virtual ground wires is nontrivial, and
results in large area

Related Work


Module
-
based design methodology [Mutoh
-
et al, JSSC’95
’96] [Kao
-
et al, DAC’98]


A
single

and
large

sleep transistor accommodates entire
module [JSSC’96]


Manual sizing


automatic sizing considering discharge

patterns
[Kao
-
et al, DAC’98]


Voltage drop on
long
virtual ground wires is nontrivial, and
results in large area


Cluster
-
based design methodology [Anis
-
et al, DAC’02]


Group gates into clusters and
minimize peak current

in
clusters by clustering algorithms


Insert a sleep transistor for each cluster to
avoid

long virtual
ground wires


Clustering may
conflict

with time
-
driven placement

Sleep transistor area


Area*:
the sleep transistor area ignoring the resistance of
virtual ground wires





MSSC
module

<

i
MSSC
cluster_i


area*
module
<
area*
cluster


Sleep transistor area


Area*:
the sleep transistor area ignoring the resistance of
virtual ground wires





MSSC
module

<

i
MSSC
cluster_i


area*
module
<
area*
cluster




Considering the resistance of virtual ground wires,
Area
mod

>
Area
clu
[Anis
-
et al, DAC’02]



DSTN
has the smallest area


Area
DSTN



Area
*
mod

DSTN: Distributed Sleep Transistor Network


DSTN
enhances

cluster
-
based design by connecting
clusters with extra virtual ground wires

Cluster
-
based design

DSTN

Current Discharging Balance Reduces Size

Cluster
-
based design

DSTN


Cluster
-
based design


Current discharges by its
private

sleep transistor


large
transistor size



DSTN


Current discharges by
both

private

and
neighboring

sleep
transistors


small transistor size

Additional Advantages of DSTN

Cluster
-
based design

DSTN


DSTN

introduces
NO constraint

on placement


Wire overhead of
DSTN

is
small

Sleep

tr.

Sleep

tr.


Entire module


resistance network plus current source

Switching
current

R
i

R
st

Modeling of DSTN


DSTN Sizing Problem (
DSTN/SP
)


Given DSTN topology,
DSTN/SP

finds the size for every sleep
transistor such that the total transistor area of DSTN is
minimized

and the performance loss constraint is
satisfied

for
every cluster

DSTN Sizing Problem

R
st
=?

W=?

W=?

W=?

W=?

PL<


偌<


R
st
=?

V
st
<
ε

V
st
<
ε

R
st
=?

V
st
<
ε

R
st
=?

V
st
<
ε

Switching
current


Primary challenge: current source


Dependency between the current sources


Current varies w.r.t. time



Secondary challenge: resistance network


Given current source, size
R
st
to minimize transistor area while
satisfy performance loss constraints



Does any algorithms exist in the literature?


No exact solution


Close solution for Power/Ground network sizing [Boyd, et
-
al
ISPD’01]


We have developed an algorithm based on
special
properties
of
DSTN/SP

Difficulties of DSTN/SP

Properties of DSTN/SP Solutions


P1
: Assuming
R
i
=0
,








: Performance loss constraint,

MSSC
: Maximum current


P2
: given current source,
Area
DSTN

increases when
R
i

increases


The increase is limited because
R
i

<< R
st


R
i
=
∞,
Area
DSTN
=
Area
cluster






Properties of DSTN/SP Solutions


P3
: Assuming cluster current and
Area
DSTN

to be constant, to
achieve minimum performance loss,


Properties of DSTN/SP Solutions

Algorithm for DSTN/SP


P1
,
P2
: Total sleep transistor area of
DSTN

is determined by








[0.05, 0.5], empirical parameter increases when
R
i
increases




P3
: Size of each individual sleep transistor is





Key is to estimate
MSSC
module

and
MSSC
cluster


Estimate
MSSC
module


Circuit current strongly depends on input vector


The space of input vector increase exponentially with the
number of primary input


Genetic algorithm (GA) based algorithm is used [Jiang et
-
al,
TVLSI’00]



Efficient algorithm to estimate
MSSC
cluster
has been
proposed in the paper

Maximum Current Estimation


Cluster
-
based design without considering placement
constraint


Given a circuit and cluster size, partition gates into clusters such
that

i
MSSC
cluster_i

is minimized and
Area
cluster

is minimized in
turn



Clustering algorithm


Simulated Annealing (SA)



Sizing algorithm


Each individual sleep transistor



Total area


Base
-
line Case: Cluster
-
based Design

Experiment Setup


Gate level synthesis


Sizing


Estimate maximum current for clusters and the entire module


Apply the sizing algorithms


Verification


Simulate the circuit and obtain the current source by 10,000 random
input vectors


Obtain
performance loss
by solving the resistance network with
circuit
KCL

and
KVL

equations


Find the
maximum performance loss
among the performance loss
for each input vector



Custom layout


Implement a four
-
bit CLA using 0.35
μ
m technology


Determine size by
SPICE

simulation


Cluster
-
based design: each cluster satisfy the performance loss
constraint


DSTN
: the entire module satisfy the performance loss constraint


On average,

DSTN
reduces total W/L by
49.8%

with smaller
performance loss

Result of Gate Level Synthesis

Cluster
-
based


DSTN

W/L of Sleep Transistors

Maximum Performance Loss

Each cluster is
accommodated by a
sleep transistor

Sleep transistors

Sleep transistors are
connected by virtual
ground wires

Sleep transistors

Virtual ground wires


Cluster
-
based design


DSTN

Custom Layout in 0.35
μ
m


DSTN

reduces runtime leakage by
50x

and
5x



compared to no sleep transistor and cluster
-
based design,
respectively


DSTN

reduces sleep transistor area by
6.83x

with
6.6%

smaller performance degradation



compared to the cluster
-
based design

Custom Layout Comparison

Leakage
current

delay

Sleep tr.
Area

Total area

No sleep transistor

Cluster
-
based

DSTN

Conclusion and Future Work


We have proposed
DSTN
and the sizing algorithm


DSTN

has reduced area, less leakage current and supply
voltage drop



Future work


Ideal power/ground network is assumed in this paper


Investigate the co
-
design of
DSTN

and the
power/ground
network