Design and Implementation of VLSI Systems

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Nov 2, 2013 (3 years and 11 months ago)

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S. Reda EN160 SP’07

Design and Implementation of VLSI Systems

(EN0160)

Lecture 13: Power Dissipation

Prof. Sherief Reda

Division of Engineering, Brown University

Spring 2007

[sources: Weste/Addison Wesley


Rabaey/Pearson]

S. Reda EN160 SP’07

Power and Energy


Power is drawn from a voltage source
attached to the V
DD

pin(s) of a chip.



Instantaneous Power:



Energy:



Average Power:


S. Reda EN160 SP’07

Dynamic power


Dynamic power is required to charge and discharge
load capacitances when transistors switch.



One cycle involves a rising and falling output.


On rising output, charge Q = CV
DD

is required


On falling output, charge is dumped to GND


This repeats Tf
sw

times


over an interval of T

S. Reda EN160 SP’07

Dynamic power dissipation

Vin

Vout

C

L

Vdd

Energy delivered by
the supply

during input 1


0 transition:

Energy stored at
the capacitor

at the end of 1


0 transition:

dissipated in NMOS
during discharge

(input: 0


1)

load capacitance
(gate + diffusion +
interconnects)

S. Reda EN160 SP’07

Capacitive dynamic power



If the gate is switched on and off
f
0

1

(switching factor) times
per second, the power consumption is given by



For entire circuit

where
α
i

is activity factor [0..0.5] in comparison to the clock
frequency (which has switching factor of 1)

S. Reda EN160 SP’07

Short circuit current


When transistors switch, both nMOS and pMOS
networks may be momentarily ON at once


Leads to a blip of “short circuit” current.


< 10% of dynamic power if rise/fall times are
comparable for input and output

S. Reda EN160 SP’07

Dynamic power breakup

Total dynamic Power

[source: Intel’03]

S. Reda EN160 SP’07

Calculating dynamic power: An example


200 Mtransistor chip (1.2 V 100 nm process C
g

= 2 fF/mm)


20M logic transistors


Average width: 12
λ


180M memory transistors


Average width: 4
λ




Static CMOS logic gates: activity factor = 0.1



Memory arrays: activity factor = 0.05 (many banks!)




Estimate dynamic power consumption per MHz.

S. Reda EN160 SP’07

Static (leakage) power


Static power is consumed even when chip is
quiescent.


Leakage draws power from nominally OFF
devices

S. Reda EN160 SP’07

Leakage example


The process has two threshold voltages and two oxide
thicknesses.


Subthreshold leakage:


20 nA/

m for low V
t


0.02 nA/

m for high V
t


Gate leakage:


3 nA/

m for thin oxide


0.002 nA/

m for thick oxide


Memories use low
-
leakage transistors everywhere


Gates use low
-
leakage transistors on 80% of logic

S. Reda EN160 SP’07

Leakage power (continued)


Estimate static power:


High leakage:


Low leakage:









If no low leakage devices, Pstatic = 749 mW (!)

S. Reda EN160 SP’07

Techniques for low
-
power design


Reduce dynamic power




: clock gating, sleep mode


C: small transistors (esp. on clock), short wires


V
DD
: lowest suitable voltage


f: lowest suitable frequency


Enable

Clock

Clock Gating

only reduce supply voltage of
non critical gates

I
1

I
2

I
3

I
4

I
5

I
6

O
1

O
2

critical

path

S. Reda EN160 SP’07

Dynamic power reduction via dynamic V
DD

scaling


Scaling down supply voltage


reduces dynamic power


reduces saturation current




increases delay


reduce the frequency




Dynamic voltage scaling (DVS):

Supply and voltage of
the circuit should dynamic adjust according to the
workload of our circuits and criticality of the tasks

S. Reda EN160 SP’07

Reducing static power


Reduce static power


Selectively use low V
t

devices


Leakage reduction:


-

stacked devices, body bias, low temperature

S. Reda EN160 SP’07

Leakage reduction via adjusting of
V
th


Leakage depends exponentially on V
th
.


How to control V
th
?


Remember: V
th

also controls your saturation current


delay

2. Oxide thickness

1. Body Bias

I
1

I
2

I
3

I
4

I
5

I
6

O
1

O
2

critical

path

Sol1: statically

choose high
V
t

cells for non critical gates

Sol2: dynamically
adjust the bias of
the body



idle:

increase V
t

(e.g. by applying

ve body bias on NMOS)



Active:

reduce V
t

(e.g.: by
applying +ve body bias on NMOS)


S. Reda EN160 SP’07

Leakage reduction via Cooling



Impact of temperature on leakage current

S. Reda EN160 SP’07

Summary

We are still in chapter 4:



We covered delay and power estimation



Next time, we going to move into
integrating the impact of wires into
delay/power calculations