CMOS Transistor Theory

heartlustElectronics - Devices

Nov 2, 2013 (3 years and 5 months ago)

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Introduction to

CMOS VLSI

Design


Lecture 3:

CMOS Transistor Theory

David Harris




Harvey Mudd College

Spring 2004

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
2

Outline


Introduction


MOS Capacitor


nMOS I
-
V Characteristics


pMOS I
-
V Characteristics


Gate and Diffusion Capacitance


Pass Transistors


RC Delay Models

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
3

Introduction


So far, we have treated transistors as ideal switches


An ON transistor passes a finite amount of current


Depends on terminal voltages


Derive current
-
voltage (I
-
V) relationships


Transistor gate, source, drain all have capacitance


I = C (
D
V/
D
t)
-
>
D
t = (C/I)
D
V


Capacitance and current determine speed


Also explore what a “degraded level” really means

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
4

MOS Capacitor


Gate and body form MOS capacitor


Operating modes


Accumulation


Depletion


Inversion

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
5

Terminal Voltages


Mode of operation depends on V
g
, V
d
, V
s


V
gs

= V
g



V
s


V
gd

= V
g



V
d


V
ds

= V
d



V
s

= V
gs

-

V
gd


Source and drain are symmetric diffusion terminals


By convention, source is terminal at lower voltage


Hence V
ds



0


nMOS body is grounded. First assume source is 0 too.


Three regions of operation


Cutoff


Linear


Saturation

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
6

nMOS Cutoff


No channel


I
ds

= 0

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
7

nMOS Linear


Channel forms


Current flows from d to s


e
-

from s to d


I
ds

increases with V
ds


Similar to linear resistor

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
8

nMOS Saturation


Channel pinches off


I
ds

independent of V
ds


We say current saturates


Similar to current source

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
9

I
-
V Characteristics


In Linear region, I
ds

depends on


How much charge is in the channel?


How fast is the charge moving?

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
10

Channel Charge


MOS structure looks like parallel plate capacitor
while operating in inversion


Gate


oxide


channel


Q
channel

=

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
11

Channel Charge


MOS structure looks like parallel plate capacitor
while operating in inversion


Gate


oxide


channel


Q
channel

= CV


C =

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
12

Channel Charge


MOS structure looks like parallel plate capacitor
while operating in inversion


Gate


oxide


channel


Q
channel

= CV


C = C
g

=

ox
WL/t
ox

= C
ox
WL


V =

C
ox

=

ox

/ t
ox

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
13

Channel Charge


MOS structure looks like parallel plate capacitor
while operating in inversion


Gate


oxide


channel


Q
channel

= CV


C = C
g

=

ox
WL/t
ox

= C
ox
WL


V = V
gc



V
t

= (V
gs



V
ds
/2)


V
t

C
ox

=

ox

/ t
ox

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
14

Carrier velocity


Charge is carried by e
-


Carrier velocity
v

proportional to lateral E
-
field
between source and drain


v

=

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
15

Carrier velocity


Charge is carried by e
-


Carrier velocity
v

proportional to lateral E
-
field
between source and drain


v

=
m
E


m

called mobility


E =

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
16

Carrier velocity


Charge is carried by e
-


Carrier velocity
v

proportional to lateral E
-
field
between source and drain


v

=
m
E


m

called mobility


E = V
ds
/L


Time for carrier to cross channel:


t

=

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
17

Carrier velocity


Charge is carried by e
-


Carrier velocity
v

proportional to lateral E
-
field
between source and drain


v

=
m
E


m

called mobility


E = V
ds
/L


Time for carrier to cross channel:


t

= L /
v

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
18

nMOS Linear I
-
V


Now we know


How much charge Q
channel

is in the channel


How much time
t

each carrier takes to cross

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
19

nMOS Linear I
-
V


Now we know


How much charge Q
channel

is in the channel


How much time
t

each carrier takes to cross

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
20

nMOS Linear I
-
V


Now we know


How much charge Q
channel

is in the channel


How much time
t

each carrier takes to cross

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
21

nMOS Saturation I
-
V


If V
gd

< V
t
, channel pinches off near drain


When V
ds

> V
dsat

= V
gs



V
t


Now drain voltage no longer increases current

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
22

nMOS Saturation I
-
V


If V
gd

< V
t
, channel pinches off near drain


When V
ds

> V
dsat

= V
gs



V
t


Now drain voltage no longer increases current

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
23

nMOS Saturation I
-
V


If V
gd

< V
t
, channel pinches off near drain


When V
ds

> V
dsat

= V
gs



V
t


Now drain voltage no longer increases current

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
24

nMOS I
-
V Summary


Shockley

1
st

order transistor models

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
25

Example


We will be using a 0.6
m
m process for your project


From AMI Semiconductor


t
ox

= 100
Å



m

= 350 cm
2
/V*s


V
t

= 0.7 V


Plot I
ds

vs. V
ds


V
gs

= 0, 1, 2, 3, 4, 5


Use W/L = 4/2
l

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
26

pMOS I
-
V


All dopings and voltages are inverted for pMOS


Mobility
m
p

is determined by holes


Typically 2
-
3x lower than that of electrons
m
n


120 cm
2
/V*s in AMI 0.6
m
m process


Thus pMOS must be wider to provide same current


In this class, assume
m
n

/
m
p

= 2



*** plot I
-
V here

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
27

Capacitance


Any two conductors separated by an insulator have
capacitance


Gate to channel capacitor is very important


Creates channel charge necessary for operation


Source and drain have capacitance to body


Across reverse
-
biased diodes


Called diffusion capacitance because it is
associated with source/drain diffusion

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
28

Gate Capacitance


Approximate channel as connected to source


C
gs

=

ox
WL/t
ox

= C
ox
WL = C
permicron
W


C
permicron

is typically about 2 fF/
m
m

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
29

Diffusion Capacitance


C
sb
, C
db


Undesirable, called
parasitic

capacitance


Capacitance depends on area and perimeter


Use small diffusion nodes


Comparable to C
g



for contacted diff


½ C
g

for uncontacted


Varies with process

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
30

Pass Transistors


We have assumed source is grounded


What if source > 0?


e.g. pass transistor passing V
DD

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
31

Pass Transistors


We have assumed source is grounded


What if source > 0?


e.g. pass transistor passing V
DD


V
g

= V
DD


If V
s

> V
DD
-
V
t
, V
gs

< V
t


Hence transistor would turn itself off


nMOS pass transistors pull no higher than V
DD
-
V
tn


Called a degraded “1”


Approach degraded value slowly (low I
ds
)


pMOS pass transistors pull no lower than V
tp

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
32

Pass Transistor Ckts

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
33

Pass Transistor Ckts

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
34

Effective Resistance


Shockley models have limited value


Not accurate enough for modern transistors


Too complicated for much hand analysis


Simplification: treat transistor as resistor


Replace I
ds
(V
ds
, V
gs
) with effective resistance R


I
ds

= V
ds
/R


R averaged across switching of digital gate


Too inaccurate to predict current at any given time


But good enough to predict RC delay

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
35

RC Delay Model


Use equivalent circuits for MOS transistors


Ideal switch + capacitance and ON resistance


Unit nMOS has resistance R, capacitance C


Unit pMOS has resistance 2R, capacitance C


Capacitance proportional to width


Resistance inversely proportional to width

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
36

RC Values


Capacitance


C = C
g

= C
s

= C
d

= 2 fF/
m
m of gate width


Values similar across many processes


Resistance


R


6 K
W
*
m
m in 0.6um process


Improves with shorter channel lengths


Unit transistors


May refer to minimum contacted device (4/2
l
)


Or maybe 1
m
m wide device


Doesn’t matter as long as you are consistent

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
37

Inverter Delay Estimate


Estimate the delay of a fanout
-
of
-
1 inverter

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
38

Inverter Delay Estimate


Estimate the delay of a fanout
-
of
-
1 inverter

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
39

Inverter Delay Estimate


Estimate the delay of a fanout
-
of
-
1 inverter

CMOS VLSI Design

3: CMOS Transistor Theory

Slide
40

Inverter Delay Estimate


Estimate the delay of a fanout
-
of
-
1 inverter

d = 6RC