D
e
sign and Simulation of Discrete

Time Cellular Neural Network
by
N
egative
D
ifferential
R
esistance
Devices
Yaw

Hwang Chen,
Long

Xian Su
,
Kwang

Jow Gan,
Cher

Shiung Tsai, Dong

Shong Liang,
Chi

Pin
Chen
,
溫俊明
and
塗俊達
Department of Electronic Engineering, Kun
Shan University of Technology
(NSC93

2215

E

168

002)
Abstract
Resonant tunneling diodes(RTD
’
s) have found
various application in high

speed digital and
analog circuits due to their
specific
advantages
associated with the unique folded

back
negative diffe
rential resistance (NDR) I

V
characteristics.
In this paper we
realize
d negative differential
resistance (NDR) I

V curve of RTD by
n
egative
d
iff
e
rential
r
esistance
d
evices
.
The
NDR device is composed of
metal

oxide
semiconductor
field

effect
transistor (MO
S)
devices
.
The discrete

time cellular neural
network cell is composed of NDR devices.
Therefore, the DT

CNN can be fabricated by
standard CMOS process.
I.
Introduction
The
cellular
n
eural
n
e
t
work
s wer
e invented by
Chua and Yang in
1988. It is in order to sol
ve
real

world problems in image processing,
robotics, motion video and many other
complex computational problems.
Th
er
efore
evokes the widespread discussion
and there
have been
documented
in the first two
IEEE International Workshops on C
ell
ular
N
eural
N
etwork
s and their Application in
1992, while retained the two basic concepts of
local connectedness and analog circuit
dynamics.
Definition: The CNN is a
i)
2

, 3

, or n

dimensional array of
ii)
mainly identical dynamical systems,
called cells, which satisfies
two properties:
iii)
most interactions are local with a finite
radius
r
,and
iv)
all state variables are continuous valued
signals.
A typical example of a cell
of a
c
ellular
n
eural
n
etwork
s is shown in figure 1,
where the suffices
u, x
,
a
nd
y
denote the
input, state, and output respectively.
Therefore
node voltage
,
and
are defined input, state, and output voltage
respectively.
is a linear capacit
or;
and
are
linear resistors;
I
is an independent current
source;
and
are
linear voltage
controlled
current sources
with the characteristics
which
=
(1)
and
=
.
(2)
(3)
is a piecewise

linear voltage controlled
current source;
is
a time

invariant
independent voltage source.
The circuit equations of a cell which satisfy
KCL and KVL are easily derived as follow:
State equation
is
(4)
Where
and
are the
non
linear cloning templates.
Output equation is
(5)
Input equation is
(6)
Constraint conditions
are
. (7)
Parameter assumptions are
(8)
where
,
and
i
s the neighbor set of
.
Fig.1. It
is an example of a cell circuit.
II. The
Λ

type
NDR Device
A
Λ

type MOS

NDR device is composed of
t
hree NMOS
transistors.
This circuit is shown
in figure 2.
In the region 2, V
DS
exceeds the
threshold voltage of Q
3
and Q
3
changes from
cutoff state to saturation state. In the
meanwhile, V
GS
will g
o down and current
from
drain to source of Q
2
also goes down.
This is the
reas
on why there is a
negative
differential resistance
in the region 2.
Fig.
2.
A
Λ

type
NDR device circuit
is
composed of three NMOS
.
The
Λ

type I

V characteristics and the
operation point
are shown in figure
3 and
table1 of each transistor.
Fig.3.
It
is the
I

V curve of
Λ

type
.
Table 1. This table
shows the operating point
V
DS
Q
1
Q
2
Q
3
V
DS
< V
T
Saturation
Linear
Cut

off
V
DS
= V
GS
+V
T
Saturation
Linear→
Saturation
Saturation
V
GS
≤V
DS
+V
T
Saturation
Linear
Saturation
I
V
(1)
(2)
(3)
of each transistor for a
NDR device
.
III. The Inverter based on
Λ

type
NDR Device
T
he inverter
is constructed by
a N
MOS
device
and
a MOS

NDR device which are
connected parallel
. T
he total current I
total
is
the sum of the currents flowed through
the
MOS

NDR and NMOS devices
: I
total
=
I
NDR
+
I
MOS
.
Since I
MOS
can be
modulated by the gate
voltage
(V
G
),
so is
I
t
otal
, as show in figure
4.
Fig.4. The peak current of
Λ

type MOS

NDR
de
vice can be controlled by the V
G
voltage.
Our inverter circuit design is based on
two
series

connected MOS

NDR devices
as
shown in figure
5.
This circuit is so called the
monostable

bistable transition logic element
(MOBILE)
. The input node is located
at the
V
G
gate. The output node is located between
the two MOS

NDR devices. When
the bias
V
S
is bigger than
twice peak voltage (
2V
P
), but is
smaller than twice valley voltage (2V
V
), there
is two possible stable points (
bistable
) that
respect the low a
nd high states (corresponding
to
“
0
”
and
“
1
”
), respectively.
A small
difference between the peak currents of the
series

connected
NDR devices det
ermines the
state
which the circuit will stay stably
. By
suitably determining the parameters of
devices and
cir
cuits
, figure 6 shows the
simulated results for the inverter.
Fig. 5. I
nverter circuit design based on the
MOBILE.
Fig. 6. These are the simulated results for the
inverter.
IV. The MOBILE CNN
T
he cell circuit configuration of a DT

CNN
implemented
with MOBILE
’
s. Here, the cell
with positive feedback and an inverting
MOBILE at the output is show in Fig 7.The
state of MOBILE are clocked with the V
A
clock, the states of inverter are clocked with
the V
B
clock. V
A
and V
B
are
complementary
clocks. Hence,
the output A is
complementary
with output B. The cell outputs with clock are
on the control. Since output values can be
latched when clock is high and is changeable
when clock is low. The cell circuit is
con
trol
led and driven by input
, self

feedback
and c
lock. The cell can adjust branch in
parallel with the load
ing
MOS

NDR to
generate different outputs. The simulating
results of
the DT

CNN are shown in the
figure
8.
We can see the outputs of cells will
remain stably only within a few iterative
process. The
cell of DT

CNN based on
MOS

NDR device is as good as RTD

based cell. It
a
lso can be manufa
ctured by stand CMOS
process.
Fig.7 It
is the circuit
al
configuration of
DT

CNN implemented with MOBILE
’
s. A
cell
consist
s with positive feedback and
inverting MOBILE at the output.
Fig
. 8.
These are simulating results for the
DT

CNN. The traces show the time
evaluation of the output voltage
of the cells.
The evaluation of the cell
’
s states was
illustrated schematically in the upper inset.
Here, the black pixels indicate
d
cell state is 1
and white pixels indicate
d
cell state is 0.
V. Conclusions
We have designed a d
iscrete

t
ime
c
ellular
n
eural
n
et
work
(DT

CNN) based on the
Λ

type
NDR

based devices and circuits
according to the standard 0.35
μm
CMOS
process.
The I

V characteristics of the
NDR
device could be controlled by the V
g
voltage.
Hence, it is eas
ier to control than RTD
DT

CNN.
References
1. L.O.
Chua and L.
Yang
,
“
Cellular Neural
Networks
：
Theory
”
,
IEEE Transactions on
circuit
s and systems, vol.35, no.10, pp.1257

1272, October
1988.
2. L.
O. Chua and Patrick Thiran,
“
An Analytic
Method for Design Simple Cellular Neural
Networks
”
, IE
EE Transactions on circuits and
systems,
vol.38, no.11, pp. 1332

1341,
November
1991
3. L.O. Chua and T. Roska,
“
The CNN
Paradigm
“
, IEEE Transactions on circuits and
systems

I: Fundamental Theory
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,
vol.40, no.3, March 1993.
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Based Cellular
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“
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u
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Inputer
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“
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