VLSI DESIGN AND VHDL PROGRAMMING - St.Joseph's ...

greatgodlyElectronics - Devices

Nov 27, 2013 (3 years and 8 months ago)

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CLASS: M.Sc. ELECTRONICS








11A / 228

St. JOSEPH’S COLLEGE (AUTONOMOUS) TIRUCHIRAPPALLI


620 002

SEMESTER EXAMINATIONS


APRIL 2011

TIME: 3 Hrs.








MAXIMUM MARKS: 100

SEM

SET

PAPER CODE

TITLE OF THE PAPER

II

201
0

10PEL2107

VLSI DESIGN AND VHDL PROGRAMMING


SECTION


A

Answer all the questions:







20 x 1 = 20

Choose the correct answer:

1.

_________ is used to convey layer information through the use of a color code.


a)

Symbolic diagram

b)

Stick diagram



c)

Diffusion

d)

none

2.

CMOS fabrication includes _________ processes


a)

P
-
well

b)

n
-
well


c)

Twin
-
tub

d)

all the above

3.

The sheet resistance Rs of metal for MOS layers of 5

m is ________


a)

0.04

b)

2

4


c)

0.03

d)

10

4.

Switch logic is al
so called as _________


a)

restoring logic

b)

gate logic


c)

pass transistor

d)

none

5.

_________ describes the behaviour of the entity


a)

configuration

b)

package


c)

entity

d)

architecture

6.

________ statement contains only sequential st
atement


a)

Process statement

b)

Sequential statement


c)

Block statement

d)

Concurrent statement

7.

________ are used to specify the design environment


a)

Constraints

b)

attributes


c)

load

d)

Drive

8.

________ is an estimated delay used t
o model the delay through typical wire used to connect
cells together


a)

intrinsic delay

b)

wire delay


c)

slope delay

d)

loading delay

9.

The Quarters II development software provides complete design environment for ________
design


a)

SOC

b)

SOPC


c)

ICSOC

d)

none

10.

_________ is used to convert design files in a project into output files


a)

simulator

b)

compiler


c)

synthesizes

d)

debugger


Fill in the blanks:

11.

The color coding of metal in stick diagram is _________.

12.

Gate logic
can be called as _________.

13.

_________ and _________ are the two types of delay used for modeling behaviors.

14.

_________ objects are used for connecting entities together to form models.

15.

Functional simulation is used to test _________ operatio
n of the design.


State True or False:

16.

MOS circuits are formed on four layers which are isolated one another by thick or thin SiO
2

layer.

17.

Switches and switch logic can not be formed from transmission gates.

18.

The process statement has a decla
ration section and a statement part.

19.

Integer types are different from mathematical integers.

20.

The quarters II software support EDIF input files.



SECTION


B

Answer all the questions:








3 x 4 = 12

21.

a.

Write short notes on BIC
MOS inverters.


OR


b.

List out the advantage of E
-
beam masks.

22.

a.

Describe about switch logic.


OR


b.

Write short notes on two phase clocking.

23.

a.

Write short notes on quarters II IDE


OR


b.

Define the following (i) Compiling

(ii) Simu
lating


Problem type questions:










1 x 8 = 8


24.

a.

Write a VHDL program to perform ALU operation using behavioral modeling.


OR


b.

Write a VHDL program to perform Encode operation using behavioral and data flow
modeling.


SECTIO
N


C

Answer any FOUR questions:






4 x 15 = 60

25.

Explain the fabrication process of nMOS transistor with neat sketch.

26.

Elaborately explain the scaling factors for device parameters.

27.

What are the basic VHDL building blocks and explain e
ach in detail.

28.

Explain VHDL data types in detail with neat sketch.

29.

Write a program for interfacing seven segment with DEI using Quarters II IDE.



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