VLSI
PROJECTS
Project Infosys Solutios
Designing, Development, Innovations and More…..
IEEE VLSI PROJECTS
SI.No
Project Title
Year
1.
Automated Placement for Parallelized FPGA FFTs
IEEE 2011
2.
High
-
Throughput, Lossless Data Compression on FPGAs
IEEE
2011
3.
Automatic HDL
-
based generation of homogeneous hard macros for FPGAs
IEEE 2011
4.
Implementation and Performance Analysis of SEAL Encryption
on FPGA, GPU and Multi
-
Core Processors
IEEE 2011
5.
Design of a FPGA
-
Based Parallel Architecture for BLA
ST Algorithm with
Multi
-
hits Detection
IEEE 2011
6.
FPGA Based High Performance and Scalable Block LU Decomposition Architecture
IEEE 2011
7.
A novel design methodology for implementing reliability
-
aware systems on SRAM
-
based FPGAs
IEEE 2011
8.
A High P
erformance and Memory Efficient LU Decomposer on FPGAs
IEEE 2011
9.
FPGA Implementation of Adjustable Wideband Fractional Delay FIR Filters
IEEE 2011
10.
Parallel FPGA
-
based Implementation of Recursive Sorting Algorithms
IEEE 2011
11.
Skein Tree Hashing
on FPGA
IEEE 2011
12.
Reconfigurable Cache implemented on an FPGA
IEEE 2011
13.
Evaluation of white
-
box and grey
-
box Noekeon implementations in FPGA
IEEE 2011
14.
Evaluation of white
-
box and grey
-
box Noekeon implementations in FPGA
IEEE 2011
15.
VLSI
Implementation of Balanced Binary Tree Decomposition based 2048
-
point FFT/IFFT Processor for
Mobile WI
-
Max
IEEE 2011
16.
Hierarchical Design of an Application
-
Specific Instruction Set Processor for High
-
Throughput and
Scalable FFT Processing
IEEE 2011
17
.
Construction of Optimum Composite Field Architecture for Compact High
-
Throughput AES S
-
Boxes
IEEE 2011
18.
VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm
IEEE 2011
19.
VLSI Architecture of Arithmetic Coder Used in SPIH
T K
IEEE 2011
20.
Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA
IEEE 2011
21.
Energy
-
Efficient Low
-
Latency 600 MHz FIR With High
-
Overdrive Charge
-
Recovery Logic
IEEE 2011
22.
Pipelined Parallel FFT Architectures via Foldin
g Transformation
IEEE 2011
23.
Loop Acceleration Exploration for ASIP Architecture
IEEE 2011
24.
A Low
-
Power Low
-
Cost Design of Primary Synchronization Signal Detection
IEEE 2011
25.
Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrin
omials
IEEE 2011
26.
Memory Efficient Modular VLSI Architecture for Highthroughput and Low
-
Latency Implementation of
Multilevel Lifting 2
-
D DWT
IEEE 2011
27.
High
-
Throughput Soft
-
Output MIMO Detector Based on Path
-
Preserving Trellis
-
Search Algorithm
IEEE
2011
28.
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell
-
Based Data Caches
IEEE 2011
29.
Robust Secure Scan Design Against Scan
-
Based Differential Cryptanalysis
IEEE 2011
30.
Efficient Pattern Matching Alg
orithm for Memory Architecture
IEEE 2011
31.
Multiple curve presentation and zooming processor using Field Programmable Gate Arrays
IEEE 2011
32.
Design and Implementation of Area
-
optimized AES Based on FPGA
IEEE 2011
33.
Multiple curve presentation and
zooming processor using Field Programmable Gate Arrays
IEEE 2011
34.
Joint Optimization of Run
-
Length Coding, Huffman Coding, and Quantization Table With Complete
Baseline JPEG Decoder Compatibility_sim
IEEE 2009
35.
A Fully Pipelined Architecture for t
he LOCO
-
I Compression Algorithm for images_Sim
IEEE 2009
36.
A Low
-
Complexity Hybrid LDPC Code Encoder for IEEE 802.3an (10GBase
-
T) Ethernet
IEEE 2009
37.
A Low
-
Cost VLSI Implementation for Efficient Removal of Impulse Noise in images_Sim
IEEE 2009
39.
A Low
-
Jitter Open
-
Loop All
-
Digital Clock Generator With Two
-
Cycle Lock
-
Time
IEEE 2009
40.
A Multibank Memory
-
Based VLSI Architecture of DVB
IEEE 2009
41.
A Parallel Pruned Bit
-
Reversal Interleaver
IEEE 2009
42.
Adaptive Frequency
-
Domain Channel Estimato
r in 4X4 MIMO
-
OFDM Modems
IEEE 2009
43.
Adaptive IIR Filtering of Noncircular Complex Signals
IEEE 2009
44.
An Efficient 4
-
D 8PSK TCM Decoder Architecture
IEEE 2009
45.
Asynchronous Current Mode Serial Communication
IEEE 2009
46.
Asynchronous Protocol
Converters for Two
-
Phase Delay
-
Insensitive Global Communication
IEEE 2009
47.
CMOS Driver
-
Receiver Pair for Low
-
Swing Signaling for Low Energy On
-
Chip Interconnects
IEEE 2009
48.
Design and Implementation of a Field Programmable CRC Circuit Architecture
IEEE 2009
49.
Design of Network
-
on
-
Chip Architectures With a Genetic Algorithm
-
Based Technique
IEEE 2009
50.
Design of Voltage Over scaled Low
-
Power Trellis Decoders in Presence of Process Variations
IEEE 2009
51.
Design Space Exploration of Hard
-
Decisi
on Viterbi Decoding: Algorithm and VLSI Implementation
IEEE 2009
52.
Energy
-
Efficient Sub threshold Processor Design
IEEE 2009
53.
Fast Scaling in the Residue Number System
IEEE 2009
54.
Integrated Solar Energy Harvesting and Storage
IEEE 2009
55.
Mult
i
-
Gbps LDPC Code Design and Implementation
IEEE 2009
56.
Noisy FIR identification as a quadratic eigenvalue problem
IEEE 2009
57.
Novel Area
-
Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension
IEEE 2009
58.
On the Relay Channe
l With Receiver
–
Transmitter Feedback
IEEE 2009
59.
Optimized Analog flat filter design
IEEE 2009
60.
Scalable Multi
-
Input
–
Multi
-
Output Queues With Application to Variation
-
Tolerant Architectures
IEEE 2009
61.
Variation
-
Aware Low
-
Power Synthesis Methodol
ogy for Fixed
-
Point FIR Filters
IEEE 2009
62.
Spectrally Shaped Generalized MC
-
DS
-
CDMA with Dual Band Combining for Increased Diversity
IEEE 2008
63.
Single Chip Encryptor Decryptor Core Implementation of AES Algorithm
IEEE 2008
64.
Serial Search Code A
cquisition Using Smart Antennas with Single Correlator or Matched Filter
IEEE 2008
65.
Practical Asynchronous Interconnect Network Design
IEEE 2008
65.
Fast Elliptic Curve Cryptography on FPGA
IEEE 2008
67.
A Novel Approach to Design BCD Adder and Carry
Skip BCD Adder
IEEE 2008
68.
A Novel Carry
-
look ahead approach to an Unified BCD and Binary Adder_Subtractor
IEEE 2008
69.
Injecting Intermittent Faults for the Dependability Validation of Commercial Microcontrollers
IEEE 2008
70.
Unspecified Transiti
on Faults: A Transition Fault Model for At
-
Speed Fault Simulation and Test
Generation
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