Introduction to L
This computer assignment will familiarize you with L
EDIT, which is an integrated circuit
(IC) layout editor developed for the desktop personal computer. Since this course deals
ith introductory very
scale integration (VLSI) design techniques, we will be using
this program throughout the semester to design elementary digital circuitry.
You will investigate the parasitic elements of some simple design layers. In addition, y
will use L
EDIT's special feature for viewing a cross
section of your design layout. This
"cross sections view" will help you understand the 3
dimensional form of your design,
which will be especially useful later this semester when we discuss fabricat
ion techniques of
CMOS and BiCMOS ICs.
Before getting started, you should read
Sections 1.2.4, 1.3
6, 1.8, 3.3.1, and 3.7.1
with any new program, reading the manual before actually working with the program will
cut save time.
you need to find access to a PC or UNIX workstation which has L
UNIX version is already available in sun workstation: tesla.ceatlabs.okstate.edu. For PC
version, you need the student version disk that comes with your L
EDIT book). If you h
bought the student version, you should follow the installation procedures in Sections 1.1,
1.2 of the L
Part 1: Exploring L
EDIT from the L
EDIT directory in DOS by typing
at the prompt, or from
the Windows File Man
ager program by double clicking on
. You should see an
Click once on the mouse to get to the screen shown in Figure 1.1 on page 1
6 of the manual.
box in the upper left
hand corner. This inf
will be useful later when we design complicated circuit layouts. The
the current layer name for each icon in the
gives all the
various layers you may use in your layout. If you want to use a
different layer, simply click
on the appropriate layer icon in the palette. The
Drawing Tool Palette
defines the various
tools used during layout design. Finally, the
box describes the particular
use of each mouse button for a variety of
operations. Note that if only two buttons are
shown, then the program assumes you are using a two
In this case, you must
hold down the Alt
key while pressing the Left mouse button
to access the center button
. An example is when
you want to reposition a pattern on the screen, you must
use the center button.
Try drawing the shapes in Figure 1.5 on page 1
13 of the manual, using the POLY layer
(which is polysilicon) from the Layer Palette.
After drawing these shapes, select these
shapes using the 'arrow' tool from the Tool Palette,
and delete them by using the Delete
Part 2: Parasitics
Parasitic resistances and capacitances are inherent to VLSI circuits due to electromagnetic
effects between layers. At the micrometer sca
le considered in VLSI design, the parasitic
elements limit the switching performance of a digital logic circuit.
To investigate parasitics, do the following and answer the corresponding questions:
Draw a POLY line, a METAL 1 line, an n
diff line, an
d a p
diff line each being
m wide and 41
m long. The n
diff line is produced by drawing a line of layer N
SELECT and then drawing another line of layer ACTIVE on top of it. The p
line is produced by drawing a line of layer P
SELECT and then drawing another line
of layer ACTI
VE on top of it.
Using Table 1. below, calculate the interconnects' R
for each of the
If we want to create a minimum area 1000 k
resistor (not necessarily a line), which
of the above layers would be best, and what woul
d be that layer's dimensions.
Discuss the reasoning behind your choice.
How many ways can the resistor from question (3) be laid out?
Table 1: Sheet Resistances and Interconnect Capacitance
Part 3: Cross
Lastly, we will look at L
sectional view option.
In addition to looking at a "side
view" of a particular
element in a layout, this option can let you
watch each layer
being "grown" and layered. This option will be discussed in
further detail in later assignments.
Draw a layout as in Figure 1 below.
Fig. 1. “Top
View” of layout for pwrt(3)
Note that for cross
' the METAL 2 line lies on top of a METAL 1 rectangle.
Also, to create the N
Ts, you must first draw a rectangle with the N
layer, then draw over it with a rectangle of ACTIVE layer. This tells the program that
diffusion lies around the poly line, but not directly under it. Part 3. will allow you
to understand this b
etter when looking at various cross
sections of Fig.1
In order to view the cross
sections shown in Fig. 1., do the following:
Section...' from the 'Special' pull
Enter the definition file (Xsect.xst or Morbn20.xst) nam
e in the top box and Click
'OK' for the cross
sectional viewer dialog box.
Position the cursor at the A
section as in Figure 1, and click on the left
mouse button. In the lower half of the screen, you should see the "side view" of the
Edit does not have the capability to print this picture, you will have to 'print
dump' the screen to a printer.
After printing, click on the mouse button to return to the work area.
Repeat steps (1) through (5) for cross
B' and C
Label the layers for each
plot to be turned in and identify any sources of parasitic capacitance.
Upon reviewing your printouts, answer the following questions:
What is the effect of the POLY CONTACT in cross
Does the order in which you draw the layers for cross
B' in L
matter? Why or why not? Is there any additional layers between POLY and MET1
or between MET1 and MET2? If YES, what is that?
With respect to the cross
A' through C
C', can you identify the layer
hierarchy (or ordering) from bottom to top? What layer is exactly below the PLOY
layer in A
A’ ? How many parasitic capacitors can you find? Turn in the labeled
section in MS word.
What is the difference be
sections between pFET and nFET?