Introduction to L-EDIT

greatgodlyElectronics - Devices

Nov 27, 2013 (3 years and 6 months ago)

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1


DIGITAL ELECTRONICS

ECEN 4303


LAB 1

Introduction to L
-
EDIT



Objective :


This computer assignment will familiarize you with L
-
EDIT, which is an integrated circuit
(IC) layout editor developed for the desktop personal computer. Since this course deals
w
ith introductory very
-
large
-
scale integration (VLSI) design techniques, we will be using
this program throughout the semester to design elementary digital circuitry.


You will investigate the parasitic elements of some simple design layers. In addition, y
ou
will use L
-
EDIT's special feature for viewing a cross
-
section of your design layout. This
"cross sections view" will help you understand the 3
-
dimensional form of your design,
which will be especially useful later this semester when we discuss fabricat
ion techniques of

CMOS and BiCMOS ICs.



Preparation:


Before getting started, you should read
Sections 1.2.4, 1.3
-
6, 1.8, 3.3.1, and 3.7.1
-
4
. As
with any new program, reading the manual before actually working with the program will
cut save time.


Also,
you need to find access to a PC or UNIX workstation which has L
-
EDIT installed(
UNIX version is already available in sun workstation: tesla.ceatlabs.okstate.edu. For PC
version, you need the student version disk that comes with your L
-
EDIT book). If you h
ave
bought the student version, you should follow the installation procedures in Sections 1.1,
1.2 of the L
-
EDIT manual.



Part 1: Exploring L
-
EDIT


Launch L
-
EDIT from the L
-
EDIT directory in DOS by typing
ledit

at the prompt, or from
the Windows File Man
ager program by double clicking on
ledit.exe
. You should see an
introduction screen.


Click once on the mouse to get to the screen shown in Figure 1.1 on page 1
-
6 of the manual.

Note the
File Name

and
Cell Name

box in the upper left
-
hand corner. This inf
ormation

2


will be useful later when we design complicated circuit layouts. The
Layer Name

box gives
the current layer name for each icon in the
Layer Palette
. The
Layer Palette

gives all the
various layers you may use in your layout. If you want to use a

different layer, simply click
on the appropriate layer icon in the palette. The
Drawing Tool Palette

defines the various
tools used during layout design. Finally, the
Mouse Functions

box describes the particular
use of each mouse button for a variety of
operations. Note that if only two buttons are
shown, then the program assumes you are using a two
-
button mouse.
In this case, you must
hold down the Alt
-

key while pressing the Left mouse button

to access the center button
operations
. An example is when
you want to reposition a pattern on the screen, you must
use the center button.


Try drawing the shapes in Figure 1.5 on page 1
-
13 of the manual, using the POLY layer
(which is polysilicon) from the Layer Palette.


After drawing these shapes, select these
shapes using the 'arrow' tool from the Tool Palette,
and delete them by using the Delete
-

key.



Part 2: Parasitics


Parasitic resistances and capacitances are inherent to VLSI circuits due to electromagnetic
effects between layers. At the micrometer sca
le considered in VLSI design, the parasitic
elements limit the switching performance of a digital logic circuit.


To investigate parasitics, do the following and answer the corresponding questions:


(1)

Draw a POLY line, a METAL 1 line, an n
-
diff line, an
d a p
-
diff line each being
2

m wide and 41

m long. The n
-
diff line is produced by drawing a line of layer N
-
SELECT and then drawing another line of layer ACTIVE on top of it. The p
-
diff
line is produced by drawing a line of layer P
-
SELECT and then drawing another line
of layer ACTI
VE on top of it.


(2)

Using Table 1. below, calculate the interconnects' R
line

and C
line

for each of the
above lines.


(3)

If we want to create a minimum area 1000 k


resistor (not necessarily a line), which
of the above layers would be best, and what woul
d be that layer's dimensions.
Discuss the reasoning behind your choice.


(4)

How many ways can the resistor from question (3) be laid out?






3


Table 1: Sheet Resistances and Interconnect Capacitance
Values



Layer

Sheet
Resistance

[


/ square]

Area
Capacitance

to Substrate

[fF /

m
2
]

Sidewall
Capacitances

[fF /

m]

POLY

22

0.058


METAL 1

0.
05

0.026


n
-
diff

35

0.122

0.451

p
-
diff

75

0.347

0.210




Part 3: Cross
-
Sectional Views


Lastly, we will look at L
-
EDIT's cross
-
sectional view option.

In addition to looking at a "side
-
view" of a particular
element in a layout, this option can let you
watch each layer
being "grown" and layered. This option will be discussed in
further detail in later assignments.


Draw a layout as in Figure 1 below.


Fig. 1. “Top
-
View” of layout for pwrt(3)




4





Note that for cross
-
section B
-
B
' the METAL 2 line lies on top of a METAL 1 rectangle.


Also, to create the N
-
MOSFE
Ts, you must first draw a rectangle with the N
-
SELECT
layer, then draw over it with a rectangle of ACTIVE layer. This tells the program that
the n
-
diffusion lies around the poly line, but not directly under it. Part 3. will allow you
to understand this b
etter when looking at various cross
-
sections of Fig.1




In order to view the cross
-
sections shown in Fig. 1., do the following:


(1)

Choose 'Cross
-
Section...' from the 'Special' pull
-
down menu.


(2)

Enter the definition file (Xsect.xst or Morbn20.xst) nam
e in the top box and Click
'OK' for the cross
-
sectional viewer dialog box.


(3)

Position the cursor at the A
-
A' cross
-
section as in Figure 1, and click on the left
mouse button. In the lower half of the screen, you should see the "side view" of the
A
-
A' c
ross
-
section.


(4)

Since L
-
Edit does not have the capability to print this picture, you will have to 'print
dump' the screen to a printer.


(5)

After printing, click on the mouse button to return to the work area.


Repeat steps (1) through (5) for cross
-
s
ections B
-
B' and C
-
C'.
Label the layers for each
plot to be turned in and identify any sources of parasitic capacitance.


Upon reviewing your printouts, answer the following questions:


(1)

What is the effect of the POLY CONTACT in cross
-
section B
-
B'?


(2
)

Does the order in which you draw the layers for cross
-
section B
-
B' in L
-
EDIT
matter? Why or why not? Is there any additional layers between POLY and MET1
or between MET1 and MET2? If YES, what is that?


(3)

With respect to the cross
-
sections A
-
A' through C
-
C', can you identify the layer
hierarchy (or ordering) from bottom to top? What layer is exactly below the PLOY
layer in A
-
A’ ? How many parasitic capacitors can you find? Turn in the labeled
cross
-
section in MS word.



5


(4)

What is the difference be
t
ween the

cross
-
sections between pFET and nFET?