Final Project Proposal
“
ALU and Register File
”
Name: Vincent Lixiang Bu
Zhoug Jian Zou
Date: 09/11/2006
2
The Objective for the P
roject
Beside the material from the lecture, we hope this Final Project can help us reach
all of
goals as follows:
Firstly, t
o
develop and fu
rther
our
understanding of how rudimentary logic functions are
designed and implemented at the transistor
-
level in complementary metal
-
oxide
semiconductor (CMOS) technology.
Secondly, t
o d
evelop
our
understanding of fabrication processes for very large sc
ale
integrated (VLSI) circuits, and ability to design the physical layout of VLSI circuits.
Thirdly, t
o develop
our
understanding of delay characterization, capacitance
characterization, and transient analysis used to optimize the performance of VLSI circ
uits,
and the concept of standard cell design methodology used to implement VLSI systems.
Fourthly, t
o further
our
understanding of VLSI design through laborator
y experiments
upon
modern
-
day Cadence
system performance
.
Last but not the least; we hope thi
s Final Project can develop our teamwork abilities,
independent research abilities, learning skills and problem solving skills.
The M
otivation
for the P
roject
The aim of this
final
project is to design the schematic and layout for a 32
-
bit
ALU
, and
if po
ssible manufacture our design.
We are particularly focusing on developing more
functions performed in one ALU, which include Addition, Subtraction, Multiplica
tion,
Logic Complement, Shift
,
Less Than,
AND/NAND, NOT, OR/NOR, XOR/N
X
OR etc.
Beside the functio
n development, w
e are interested in optimizing the speed of our ALU
,
and
try to minimize the overall delay.
If we accomplish
those
initial goals, we hope to
analyze some power, area, and scaling trade
-
offs.
3
Block Diagram
Figure 1. ALU Block Diagram
Block description
The
control logic block
uses the ALU opcode and the status flags to generate individual
control/select signals for the different modules.
In the current implementation,
we use the Carry Look Ahead adder with
4 bit group for
Adder.
The carry select algorithm is also combined with CLA adder to reduce
calculation time.
In the
output multiplier and status flag generation
block the operation result and status
flags are selected according to the ALU opcode. The B
YPASS signal can be used to
disable changes in the status flags. If BYPASS is high, STATUS is always the same as
STATUS_IN.
TEMP_
OUT
Selection
A
STATUS
BYPASS
STATUS_IN
OPCODE
STATUS_IN
OPCODE
C Status
C Status
A B
A B
A B
A B
A B
A B
A B
A B
TEMP_IN
Logic Con
trol
AND
/
NAND
NOT
OR /
N
OR
XOR /
NXOR
Comp
Adder
Less
than
Subtr
act
or
Shift
Output Multiplier and Status Flag Generation
A
B
R
4
Floor Plan
with I/O pins
Figure 2. ALU Floor Plan
gnd
NC
Testmux
gnd
S3
S2
S1
S0
testreset
testqbar
Vdd
B0
B1
B2
B3
A0
A1
A2
A3
TEMP_IN
Adder
NOT
AND / NAND
OR / NOR
XOR / NXOR
Complementary
Subtract
Logic Control
Less Than
Test Logic
Output
M
ultiplier
Shifter
ROUTE
NC
NC
vdd
R0
R1
R2
R3
R4
R5
R6
R7
NC
vdd
C0
C1
C2
C3
gnd
testq
testclk
5
Floorplan description
A3
–
A0
Input A
B3
–
B0
Input B
TEMP_IN
Temporary Input, like Carry Input for Addition
R7
–
R0
Output / Result
S3
–
S0 Shift Select
vdd
Supply Voltage
gnd
Circuit Ground
tst
Test Logic
muxtst
Test the working of the Multiplexer
NC
No Connection
Team Management Plan
For our final project, there is a two member group. We split the tasks into individual part
and cooperated part. For individual part, each member trys to finish his task
independently and flexibly according to perso
nal schedule. For cooperated ones, we will
meet and work all together on some available spot.
For th
e project, the detail works
consist of Schematic, Layout and Simulation and Test.
Here we try to do the Schematic and schematic simulation together, and t
hen do the
layout part. Beside above, there are still some paper works and webpage building up.
Below is our detailed team management:
1. Schematic and Simulation
1.1.
Basic Building Blocks of the ALU
(done already by Vincent)
1.2
.
Intermediate Building Blocks of the ALU
1.2.1
.
1
-
Bit Blocks
(done already by
Z
ou)
1.2.2
.
4
-
Bit Blocks
Zou has already finished :
2
-
1 Mux
,
4
-
1 Mux
and
8
-
1 Mux
;
Vincent has already finished:
Inverter Units
,
OR Units
,
AND Units
,
XOR
,
Units
,
ALU
and
B
-
Select
;
Will do
: ALU
(
Zou
)
1.3
.
Large
Circuit
Blocks
Zou has already finished:
Carry Look Ahead (CLA)
Vincent wi
ll do: Shifter
6
Zou will do: Subtract
We will do corporately:
32
-
Bit ALU
,
Look Ahead Unit
2. Layout
2.1
.
Basic Building Blocks of the ALU
(will do by Vincent)
2.2
.
Intermediate Building Blocks of the ALU
2
.2.1
.
1
-
Bit Blocks
(will do by
Z
ou)
2.2.2
.
4
-
Bit Blocks
Zou will do :
2
-
1 Mux
,
4
-
1 Mux
and
8
-
1 Mux
and
ALU
Vincent will do:
Inverter Units
,
OR Units,
AND Units,
XOR Units
,
ALU
and
B
-
Select
;
2.3
.
Large Circuit Blocks
(We will do corporately)
3. Paper work and We
bpage Building up
3.1
.
Project Proposal (done by Vincent)
3.2
.
Other paper works (will do by Zou)
3.
3
.
Webpage Building up (We will do corporately)
4. Verilog Functional Simulations
Zou is doing this part of
work
right now
;
if possibl
e we will turn in the Verilog code
and simulation result attached in this proposal. Otherwise we will post in our future
Project Webpage.
Appendix: Verilog Functional Simulations
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