Advanced VLSI Design Course Project

greatgodlyElectronics - Devices

Nov 27, 2013 (3 years and 11 months ago)

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1



Advanced VLSI Design


Course Project


http://6371.lcs.mit.edu/

1.
Project Guidelines

Projects may be done by one, two or three people working together with each person's
responsibil
ities clearly defined. The goal of the project
is to design a custom CMOS chip,

using the
0.35
μm
CMOS n
-
well process.

Each team is expected to do the following:

1.

prepare a
project proposal

in the form a
web page.

2.

schedule a
project review


3.

give a 10 minute
project presentation


4.

prepare a
final project report

in the form a web page




it must conform the standard "tiny chip" form factor: 40
-
pin package (34 signal
pins) with a 1830
μ

x 1800
μ

core area (see below).



it must pass the design rule checker



it must pass a logic simulati
on test you construct and the output of the design
must match the intended results


1.1.
The Project Proposal (due 18/10/2005
)

The project proposal is a web page page that summarizes
what

you intend to do for your
project and
how

you intend to get it all
done. The proposal should have the following
sections:

Overview.

Just a
few

sentences explaining what the project is about. What does it do?
Does it fit into a larger system and if so, how?

Team members and Responsibilities.

Lay out the responsibilities
of each team member.
Everyone should be responsible for some circuit design and layout (3 to 6 cells would be
an average workload
--

more if it's just logic gates, fewer for complex cells such as static
rams); architecture, simulation and documentation can

be shared by all. Team members
will be graded individually so each must have a legitimate role in the project's creation.
This is a good point to reach an agreement between the team members about who's going
to do what. You'll be expected to hold up your
end of the bargain.

Schedule.

Try to make a schedule you can stick to
.
;


2

Theory of Operation.

Briefly explain how the project works at a low enough level of
detail so that an interested reader can figure out how it all fits together. What major
components

can you partition your design into? What are the component interfaces like?
A block diagram (either in words or graphics) is a good idea perhaps augmented by a
simple datapath or pipeline diagram along with some information about how the timing
will work
in your circuit.
Present a Verilog project description.
Don't explain how blocks
work at the transistor level, but you should point out any non
-
obvious implementation
strategies you intend to employ.

Pinout.

A "tiny chip" has 40 pins: you can have up to 3
4 signal pins; there six dedicated
power pins (4 for the pad ring, 2 for the core logic). A simple listing of the pins and a
sentence describing what each does is all that's needed
--

the goal is to make sure that you
have thought about how to interface yo
ur design to the outside world. The pin limitation
might force you into implementing an n
-
bit slice of some larger design. Make some
provision for observing interesting data and control signal values so that there's a hope of
debugging the chip when it com
es back. If your project is a module of a larger system,
think about how you expect to test the module without the rest of the system.

Floorplan.

This is a diagram showing how your logic fits inside of the ring of i/o cells
(called the pad frame). The ide
a is to arrange things so that you don't have a lot of
unnecessary routing of signals back and forth across the chip. This is a good point to
make some preliminary size estimates. The area inside the tiny chip pad frame is
1830μ x
1800μ
, but you'll need to

leave some room for routing to and from the pads, so a practical
upper bound on the size of your logic is
1600μ x 1600μ
. The floorplan should help you
visualize how the clock and power routing will work. Here's a picture of a blank pad
frame:

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3

Cells.

Each team member is expected to lay out between
3 and 6 cells. More than 10 cells
per person is getting to be a lot; remember that cell layout and interconnect will take a lot
of time.

References.

Since this is a course about VLSI technology rather than architecture, you
are encouraged to borrow good p
roject ideas from other places: your friends, your
research group, journals, conferences, etc. Please reference any material that you use
--

it's the right thing to do and it will help other people find related material when they read
about your project.

1.2.
The P
roject Review (completed by 20/1
2/
2005
)

This is a short (10
-
15 min) meeting scheduled between the team and one or more of the
staff during lab hours the week of 11/18/96. We want to hear how you are doing, i.e.,
what progress has been made and w
hat problems you are having. The goal of this
meeting is to make sure things are on track to complete the project by the deadline and to
brainstorm about any outstanding issues you have.

1.3. The Project Presentation (10
/
01/200
6 and 1
7/0
1/96)

This is a s
hort (10 min max) presentation to the class about your project. Typical props
include a slide of the chip's floorplan, some layout plots, some simulation results. The
staff can help turn printouts into slides for the overhead projector. Talk about the
inte
resting parts: neat architectural features, what went well, what didn't. Time slot is
determined by lottery and will be posted at the course web site after the proposals have
been turned in.

1.4.
The Project Report Web Page (due
23/01/2006
6)

The final re
port for the project is again in the form of a web page. Your project proposal
is a good place to start. Your report should address the following: architectural design,
external chip interface, internal subsystem functionality and interfaces, floorplan, ge
neral
routing of power and clocks, control subsystem design, clocking strategy, test strategy,
initial and final designs of cells, initial and final area speed estimates.




2.
Project proposals


1.
Transmitter Equalizer.



The goal of this project is to build the 4GHz equalizing FIR filter for a differential
transmitter. The equalizer cancels the frequency
-
dependent atte
nuation caused by the
skin
-
effect resistance of copper wire giving a frequency response that is flat to within 5%
over the band from 200MHz to 2GHz even over wires with 6dB of high
-
frequency

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attenuation, and thereby allows dependable transmission of high
-
f
requency signals with
no intersymbol interference.



2.
Prime Factorization Chip.



The goal of this project is to c
reate a prime factorization algorithm in VLSI. Repeated
subtraction is used to implement the required division operation. The chip accepts a 15
-
bit input number and outputs its prime factors. It begins by testing the numbers 2, 3, 5,
and every subsequent o
dd number. When the system discovers a number that is a factor
of the input, it checks to see whether the factor is prime or not. If the factor is prime, it is
sent to the output, otherwise the system procedes to identify the next factor.


3.
MIDI decoder and sound synthesis controller.



The VLSI system will take MIDI input signals with the aid of a clocked UART chip, and
w
ill produce control signals for synthesis subsystems, which will consist of EPROMs,
D/A converter(s), and PALs. The system must produce the necessary control signals at
specific rates, depending on the frequency/tone requested by the MIDI input. The system

should provide controls for at least four subsystems so that at least four voices/tones may
play simultaneously. Mixing of the waveforms may be done either before or after the
D/A conversion with external circuitry.


4

ZF8081
--

a small microprocessor.



The goal of the project is to implement a full functioned microprocessor using VLSI
technology. This chip includes a ti
ming generator, a memory address register(MAR), a
memory data register(MDR), a program counter(PC), an Opcode latch and decoder, an
accumulator and an arithmetic
-
logic unit (ALU). The data width is 16
-
bit, the address
length is 13
-
bit and the Opcode length

is 3 bit (load, store, add, AND, XOR, OR...).


5.
El Cheapo PIC.



The goal of this 6.371 project is to design and i
mplement a PIC
-
like microcontroller
called the ecPIC. Like a PIC, this processor will implement a load store, Harvard
architecture capable of executing 1 instruction per cycle. The ecPIC will feature 8 output
lines for controlling devices. Unlike a PIC, th
is processor will not feature any pipelining
and will have fewer arithmetic and control operations. Furthermore, the instruction
memory will be located off the chip.



6.
ALU and Register File.



After contemplating implementing a microprocessor compatible with the Beta
instruction set, it was decided that a more realistic goal would be implementation of the
register fi
le and ALU, and limited control circuitry which would allow their interaction.


5





7.
Basic Microinstruction Sequencer


.

The goal of this project is to create an address sequencer that controls the sequence of
execution of microinstructions stored in microprogram memory. In addition to the
capability of sequential access, it provides conditinoal branching to any microin
struction
within its 4096
-
microword range. A last
-
in, first
-
out stack provides microsubroutine
return linkage and looping capability; there are eight levels of nesting of
microsubroutines.


8.
The Square Root Machine.



The goal of this chip is to produce the square root of a 16
-
bit number with an accuracy of
several decimal places corresponding to 8 bits of precision past t
he decimal point. The
chip is provided with a free
-
running clock, and the 16
-
bit input marked by the DVAL
signal. After a variable number of clock cycles, the integer part of the square root is
output and the INT signal is asserted. A fixed number of clock

cycles later, the fractional
portion of the square root is output, and the FRAC signal is asserted.


9.
An Electron
ic Sunflower.



The goal of this project is to build a machine that will "rotate" itself in order to head
towards the strongest light source in a two dimensional space. The light sensors
(photocells), actuators and power drivers will stay off chip. The ma
chine control will be
accomplished using basic fuzzy logic methods and will be implemented using analog
current mode circuitry


10.
RSA Encryption and Decryption.



The goal of this project is to create an implementation of RSA encryption and
decryption. The message will be doubly encrypted using the receiver's public key and
then the sender's private key. Th
is involves the computation of exponentiation using the
fast mulitplication algorithm and calculation of modulus using the GCD algorithm. The
public and private keys are bit shifted in before the respective messages. This chip can be
used for securing tran
smissions in almost real time. An example would be securing
telephone conversations or credit card transactions by piping the unsecure transmission
through the chip



11.
3D Graphics Rendering Pipeline.



The goal of this project is to implement the transformation module for a 3
-
D graphics
rendering pipeline. Given a point, this module will perform a perspective projection of

6

the point based upon state variables specifying a 3
-
D viewing frustum. This operat
ion
will require fast matrix multiplication of a vector with the matrix specifying the
perspective transformation. Computing the transformed coordinates, as well as deriving
the transformation matrix from the frustum data, will require multiplication, addi
tion, and
division operations within the module.


12.
A Key
-
Agile ATM Cell Encryptor.



We will develop an ATM

(Asynchronous Transfer Mode) cell encryption chip that uses
different keys to encrypt the payload of different cells based on information in the header
of the ATM cell
-

hence the term "Key
-
Agile". Such a chip can be placed at the endpoints
of a point
-
to
-
point connection just before entering and just after exiting a public ATM
network. This would provide security on the overall link, and on the individual sessions
in the stream. This chip, with the addition of another chip to perform interencryptor
Signall
ing, Administrivia, and Management (SAM), can form the "black box" that
operates at the endpoints of the link. The encryption process has the side benefit of
scrambling the data stream to simplify clock recovery circuits at the receiving end
.