EGE535 Low Power VLSI Design

gilamonsterbirdsElectronics - Devices

Nov 24, 2013 (3 years and 11 months ago)

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Damu, 2008

EGE535 Spring 08, Lecture 1

1



EGE535 Low Power VLSI
Design

Damu Radhakrishnan

Dept of Electrical and Computer Engineering

State University of New York, New Paltz, NY 12561

Tel: (845) 257
-
3772


damu@engr.newpaltz.edu

http://www.engr.newpaltz.edu/~damu/spring2008/lowpower.htm



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EGE535 Spring 08, Lecture 1

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Course Objectives


Low
-
power is a current need in VLSI
design.


Learn basic ideas, concepts, theory and
methods.


Gain experience with techniques and tools.

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EGE535 Spring 08, Lecture 1

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Low
-
Power Design


Design practices that reduce power
consumption at least by one order of
magnitude; in practice 50% reduction
is often acceptable.


Low
-
power design methods:


Algorithms and architectures


High
-
level and software techniques


Gate and circuit
-
level methods


Test power

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EGE535 Spring 08, Lecture 1

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Prerequisites



Graduate Standing


Basic background in probability and
statistics


Familiarity with basic MOSFET structure


Analyzed circuits involving transistors


Circuit simulation (PSPICE)



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Topics Covered




MOSFET Basics


Power dissipation in CMOS circuits

Dynamic power



Charging and discharging of load and parasitic capacitances



Short circuit power



Both nmos and pmos conducting simultaneously



Static power



leakage power due to reverse biased pn junctions



sub
-
threshold conduction


Low power analysis and design tools

Analysis, especially

power estimation in CMOS circuits (circuit,
gate and architecture level)


Simulation based approaches (highly computationally
intensive)



Probabilistic approaches (based on random processes
with certain statistical characteristics)

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EGE535 Spring 08, Lecture 1

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Topics Covered

(contd.)


Logic level power optimization


Combinational Circuit


two level and multilevel


Sequential Circuits


state assignment, logic
optimizations




Circuit level power optimization


Logic styles
-

Static, dynamic, pass transistor


Latches and flip
-
flops


Transistor sizing and ordering


Drivers for large loads

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Topics Covered (
contd
.)



Low power design of sub
-
modules


adder, multiplier


Case studies of arithmetic sub
-
modules



-

full adder, 4
-
2 compressor, adder arrays, multiplier etc.



Memory and Multicore design

Mem
ory hierarchy, power consumption in memory systems


Low power memory designs


DRAM and SRAM


Low power datapath architecture


Power reduction in processors



System on a chip

Power reduction at the chip level

Bus power minimization


Clock power


Project presentations?


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EGE535 Spring 08, Lecture 1

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Student Evaluation


Homeworks (15%)


Midterms (30%)


Quiz (10%)


Class Project (15%)


Final Exam (30%): Thursday, May 15,
2008, 2:30


4:30PM, REH111.

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EGE535 Spring 08, Lecture 1

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Power Consumption of VLSI Chips

Why is it a concern?

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EGE535 Spring 08, Lecture 1

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ISSCC, Feb. 2001, Keynote

“Ten years from now,
microprocessors will run at
10GHz to 30GHz and be capable
of processing 1 trillion operations
per second


about the same
number of calculations that the
world's fastest supercomputer
can perform now.


“Unfortunately, if nothing
changes these chips will produce
as much heat, for their
proportional size, as a nuclear
reactor. . . .”

Patrick P. Gelsinger


Senior Vice President

General Manager

Digital Enterprise Group

INTEL CORP.


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EGE535 Spring 08, Lecture 1

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VLSI Chip Power Density

4004

8008

8080

8085

8086

286

386

486

Pentium®

P6

1

10

100

1000

10000

1970

1980

1990

2000

2010

Year

Power Density (W/cm
2
)

Hot Plate

Nuclear

Reactor

Rocket

Nozzle

Sun’s

Surface

Source: Intel


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EGE535 Spring 08, Lecture 1

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SIA Roadmap for Processors (1999)

Year

1999

2002

2005

2008

2011

2014

Feature size (nm)

180

130

100

70

50

35

Logic transistors/cm
2

6.2M

18M

39M

84M

180M

390M

Clock (GHz)

1.25

2.1

3.5

6.0

10.0

16.9

Chip size (mm
2
)

340

430

520

620

750

900

Power supply (V)

1.8

1.5

1.2

0.9

0.6

0.5

High
-
perf. Power (W)

90

130

160

170

175

183

Source:
http://www.semichips.org


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Recent Data

Source:
http://www.eetimes.com/story/OEG20040123S0041

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IC Design Space

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Why worry about power?


Portability: Battery Storage Capacity is the
limiting factor

Multimedia Terminals

Laptop Computers

Digital Cellular Telephony

Personal Digital Assistants

Increasing Prominance of Portable Systems

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EGE535 Spring 08, Lecture 1

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In July 2006, the U.S. Congress approved legislation
instructing businesses to give high priority to energy efficiency
as a factor in determining best value and performance for
purchase of servers1. While Washington may have recently
discovered that higher efficiency server not only reduces
electricity bills but utilize less power for cooling, businesses
have long found that these energy
-
efficient performance
platforms provide tremendous benefits.


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EGE535 Spring 08, Lecture 1

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Battery progress

Factor 4 over the last 10 years!

2X improvements in semiconducors in 18 months

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10 times more charge for lithium
-
ion batteries




A group of researchers have formulated a way of increasing
the capacity of lithium
-
ion batteries. The team lead by Yi Cui at
Stanford University, has built a substrate out of silicon nanowiers
capable of holding ten times more lithium compared to a carbon
solution. Ten times more lithium means 10 times more charge.

“High
-
performance lithium battery anodes using
silicon nanowires.” Nature Nanotechnology,
December 2007


New Battery Technologies


Intel is investigating fuel cells and other exotic options and is
particularly interested in two existing chemistries


advanced lithium
polymer and zinc
-
alkaline, which have the potential to double battery
capacities without significant increase in size or weight.

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Source: S. Borkar, Intel

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Cooling Costs

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IEEE Spectrum, October 2007

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Books on Low
-
Power Design (1)


L. Benini and G. De Micheli,
Dynamic Power Management Design Techniques and
CAD Tools
, Boston: Springer, 1998.


T. D. Burd and R. A. Brodersen,
Energy Efficient Microprocessor Design
, Boston:
Springer, 2002.


A. Chandrakasan and R. Brodersen,
Low
-
Power Digital CMOS Design
, Boston:
Springer, 1995.


A. Chandrakasan and R. Brodersen,
Low
-
Power CMOS Design
, New York: IEEE
Press, 1998.


J.
-
M. Chang and M. Pedram,
Power Optimization and Synthesis at Behavioral
and System Levels using Formal Methods
, Boston: Springer, 1999.


M. S. Elrabaa, I. S. Abu
-
Khater and M. I. Elmasry,
Advanced Low
-
Power Digital
Circuit Techniques
, Boston: Springer, 1997.


R. Graybill and R. Melhem,
Power Aware Computing
, New York: Plenum
Publishers, 2002.


S. Iman and M. Pedram,
Logic Synthesis for Low Power VLSI Designs
, Boston:
Springer, 1998.


J. B. Kuo and J.
-
H. Lou,
Low
-
Voltage CMOS VLSI Circuits
, New York: Wiley
-
Interscience, 1999.


J. Monteiro and S. Devadas,
Computer
-
Aided Design Techniques for Low Power
Sequential Logic Circuits
, Boston: Springer, 1997.


S. G. Narendra and A. Chandrakasan,
Leakage in Nanometer CMOS
Technologies
, Boston: Springer, 2005.


W. Nebel and J. Mermet,
Low Power Design in Deep Submicron Electronics
,
Boston: Springer, 1997.

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EGE535 Spring 08, Lecture 1

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Books on Low
-
Power Design (2)


N. Nicolici and B. M. Al
-
Hashimi,
Power
-
Constrained Testing of VLSI Circuits
,
Boston: Springer, 2003.


V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic,
Digital System
Clocking: High Performance and Low
-
Power Aspects
, Wiley
-
IEEE, 2005.


M. Pedram and J. M. Rabaey,
Power Aware Design Methodologies
, Boston:
Springer, 2002.


C. Piguet,
Low
-
Power Electronics Design
, Boca Raton: Florida: CRC Press, 2005.


J. M. Rabaey and M. Pedram,
Low Power Design Methodologies
, Boston:
Springer, 1996.


S. Roudy, P. K. Wright and J. M. Rabaey,
Energy Scavenging for Wireless Sensor
Networks
, Boston: Springer, 2003.


K. Roy and S. C. Prasad,
Low
-
Power CMOS VLSI Circuit Design
, New York: Wiley
-
Interscience, 2000.


E. Sánchez
-
Sinencio and A. G. Andreaou,
Low
-
Voltage/Low
-
Power Integrated
Circuits and Systems


Low
-
Voltage Mixed
-
Signal Circuits
, New York: IEEE
Press, 1999.


W. A. Serdijn,
Low
-
Voltage Low
-
Power Analog Integrated Circuits
,
Boston:Springer, 1995.


S. Sheng and R. W. Brodersen,
Low
-
Power Wireless Communications: A
Wideband CDMA System Design
, Boston: Springer, 1998.


G. Verghese and J. M. Rabaey,
Low
-
Energy FPGAs
, Boston: springer, 2001.


G. K. Yeap,
Practical Low Power Digital VLSI Design
, Boston:Springer, 1998.


K.
-
S. Yeo and K. Roy,
Low
-
Voltage Low
-
Power Subsystems
, McGraw Hill, 2004.

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EGE535 Spring 08, Lecture 1

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Books Useful in Low
-
Power Design


A. Chandrakasan, W. J. Bowhill and F. Fox,
Design of High
-
Performance Microprocessor Circuits,
New York: IEEE Press,
2001.


R. C. Jaeger and T. N. Blalock,
Microelectronic Circuit Design,
Third Edition
, McGraw
-
Hill, 2006.


S. M. Kang and Y. Leblebici,
CMOS Digital Integrated Circuits
,
New York: McGraw
-
Hill, 1996.


E. Larsson,
Introduction to Advanced System
-
on
-
Chip Test
Design and Optimization
, Springer, 2005.


J. M. Rabaey, A. Chandrakasan and B. Nikolić,
Digital Integrated
Circuits, Second Edition
, Upper Saddle River, New Jersey:
Prentice
-
Hall, 2003.


J. Segura and C. F. Hawkins,
CMOS Electronics, How It Works,
How It Fails
, New York: IEEE Press, 2004.


N. H. E. Weste and D. Harris,
CMOS VLSI Design, Third Edition
,
Reading, Massachusetts: Addison
-
Wesley, 2005.