Dynamic Voltage Scaling

gilamonsterbirdsElectronics - Devices

Nov 24, 2013 (3 years and 6 months ago)

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VADA Lab.


SungKyunKwan Univ.


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Dynamic Voltage Scaling

VADA Lab.


SungKyunKwan Univ.


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Energy Efficient Software for General
Purpose Computing, Trevor Pering, UC
-
Berkeley

VADA Lab.


SungKyunKwan Univ.


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Introduction: Research Spectrum

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SungKyunKwan Univ.


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Introduction: My Contributions


Simulator: Instruction
-
level Energy
Estimation


Software: Energy Efficient Algorithms


OS: Voltage Scheduling Algorithms ***


OS: Multiprocessing for Energy


Microprocessor: Dynamic Caches

VADA Lab.


SungKyunKwan Univ.


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Processor Systems:high
Power


Thinkpad (Pentium)

0.3 Hours/AA


InfoPad (ARM)

0.8 Hours/AA


Toshiba Portable (486)

0.9
Hours/AA


Newton (ARM)

2.0 Hours/AA


Device (Processor) Processor
System Lifetime

VADA Lab.


SungKyunKwan Univ.


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Do We Just Optimize Power?


Operations per Battery Life:


Minimize Energy Consumed per
Operation


Operations per Second:


Maximize Throughput

Operations/
second

VADA Lab.


SungKyunKwan Univ.


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Ultra
-
low power Infopad Project

VADA Lab.


SungKyunKwan Univ.


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Voltage Scaling


Merely changing a processor clock frequency
is not an effective technique for reducing
energy consumption. Reducing the clock
frequency will reduce the power consumed by
a processor, however, it does not reduce the
energy required to perform a given task.


Lowering the voltage along with the clock
actually alters the energy
-
per
-
operation of the
microprocessor, reducing the energy required
to perform a fixed amount of work.

VADA Lab.


SungKyunKwan Univ.


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VADA Lab.


SungKyunKwan Univ.


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OS: Voltage Scaling

VADA Lab.


SungKyunKwan Univ.


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DVS

VADA Lab.


SungKyunKwan Univ.


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Dynamic Voltage Scaling

VADA Lab.


SungKyunKwan Univ.


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DVS Scheduling Framework

µProc. Speed

Time

Start

Deadline

Start

Deadline

Idle time
represents
wasted
energy

Lower speed,

Lower voltage,

Lower energy

Energy
~

Work • Speed

Work

Work


Use real
-
time framework to

constrain task voltage scheduling

VADA Lab.


SungKyunKwan Univ.


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DVS Simulation

Speed

Time

S
1

S
2

S
3

D
1

D
3

D
2

Task
Variance

Weather

Interrupts

User
Input

Cache
Behavior

Scheduling
Overhead

Intercom

Reality

Theory

Implementation


Simulate run
-
time scheduler to

fully understand voltage
-
scaling behavior

VADA Lab.


SungKyunKwan Univ.


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Simulation Infrastructure


GUI

Run
-
time

Scheduler

Voltage

Scheduler

Application

support libraries

MPEG



Priority 80

GUI



Priority 23

Speed



Priority

{


Frame_Start(deadline);


Decode_MPEG_Frame();


Frame_Finish();

}

Windowing

Cryptography

I/O Support

lpARM

MPEG


Develop support environment to

model complete software system

VADA Lab.


SungKyunKwan Univ.


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Results: Run
-
Time Voltage
Scaling


73%
58%
25%
16%
65%
46%
15%
20%
0%
20%
40%
60%
80%
100%
Audio
GUI
MPEG
Audio &
MPEG
Total System Energy
DVS Simulation
Post-Trace Optimal
Normalized
to 3.3V
fixed
-
voltage
processor

Combination
of independent
benchmarks


Dynamic Voltage Scaling

significantly reduces energy dissipation!

VADA Lab.


SungKyunKwan Univ.


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Run
-
Time Performance Analysis


Frame Computation Histogram
0%
20%
40%
60%
80%
100%
Fixed-V Frame Execution Time
Audio
GUI
MPEG
DVS System Energy
0%
20%
40%
60%
80%
100%
Total System Energy
Basic Algorithm
Adjusted Algorithm
Post-Trace Optimal
Audio

MPEG

GUI

Software can automatically
recognize and adjust for

bi
-
modal GUI distribution

0

2x
deadline

Normalized to
deadline at max
processor speed


Application characteristics strongly affect

voltage scaling performance

VADA Lab.


SungKyunKwan Univ.


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Variable Supply Voltage Block Diagram


Computational work varies with
time. An approach to reduce
the energy consumption of
such systems beyond shut
down involves the dynamic
adjustment of supply voltage
based on computational
workload.



The basic idea is to lower
power supply when the a fixed
supply for some fraction of
time.


The supply voltage and clock
rate are increased during high
workload period.

VADA Lab.


SungKyunKwan Univ.


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Data Driven Signal Processing

The basic idea of averaging two
samples are buffered and their
work loads are averaged.

The averaged workload is then
used as the effective workload to
drive the power supply.

Using a pingpong buffering
scheme, data samples I
n +2
, I
n +3

are being buffered while I
n
, I
n +1

are being processed
.

VADA Lab.


SungKyunKwan Univ.


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Simplest Approach: Compute
ASAP

VADA Lab.


SungKyunKwan Univ.


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Another Approach: Reduce Clock
Frequency

VADA Lab.


SungKyunKwan Univ.


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Voltage Scheduling II

VADA Lab.


SungKyunKwan Univ.


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Evaluation: Algorithms

VADA Lab.


SungKyunKwan Univ.


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OS: Voltage Scheduling

VADA Lab.


SungKyunKwan Univ.


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Run
-
Time Scheduling Dynamics


µProc. Speed

Time

Thread accomplishing
more than expected,

reduce speed

Deadline exceeded,

increase speed

Higher
-
priority
task

Run faster
to make up
lost time

Initial speed
estimate

Optimal
schedule

E(work)

Workload calculated to be
average of previous frames


Periodically re
-
evaluate schedule to

adjust for unforeseen events

VADA Lab.


SungKyunKwan Univ.


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Vertical Layering

VADA Lab.


SungKyunKwan Univ.


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Optimal Scheduling


For a region spanned by a given task
specification, each point in time will either be
scheduled at the minimum speed spanned by
that task or else the task will not be
scheduled to run at that point.


Algorithm



n tasks to schedule


O(
n
) speed settings to consider for each task


O(
n
) linked tasks requiring adjustment for
each setting: Total complexity: O(
n 3
) time.

VADA Lab.


SungKyunKwan Univ.


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SungKyunKwan Univ.


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SungKyunKwan Univ.


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SungKyunKwan Univ.


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SungKyunKwan Univ.


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SungKyunKwan Univ.


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SungKyunKwan Univ.


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SungKyunKwan Univ.


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[Ishihara98]
-

Dynamic voltage scaling with non
-

constant
capacitances

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SungKyunKwan Univ.


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SungKyunKwan Univ.


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SungKyunKwan Univ.


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SungKyunKwan Univ.


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