Digital Control of Power

gilamonsterbirdsElectronics - Devices

Nov 24, 2013 (3 years and 6 months ago)

127 views

Digital Control of Power

“a Different Way of Thinking”

Rob de Nie

Digital Control of Power

TUE guest lecture

05, OCT, 2010

PUBLIC

Outline

Pro’s & Con’s

Example

Closing the Loop

Communication

Simulation

Prototyping

Conclusions

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


2

PUBLIC

Digital Control: Pro’s and Con’s

Pro’s
:

No aging components determining loop behavior (BOM cost)

Adapt loop parameters on the fly: max. efficiency, non
-
linear control

“Native” communication with outside world: I2C, SMBus, PMBus
TM

“One design fits all” (cost of ownership)

Faster design
-
in cycle

IC manufacturer benefits:


Big
D
, small
a
(mainstream processes, scalability)


Faster simulation, FPGA prototyping


Structural testing instead of functional testing


Less derivatives needed (programmability)

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


3

PUBLIC

Digital Control: Pro’s and Con’s

Con’s:

Traditional solutions for ADC, PID
-
controller and PWM generator are
too big and power
-
hungry

New way of working for application engineers (GUI instead of
soldering)

IC manufacturer drawbacks:


Low voltage + High voltage die’s (Multi Chip Module)


Provide GUI


Other experience needed

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


4

PUBLIC

Example : Point of Load Controller


Definition of PoL

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


5

“Point of Load” is the term used for electronic devices, which:

are low voltage (0.8
-
2.5V), high current (10
-
150A), DC/DC
-
converters

are placed physically close to the load

thereby minimizing self induction and power losses of the power tracks

and allow circuits with different supply voltage be used on the same board

Similar to VRM (Intel), but more general and less demanding



Typical load properties:

low supply voltage with tight tolerances

variable current consumption exhibiting large di/dt’s (10A
-
1000A/
m
s)


PUBLIC

Example:


Point of Load (PoL)

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


6

POL module

PUBLIC

Example


Block Diagram

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


7

Buck

Vout

Vin

Vout, Vin, I_out, I_in, Temp

Digital PoL Controller

PUBLIC

Closing the Loop



Basic Loop Circuit Diagram

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


8

Vin

Vout

PWM

Feedback

Drivers

Loop Controller

Settings

Ideally: Vout = D x Vin

D is on
-
time duty
-
cycle

of Control FET

Fsw = 0.5


1 MHz

Control

FET

Sync

FET


PIP212

“DrMOS”

Voltage mode control

PUBLIC

Closing the Loop


Analog control

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


9


PID controller with external R/C
-
filter

PWM via compare to saw
-
tooth




Advantages


Well known


Cheap


Higher PWM frequencies not too difficult




Disadvantages


Cumbersome application (calculation feedback network, guarantee stability for
all kinds of loads)


Component tolerances


Drifts over temperature and lifetime


No remote controllability

PUBLIC

Closing the Loop


analog transient performance with dual PIP212 + Intersil

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


10

1cm wire

Vout

22.7m
W

magenta

yellow

green

320 mV

12 us

Load step:

2V / 22.7m
W

= 88A

di/dt ~ 33A/
m
s

Fsw = 500kHz

dual
-
phase:

1 MHz eff.

PUBLIC

Digital control


ADC, PID, DPWM

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


11

Discrete
Compensator
DPWM
SMPC
Sense Circuits
Vref
Ve[n]
d[n]
ADC(s)
+
-
Vo[n]
Coefficients

General straight
-
forward way of implementing PID control

Suitable for steady
-
state operation

]
2
[
8546
.
1
]
1
[
7685
.
2
]
[
204
.
1
]
1
[
]
[







n
Ve
n
Ve
n
Ve
n
d
n
d
duty
-
cycle

(previous) error samples

10
-
bit

13
-
bit

Chip boundary

Vout

PUBLIC

Digital control


ADC

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


12

Reducing necessary bit
-
width of ADC

Discrete

Compensator

DPWM

SMPC

Sense Circuits

Vref window

d[n]

Flash

ADC

Ve[n]

13
-
bit

4
-
bit

12
-
levels

]
2
[
8546
.
1
]
1
[
7685
.
2
]
[
204
.
1
]
1
[
]
[







n
Ve
n
Ve
n
Ve
n
d
n
d
Vout

PUBLIC

Digital control


PID controller

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


13

Solution for (fast) calculation of new duty
-
cycle

]
2
[
8546
.
1
]
1
[
7685
.
2
]
[
204
.
1
]
1
[
]
[







n
Ve
n
Ve
n
Ve
n
d
n
d
A

B

C

LUT
-
A

(13x24
-
bit)

LUT
-
B

(13x24
-
bit)

LUT
-
C

(13x24
-
bit)

reg Ve[n
-
1]

(4
-
bit)

reg Ve[n
-
2]

(4
-
bit)

reg d[n
-
1]

(13
-
bit)

Ve[n]

4
-
bit

+

d[n]

Note: PID controller uses only


12 comparators (000
-
FFF)


to encode errors

6 … +6


in 4 bits (0
-
C
-
> 13 values)

trunc

13
-
bit

New

content

PUBLIC

Digital control


Digital Pulse
-
Width Modulator (DPWM)

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


14

Counter solution would require very high clock frequency (>1GHz)

Therefore
SD
-
modulation implemented


(average duty
-
cycle is accurate)

2
nd
-
order
SD
-
modulation used,
because 1
st
-
order results in too
much repetitive disturbance

PUBLIC

Digital control


Transient Improvement

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


15

PID

Compensator

DPWM

SMPC

Sense Circuits

Vref window

d[n]

Flash

ADC

Ve[n]

13
-
bit

4
-
bit

12
-
levels

Improved transient response

Vout

Large signal

compensator

tr
-
mode

PUBLIC

Digital control


non
-
linear, time
-
optimal

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


16

When a light
-
2
-
heavy load
-
step is detected
by the transient detector, the high
-
side switch
is switched on immediately


After some time the inductor current will be
equal to the load current and Vout will start to
rise

At the valley
-
point it can be calculated how
much lost charge has to be made up for
(shaded tri
-
angle). L and C have to be known

Optimal t
on

and t
off

can be determined and
sequence executed, after which the control
can be handed back to the PID controller

PUBLIC

Digital control


non
-
linear, minimum deviation

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


17

Transient detected when v
out
(t)
(black)

crosses v
c
-
(t) or v
c
+
(t)


At the crossings of v
out
(t)
(black)

with red
curve (extreme points),

i
L
(t) equals i
load
(t)

At first extreme point c(t) is extended
with t
on
. At second extreme point

c(t) kept low for t
off

After t
off
, control can be handed back
to the PID controller

2
sw
on
T
D
t


2
1
sw
off
T
)
D
(
t



PUBLIC

Digital control


non
-
linear, detection circuit

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


18

L

C
out

ESR

i
L
(t)

i
load
(t)

When i
L
(t) = i
load
(t) :

I
ESR

= I
Resr
= 0

When ESR x C
out

= R
esr

x C*:

v
c
(t) becomes perfect reconstruction of intrinsic v
cout
(t)

PUBLIC

Communication

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


19

Digital Control = Digital Power management

PUBLIC

Communication



What can be influenced?

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


20

PUBLIC

Communication



More parameters

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


21

PUBLIC

Simulation


simulation model

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


22

REAL2PWM

Vout_ana <= real(to_integer(unsigned(Vout)))/scale_factor;

Ground <= ‘0’;

Real_to_Float64

Vin

IC model

incl. bondpads

PUBLIC

Simulation


simulation result

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


23

Vout

I_ind

I_load

PWM

30A

Looks

Pretty

Good

BUT…

what

about

real

world?

PUBLIC

Prototyping


setup

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


24

Standard Altera DE2

Development board

Companion board with

mixed
-
signal part and application

PUBLIC

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


25

Prototyping


FPGA companion board

square

to pulse

PIP

ADC

DAC

Flash

ADC

Vout

Debug

Load switches + resistors

12V

I2C

analog

buffers

3V3

to 5V

PUBLIC

Prototyping


real world behavior translated to simulation

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


26

Initial design behaves improperly

Mainly caused by X
-
talk spikes
induced by LX node

(larger at high current)

Vout

I_ind

30A

100 MHz scope bandwidth

When X
-
talk is added to the test
bench simulation model, behavior
looks similar

PUBLIC

Prototyping


result after design has been hardened against X
-
talk

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


27

Measures taken in IC design

(NOT in application!) to counteract
X
-
talk influence yield again a nice
behavior in simulation

And, when put into FPGA,
real
-
world prototype
behavior is fine as well

100 MHz scope bandwidth

PUBLIC

Prototyping

Response to 30A load step with and without

Transient Improvement

PID only

Vout

I_inductor

540 mV

50
m
s

PUBLIC

Simulation revisited


adding X
-
talk in simulation model

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


29

REAL2PWM

Vout_ana <= real(to_integer(unsigned(Vout)))/scale_factor;

Ground <= ‘0’;

Real_to_Float64

Vin

X
-
talk
generator

Vout_ana <= real(to_integer(unsigned(Vout)))/scale_factor


+ xtalk_real;

100nF

Real_to_Float64

$bits

2real

IC model

incl. bondpads

PUBLIC

Conclusions

“Full” digital control can do the job !

Sticking to linear behavior will not always yield optimal performance.

Sticking to “classic” digital implementations will not always yield
minimum area.

Use best of both worlds.

FPGA prototyping will most likely reveal real
-
world problems early
-
on
and gives the opportunity to fine
-
tune simulation models for verification.


November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


30

PUBLIC

November 24, 2013

Subject / Department / Author
-


31

QUESTIONS ?

PUBLIC

Literature

Z. Lukic, N. Rahman and A. Prodic, “”, Multi
-
bit
SD

PWM digital controller IC for
DC
-
DC converters operating at switching frequencies beyond 10 MHz”,
IEEE
Trans. Power Electron
ics, vol. 22, pp. 1693
-
1707, Sep. 2007

Zhenyu Zhao and A. Prodic,

Continuous
-
time digital controller for high
-
frequency DC
-
DC converters”,
IEEE Trans. Power Electron
ics, vol. 23, pp. 564
-
573, Mar. 2008

A. Radic, Z. Lukic, A. Prodic and R. de Nie, “Minimum deviation digital
controller IC for single and two phase DC
-
DC switch
-
mode power supplies”, in

Proc. IEEE Applied Power Electronics Conf. (APEC 2010),

2010, pp. 1
-
6

A. Radic, A. Prodic and R. de Nie, “Self
-
tuning mixed
-
signal optimal controller
with improved load transient waveform detection and smooth mode transition
for DC
-
DC converters”,
Proc. IEEE Energy Conversion Congress and
Exposition (ECCE 2010)

R. de Nie, “Design challenges in the development of mixed
-
signal control IC’s
for switched
-
mode power supplies and their solutions”, in
Proc. IEEE Workshop
Comp. in Power Electronics (COMPEL 2010)

November 24, 2013

Digital Control of Power / Innovation
-
PLS/ R.de.Nie
-


32

PUBLIC

November 24, 2013

Subject / Department / Author
-


33