Server Architectures SMP: Symmetric Multi-Processors - Chevance

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Server Architectures
SMP: Symmetric Multi-Processors
René J. Chevance
January 2005
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© RJ Chevance
Foreword
 This presentation is an introduction to a set of presentations
about server architectures.
They are based on the following book:
Serveurs Architectures: Multiprocessors, Clusters,
Parallel Systems, Web Servers, Storage Solutions
René J. Chevance
Digital Press December 2004 ISBN 1-55558-333-4
http://books.elsevier.com/
This book has been derived from the following one:
Serveurs multiprocesseurs, clusters et
architectures parallèles
René J. Chevance
Eyrolles Avril 2000 ISBN 2-212-09114-1
http://www.eyrolles.com/
The English version integrates a lot of updates as well as a
new chapter on Storage Solutions.
Contact: www.chevance.com
rjc@chevance.com
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© RJ Chevance
Organization of the Presentations
 Introduction
 Processors and Memories
 Input/Output
 Evolution of Software Technologies
 Symmetric Multi-Processors (this document)
 SMP Architecture Overview
 Microprocessors and SMP
 Operating Systems and SMP
 SMP with moderate number of processors(8 processors)
 SMP with Many Processors (16 processors): Nearly UMA Systems, CC-
NUMA, COMA
 Performance Improvement Provided by SMP
 Advantages and disadvantages of SMP architecture
 Partitioning: Virtual Machines, Hardware Partitioning, Logical Partitioning
 Cluster and Massively Parallel Machines
 Data Storage
 System Performance and Estimation Techniques
 DBMS and Server Architectures
 High Availability Systems
 Selection Criteria and Total Cost of Possession
 Conclusion and Prospects
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© RJ Chevance
SMP Architecture Overview
 Symmetric MultiProcessor Architecture
• With SMP, all processorsmay accessto all system resources(memory, I/O). A SMP is operating
under thecontrol of one Operating Systemmanaging all system resources.
• Thenative programming model is thesharing of memory between processes.
Processor
Processor
Processor
SystemController
Memory
I/OController
I/OController
Processor -memory-I/Ointerconnect
I/O bus
or
Système Operating System
DBMS(s)
Middleware
Applications
Hardware resources
(processors,memory,controllers and peripherals)
b) SoftwareViewof aSymmetrical Multiprocessora) Hardwareviewof a Symmetrical Mutiprocessor
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© RJ Chevance
SMP Architecture Overview(2)
 SMP Programming and Execution Model
Process
Processor
Process
Process
Processor
Processus
Processor
Process
Processor
Process
Processor
Process
a) - Uniprocessor b) - Tightly-Coupled Multprocessor/SMP
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© RJ Chevance
SMP Architecture Overview(3)
 Lightweight processes (threads)
 Threads are sharing process resources
 Cost of thread switching is lower than process
switching
Single-threaded
User Process
2GB
Shared
Libraries
Shared
Memory
Stack
Data
Code (text)
0
Proc.Context
Multi-threaded
User Process
Kernel
code
and data
4GB
2GB
Operating
System
Address
Space
u area:Status and control information
associated with the process
User
Address
Space
2GB
Shared
Libraries
Shared
Memory
Data
Code (text)
0
Proc.Context
Stack
Thread 0
Thread n
‘Main’ process
Proc.Context
Stack
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© RJ Chevance
Microprocessors and SMP
 Microprocessors must integrate specific features
to operate in an SMP environment
 Cache Coherence - Illustration
Store '4' ->A
Memory
(1)
Processor
P1
P2
P3
Cache
Load A
Load A
b
A=1
A=1
A=1
Memory
(2)
Processor
P1
P2
P3
Cache
Load A
Load A
b
A=1
A=1
A=1
A=4
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© RJ Chevance
Microprocessors and SMP(2)
 Cache Coherence Protocol (e.g. MESI)
 Memory Consistency
 Synchronization Mechanisms
Invalid
Shared
Exclusive
Modified
Read miss
LB
LB
U
U
Read miss
External write
External write
External
read
External
read
Write hit
Write hit
Read Hit
Read hit
Read hit
Write hit
External write
U indicates an update of the memory
LB indicates loading a blockinto the cache
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© RJ Chevance
Operating Systems and SMP
 Operating systems must be designed for SMP
(e.g. Windows NT) or adpated to SMP (e.g. Unix)
 e.g. transforming an OS for SMP:
 MP Safe Operation then MP efficient
 Transforming kernel processes into threads
 Pre-emptive kernel
 Locking to prevent simultaneous access to shared
resources (e.g. data structures)
 Granularity, number of locks,duration of locks
 Dead locks
 Allocating processes/threads to processors (affinity)
 ……
 Need constant tuning to adapt to changing
characteristics such as the number of
processors,….
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© RJ Chevance
SMP with moderate number of processors
 By 2003, we can assume that up to 8 is a moderate number
of processors (no need to use sophisticated technologies).
This limit is growing with time as microprocessor vendors
integrate more and more system capability into their
silicon.
 Internal Structure of the AMD Opteron Processor
(according to AMD)
DDR Memory
Controller
DDR Memory
Controller
Opteron
Processor
Core
Opteron
Processor
Core
L1
Instruction
Cache
L1
Instruction
Cache
L1
Data
Cache
L1
Data
Cache
L2
Cache
L2
Cache
HyperTransport
HyperTransport
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© RJ Chevance
SMP with moderate number of processors(2)
 4 and 8 processor HyperTransport-based
SMP Systems (according to AMD)
HyperTransport
To AGP Bridge
HyperTransport
To AGP Bridge
HyperTransport
To PCI-X bridge
HyperTransport
To PCI-X bridge
HyperTransport
To PCI-X bridge
HyperTransport
To PCI-X bridge
Southbridge
Southbridge
Opteron
Opteron
Opteron
Opteron
Opteron
Opteron
Opteron
Opteron
8x
AGP
8x
AGP
AGP optional
a) – 4 way SMP
a) – 8 way SMP
Opteron
Opteron
Opteron
Opteron
Opteron
Opteron
Opteron
Opteron
Opteron
Opteron
Opteron
Opteron
Opteron
Opteron
Opteron
Opteron
PCI Adapters
Memory
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© RJ Chevance
SMP with moderate number of processors(3)
 Overview of IBM’s X-Architecture (IBM)
Proc.
Proc.
Proc.
Proc.
Memory
Proc.
Proc.
Proc.
Proc.
Memory
Proc.
Proc.
Proc.
Proc.
Memory
Proc.
Proc.
Proc.
Proc.
Memory
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© RJ Chevance
SMP with moderate number of processors(4)
 Architecture of a 4-Way Itanium-2 Based SMP Server, the
SR870NB4 (Source INTEL)
Itanium 2
Itanium 2
Itanium2
Itanium2
Itanium2
Itanium2
Itanium2
Itanium2
System Bus 6.4 GB/s
Scalable Node
Controller
SNC
Scalable Node
Controller
SNC
6.4 GB/s
DMH
DDR
DDR
DMH
DDR
DDR
DMH
DDR
DDR
DMH
DDR
DDR
Memory
128 GB
Firmware
Hub
I/O Hub
I/O Hub
Scalability Ports
Legacy
I/OHub
PCI-X
Bridge
Hub Interface
1 GB/s per link
PCI-X
Bridge
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© RJ Chevance
SMP with moderate number of processors(5)
 Architecture of a 4-Way Xeon MP-based Server
(according to ServerWorks)
Pentium 4
Xeon MP
Pentium 4
Xeon MP
Pentium 4
Xeon MP
Pentium 4
Xeon MP
Pentium 4
Xeon MP
Pentium 4
Xeon MP
Pentium 4
Xeon MP
Pentium 4
Xeon MP
GC HE
GC HE
CIOB-X
CIOB-X
IMBus
CIOB-X
CIOB-X
CIOB-X
CIOB-X
PCI-X
DDR 200
DDR 200
DDR 200
DDR 200
16 B
CSB5
Legacy I/O
CSB5
Legacy I/O
32-bit PCI
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© RJ Chevance
SMP with moderate number of processors(6)
 Crossbar-based Architectures: Sun Fire
3800 Architecture (Source:Sun)
Processor
& E Cache
Memory
8 GB
CPU Data Switch
Processor
& E Cache
Memory
8 GB
2.4 GB/sec2.4 GB/sec
2.4 GB/sec2.4 GB/sec
Processor
& E Cache
Memory
8 GB
CPU Data Switch
Processor
& E Cache
Memory
8 GB
2.4 GB/sec2.4 GB/sec
2.4 GB/sec2.4 GB/sec
Address Repeater
Board Data Switch
4.8 G /sec
4.8 GB/sec
Datapath
Controller
150 million
addresses/sec
4.8 GB/sec
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© RJ Chevance
SMP with Many Processors 16 processors
 Because of the physical and electrical constraints,larger SMP
systems must use a hierarchy of interconnect mechanisms; in a
recursive manner, a large SMP tends to be a collection of smaller
systems,eachof which is itself an SMP
 Sucha hierarchy means that memory access times differ - whena
processor accesses its own memory,it will see a much shorter
access time than when it accesses memoryin a distant module.
This non-uniformityof memory access times canhave a major
effect on systembehavior andon the software running on it
 The degree of uniformity allows us to distinguish twoclasses of
SMP systems.
 Systems in which access to any memory takes an identical amount
of time, or very nearly identical are called(respectively) UMA - for
Uniform Memory Access - or nearly UMA .
 Systems in which there is anoticeable disparity in access times - a
factor greater than 2 - are referred to as CC-NUMA, for Cache-
Coherent Non-Uniform MemoryAccess
 This classification is purely empirical,and its practical
significance is that in a distinctly NUMA system, software must -
for maximum efficiency- take account of the varying access
times.The amount of work neededfor this adaptation tends to
increase with the NUMA ratio.
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© RJ Chevance
Nearly UMA Systems
 Fujitsu Prime Power System architecture
(simplified) (after Fujitsu)
Processors
Memory
PCI cards
L1 Crossbar
System card
Up to 8 cards
(32 processors)
L2 Crossbar
Cabinet
(32 processors)
M
P
P
P
P
PCI
L1
L2
L2
L2
L2
Memory latency: 300 ns when a L2 crossbar is part of th
access path (one may assume 200 ns for local access time)
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© RJ Chevance
Nearly UMA Systems(2)
 HP Superdome
 HP Superdome Cell (after HP)
Cell
Controller
Memory
Up to 16 GB
PA
-
8600
PA
-
8600
PA
-
8600
PA
-
8600
Crossbar
I/O
Controller
ASIC
PCI
ASIC
PCI
ASIC
PCI
ASIC
PCI
1.6 GB/s
6.4 GB/s
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© RJ Chevance
Nearly UMA Systems(3)
 HP Superdome Architecture (after HP)
I/O
Cell
Crossbar
Crossbar
Crossbar
I/O
Cell
Crossbar
BackplaneBackplane
CabinetCabinet
Memory latencies for a fully-loaded system
are said to be:
• within-cell: 260 ns;
• on the same crossbar: 320 to 350 ns;
• within the same cabinet: 395 ns;
• between cabinets: 415 ns.
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© RJ Chevance
Nearly UMA Systems(4)
 IBM pSeries 690
 Structure of Power4 MCM (after IBM)
CPU
Core
CPU
Core
L3 Dir.
Shared L2
Chip-Chip Comm.
CPU
Core
CPU
Core
L3 Dir.
Shared L2
Chip-Chip Comm.
CPU
Core
CPU
Core
L3 Dir.
Shared L2
Chip-Chip Comm.
CPU
Core
CPU
Core
L3 Dir.
Shared L2
Chip-Chip Comm.
Multi-chip Module Boundary
L3
Memory
Ctrl
L3
Memory
Ctrl
Memory
Memory
GX Bus
GX Bus
L3
Memory
Ctrl
L3
Memory
Ctrl
Memory
Memory
GX Bus
GX Bus
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© RJ Chevance
Nearly UMA Systems(5)
 Architecture of IBM pSeries 690 (after IBM)
P
P
L2
P
P
L2
P
P
L2
P
P
L2
GX
GX
GX
GX
L3
L3
L3
L3
L3
L3
L3
L3
P
P
L2
P
P
L2
P
P
L2
P
P
L2
GX
GX
GX
GX
L3
L3
L3
L3
L3
L3
L3
L3
P
P
L2
P
P
L2
P
P
L2
P
P
L2
GX
GX
L3
L3
L3
L3
L3
L3
L3
L3
P
P
L2
P
P
L2
P
P
L2
P
P
L2
GX
GX
L3
L3
L3
L3
L3
L3
L3
L3
GX
GX
GX
GX
GX Slot
GX Slot
GX Slot
MemorySlot
MemorySlot
MemorySlot
MemorySlot MemorySlot
MemorySlot
MemorySlot
MemorySlot
MCM 0MCM 1
MCM 2 MCM 3
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© RJ Chevance
Nearly UMA Systems(6)
 z900 Hardware Architecture (after IBM)
PU01
L1
PU02
L1
PU03
L1
PU04
L1
PU05
L1
PU06
L1
PU07
L1
PU08
L1
PU09
L1
L2 cache control chip and L2 cache data chips (16 MB shared )
PU00
L1
MBA
1
MBA
0
STI
STI
Memory
card
0
Memory
card
2
Clock
PU0B
L1
PU0C
L1
PU0D
L1
PU0E
L1
PU0F
L1
PU10
L1
PU11
L1
PU12
L1
PU13
L1
L2 cache control chip and L2 cache data chips (16 MB shared )
PU0A
L1
MBA
2
MBA
3
STISTI
Memory
card
1
Memory
card
3
CCE 0
CCE 1
ETR
ETR
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© RJ Chevance
Nearly UMA Systems(7)
 Architecture of a system with 16 Itanium 2
processors (after INTEL)
Itanium
2
Itanium
2
Itanium
2
Itanium
2
SNC
Memory
Firmware Hub
Itanium
2
Itanium
2
Itanium
2
Itanium
2
SNC
Memory
Firmware Hub
Scalability
Port Switch
I/O Hub
Legacy I/O
Controller Hub
PCI-X
PCI-X
Itanium
2
Itanium
2
Itanium
2
Itanium
2
SNC
Memory
Firmware Hub
Itanium
2
Itanium
2
Itanium
2
Itanium
2
SNC
Memory
Firmware Hub
Scalability
Port Switch
I/O Hub
Legacy I/O
Controller Hub
PCI-X
PCI-X
The system is based on 4-processor building blocks, using - here - the Scalability Port Switch and its Scalability Ports.
These provide both connection and coherence, and offer a reasonable NUMA factor - Intel indicates a value of 2.2 for this system.
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© RJ Chevance
Nearly UMA Systems(8)
 Structure Sun’s 3800(8), 4800(12) and
6800(24) Systems (after Sun)
Fireplane address router
Fireplane data crossbar
CPU/
Memory
Board 4
CPU/
Memory
Board 5
CPU/
Memory
Board 6
CPU/
Memory
Board 3
CPU/
Memory
Board 2
CPU/
Memory
Board 1
I/O Assembly 1
I/O Assembly 1
I/O Assembly 2
I/O Assembly 2
I/O Assembly 4
I/O Assembly 4
I/O Assembly 3
I/O Assembly 3
Sun Fire 3800 Server
Sun Fire 4800/4810 Server
Sun Fire 6800 Server
Local memory access time:180 ns, access to memory on another card takes 240 ns
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© RJ Chevance
CC-NUMA Architecture
 Early CC-NUMA systems were based upon 4-way
building blocks (Pentium-based) and used
derivatives of the SCI (Scalable Coherent
Interface). Early systems were characterized by
poor performance
 Principles of CC-NUMA Architecture
Proc.
Cache
Memory
E/S
I/O
Coherent
network i/f
Module
Coherent Network Interconnect
Proc.
Cache
Mémoire
Mémoire
Mémoire
Mémoire
Memory
E/S
E/S
E/S
E/S
I/O
Physical Configuration Equivalent Logical Configuration
Proc.
Cache
Memory
E/S
I/O
Coherent
network i/f
Module
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© RJ Chevance
CC-NUMA Architecture(2)
 CC-NUMA performance is very sensitive to
locality of information. Large NUMA factor (e.g.
above 5) requires extensive software
optimizations
 Some examples of possible optimizations when
NUMA factor is large:
 Affinity scheduling: arranging that a process, once
suspended, is rescheduled on the same processor on
which it last executed in the expectation that the
caches contain useful state from the earlier execution
 When allocating memory, prioritize local allocation
(i.e., allocation within the module on which the
program is executing) above distant allocation
 When a process has had pages paged out, allocate
memory for the pages when paged back in on the
same module as the process is executing
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© RJ Chevance
CC-NUMA Architecture(3)
 General Architecture of SGI Origin 3000
System (after SGI)
Possessor A
Possessor B
Hub
Chip
Memory
and
Directory
I/O
Crossbar
Module 0
Scalable Interconnect Network : NUMAlink = 3.2 GB/sec.
Module 1 Module 255
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© RJ Chevance
CC-NUMA Architecture(4)
 32 and 64 processor SGI Origin 3000
configurations (after SGI)
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
32 processors
64 processors
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© RJ Chevance
CC-NUMA Architecture(5)
 SGI Origin 3000 - 128-processor Configuration
(after SGI)
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
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M
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R
M
M
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M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
R
M
M
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M
M
R
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M
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M
M
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M
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M
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M
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M
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M
R
M
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R
M
M
R
M
M
R
R
R
R
R
R
R
R
128 processors
« Hierachical Fat
Bristled Hypercube »
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© RJ Chevance
COMA Architecture
 COMA Architecture (Cache Only Memory Architecture)
aimed at large SMP: data doesn’t have a fixed place in
memory (that is, has no fixed address in the memory of a
module), and the memory of each module acts as a cache.
Data is moved, by hardware, to where it is being accessed,
and data that is shared for reading may therefore be
resident in several modules at any one time
 Schematic diagram of a COMA architecture
E/S
E/S
E/S
E/S
I/O
Cache
Proc.
Cache
(Memory)
Physical Configuration
Equivalent Logical Configuration
Proc.
Cache
Memory
E/S
I/O
Coherent
network i/f
Module
Coherent Network Interconnect
Proc.
Cache
Memory
E/S
I/O
Coherent
network i/f
Module
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© RJ Chevance
COMA Architecture(2)
 Only one Company (KSR now disappeared) has introduced a
COMA system to the market place
 Advantages:
 because memory is managed as a cache, data is always local to
the module using it
 many copies of data used read-only may exists simultaneously
 Disadvantages:
 the hardware is more complex
 directory sizes increase, as does the time necessary to make
allocate data
 As originally described, COMA required a specific
microprocessor architecture in the area of memory
management (e.g. KSR) and so a very large investment
 S-COMA (Simple COMA), a project at Stanford University), is
using standard microprocessors
Page 32
© RJ Chevance
SMP, CC-NUMA, COMA: a Summary
 The traditional UMA SMP architecture provides the best characteristics as regards
memory access time and the simplicity of the required cache coherence protocols
 CC-NUMA’s data uniqueness property (0 or 1 copies of an object in memory at any time)
simplifies the coherence protocol at the expense of increased access time to data in other
modules
 COMA’s ability to replicate data copies improves effective access time but results in a
greater complexity in the needed cache coherence protocol
VMExtracts
0 or 1 copies,
managed by
the VM system
Virtual
Memory
(VM)
Implementation
of VM
« Classic » SMP CC-NUMA COMA
VMExtracts
0..N copies
Managed by
cachecoherence
VMExtracts
0..N copies
Managed by
cachecoherence
Memory
VMExtracts
0..N copies
Managed by
cachecoherence
VMExtracts
0 or 1 copies,
managed by
the VM system
VMExtracts
0 or 1 copies
VMExtracts
0 or 1 copies
VMExtracts
0..N copies
Managed by
cachecoherence
Cache-coherent
interconnect
Proc.
Cache
Proc.
Cache
Proc.
Cache
Proc.
Cache
Proc.
Cache
Proc.
Cache
Proc.
Cache
Proc.
Cache
Proc.
Cache
Proc.
Cache
Memory
Memory
Memory
Memory
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© RJ Chevance
Performance Improvement Provided by SMP
 A number of factors prevents an N-processor
SMP having N times the performance of a
uniprocessor e.g.
 Contention for the bandwidth of the processor-
memory interconnect increases with the number of
processors
 Contention for shared memory increases with the
number of processors
 Maintaining cache coherence means that cache line
invalidations, and movement of data from cache to
cache, must occur
 Reduction of cache hit rate as a result of more context
switches
 An increase in the number of instructions which must
be executed to implement a given function because of
the existence of locks and the contention for them
 Very few data publicly available about scalability
of SMP
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© RJ Chevance
Performance Improvement Provided by SMP(2)
 Evolution of the behavior of a system multiprocessor
(transactional application and DBMS) according to the
successive versions of software showing the importance of
improvements in the OS and the DBMS (the hardware being
unchanged)
0
1
2
3
4
5
1 2 3 4 5 6 7 8
Number of Processors
Relative Performance
Version i+1
Version i
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© RJ Chevance
Advantages and disadvantages of SMP architecture
Advantages Disadvantages
. Scalability of the system at a moderate cost.. Existence of at least one single point of failure - the
operating system
. Simple performance increase by adding a
card or a processor module
. Maintenance or update activities on the hardware and
the OS generally require the whole system to be
stopped
. Multiprocessor effectiveness - the system
performance increases (within definite limits) as
the num ber of processors grows
. Limitation of the number of processors because of
access contention in the hardware (e.g., the bus) and
software (operating system and DBMS’s).
. Simplicity of the programming model. Upgrade capability limited by rapid system
obsolescence versus processor generations
. Application transparency - single processor
applications continue to work (although only
multi- threaded applications can benefit from
the architecture)
. Complexity of the hardware.
. Availability: if one processor fails, the system
may be restarted with fewer processors
. Adaptation and expensive tuning of the operating
system.
. The ability to partition the system. Necessary application adaptation to benefit from the
performance available.
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Partitioning
 Partitioning divides a single physical SMP system into a number of
independent logical SMPs, each logical SMP running its own OS.
Examples of situations where partitioning is useful:
 when consolidating several servers into a single system (for investment
rationalization, for example), while maintaining the apparent
independence of the servers;
 sharing the same systems between independent activities whose
balance changes over time
 Example of system partitioning:
Proc.
Cache
Proc.
Cache
Proc.
Cache
Memory
SMPPhysical Configuration
Proc.
Cache
Proc.
Cache
Production System
Proc.
Cache
Proc.
Cache
Test System for
New Versions
(Operating System
and/or Applications)
Proc.
Cache
Proc.
Cache
Development
System
Memory
Memory
Memory
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© RJ Chevance
Partitioning(2)
 Techniques of Partitioning
 Virtual Machines (introduced in the late 60’s for mainframes
and widely used, being now used for servers based upon
standard technologies)
 Virtual Machine - Principles of Operation
 Each virtual machine has its own address space and Operating
System (all can be different)
 The Hpervisor executes privilegedmode instruction issued by
guest OS onto real resources
Hypervisor
Proc.
Proc.
Physical
Page
Physical
Page
Storage
Operating
System
Operating
System
Hardware
Resources
Virtual
Machine 1
Virtual
Machine N
Application
Application
Application
Application
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© RJ Chevance
Partitioning(3)
 Hardware Partitioning
 Consists of defining, for a given physical system configuration, a number of
logical systems, each with its own allocation of hardware resources (processor,
memory, controllers and peripherals)
 Logical Partitioning
 Logical partitioning does not require dedication of the physical resources to
logical systems; rather, the resources are managed by a special operating system
which dynamically multiplexes the physical resources correctly between the
logical systems
Proc.
Proc.
Physical
Page
Physical
Page
Storage
Operating
System
Operating
System
Hardware
Resources
Logical
Machine 1
Logical
Machine 1
Application
Application
Application
Application
Virtual System
Abstraction Layer
Virtual System
Abstraction Layer
System Abstraction Layer
Hypervisor
Resource
Management
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© RJ Chevance
Partitioning(4)
 Dynamic partitioning is key for the flexibility of
the operation (otherwise the whole system must
be stopped, reconfigured and restarted). Virtual
Machines and Logical Partitioning facilitate
dynamic partitioning
 Workload Managers:
 Complements an OS by ensuring that a given
application (or set of applications) can be afforded a
guaranteed slice of the actual physical systems
resources (e.g, physical memory, processor time.)
 A Resource Manager reserves sufficient resources to
ensure that critical work may be performed as
required, while allowing a system so support multiple
concurrent applications. When the critical work does
not use all pre-allocated resources, the unused
resource slots may be used by other applications
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© RJ Chevance
Server Consolidation
 The pressure on costs (TCO reduction), information managers are
looking at reducing the number of servers deployed. Several
approaches are proposed such as:
 physical concentration were several servers are regrouped in the same
location possibly in a cluster configuration (offering high availability if
needed);
 concentration were all applications distributed on several servers are
supported on a single system (i.e. in a way similar to the “traditional”
mainframe) with technologies such as:
 Virtual machine approach
 Workload management were a single operating system supports
simultaneously several applications. Resource sharing between applications
is being managed according to a set of stated rules.
 data centric were data is supported by a single (high availability) system,
offering to application servers the data service (application servers does
not support data) ;
 application integration were various applications and associated data are
concentrated on a smaller set of servers in order to facilitate the
cooperation between applications.
 The choice of a solution depends heavily on the characteristics of the
existing configuration and the set of constraints. Obviously, reducing
the number of servers contributes to reduce the TCO. Both cost and
business continuity issues may prevent to go further than physical
concentration.