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ELEC1700
Computer Engineering 1
Week 1
Introduction
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•
Lecturers and tutors:
•
Lecturer and tutor:
»
Mr. Fernando Martinez (first 4 weeks only)
»
fernando.martinez.martos@gmail.com
•
Lecturer and tutor:
»
Mr. Brenton Schulz (rest of the course)
»
vk2mev@gmail.com
Teaching staff
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Lectures, tutorials and hands on
laboratories
Lectures:
Fridays 8:30am
–
11:30am
GP3
-
24
Tutorials/Labs:
Fridays 12:00pm
–
2:00pm
In EE107/8 for weeks 1
-
4, 6
-
9 and 11
end unless specified
otherwise(1
st
floor in Building EE over the Faculty of
Engineering)
In weeks 5 and 10: We will be doing hands on labs in room
EE103a (also 1
st
floor in Building EE over the Faculty of
Engineering)
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•
Because of Occupational Health and Safety rules, nobody is permitted to enter
the Electrical Engineering laboratories without having first passed the Safety
Induction test.
•
The tutorial work in this course is in EE107/108. Access to this room will be
provided by your tutor during normal tutorial hours, however, you will need a
pass to get in outside the tutorial hours.
•
In weeks 5 & 10, however, there will be laboratory work in one of the building
EE laboratories (EE103a), and you will not be permitted to do that laboratory
session until you have done a safety induction test. If you done this induction test
already this year, you don’t have to do it again.
•
It is therefore essential that you pass the Safety Induction test some time in the
first 4 weeks of the semester.
•
Arrangements for taking this test will be announced either in lectures or via
Blackboard. For more details, see
http://www.eng.newcastle.edu.au/eecs/ect/oh&s/generalsafety.html
Safety induction test and guidelines
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•
This year we will have two projects. One combinational project
(for which minimum documentation is needed and will be done
during your normal tutorial time) and a sequential project in which
a proper typed report must be submitted.
•
The demonstration of the second project will be done during your
normal tutorial time. More information about the projects and
project guidelines, can be found in the project guidelines document
and in the course overview.
•
Each student must do ALL projects. Working in groups is NOT
allowed.
Assignment projects
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Questions and help
•
If you have a question on the lecture material, then
1.
Look up a book! Be resourceful
A University degree is a certification of resourcefulness
2.
Ask your tutor during the tutorial session.
3.
Ask the question in Blackboard.
4.
See us during the break or after the tut/lecture.
•
If you come and ask us a question, but obviously haven’t tried to
work it out yourself, then we won’t help you other than to suggest a
book for you to read.
•
If you are still stuck after having tried your best, then we will be
happy to help you.
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Learning resources
•
Blackboard
on
-
line learning system:
blackboard.newcastle.edu.au
course documents (lecture slides, tutorial sheets etc.,
announcements, discussion forums + more)
Students are expected to login regularly
–
recommend daily
Logisim
A logic simulation software which can be down loaded from
http://ozark.hendrix.edu/~burch/logisim
for free an will be used in ELEC1700_NIC extensively.
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http://bit.ly/u3M7An
Textbook
•
Prescribed textbook:
Digital Fundamentals (International Edition,
10e), Thomas L. Floyd
Pearson Education, ISBN: 978
-
0
-
13
-
814646
-
7,
ISBN
-
10: 0
-
13
-
814646
-
2
•
Available in the Co
-
Op bookshop at the
Callaghan campus. Copies are also available in
the Auchmuty Library
•
Students are strongly encouraged to purchase a
copy
•
ELEC1700_NIC will follow this text very
closely
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Assessment
3 quizzes @10% each
30%
2 projects, demonstrated to tutor (5% & 15%)
20%
2 labs @ 5% each
10%
Final Examination
40%
100%
To pass the course you need to have an overall mark
of at least 50%
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Expected workload in ELEC1700_NIC
•
12 weeks of contact, plus final exam period
•
Sample time budget
—
your mileage may vary!
Lectures
–
Attendance/EchoSystem: 3 hours per week
×
12 weeks →
36
Textbook readings:
1 hour per week →
12
Tutorials (incl. in
-
class project demos)
–
Tutorial preparation: 1 hour per week
×
10 weeks →
10
–
Tutorial attendance: 2 hours per week
×
10 weeks →
20
–
Project #1 preparation →
4
–
Project #2 preparation →
12
Labs 1 and 2:
–
Preparation: 1 hour each
×
2 labs →
2
–
Attendance: 2 hours per week for weeks 5 & 10 →
4
Quizzes 1−3
–
Preparation: 3 quizzes @ 5 hours each →
15
–
Completion and attendance (done instead of lecture see above)→
0
Exam
•
Preparation →
10
•
Attendance →
3
•
36 + 12 + 10 + 20 + 4 + 12 + 2 + 4 + 15 + 3 + 10 + 3 =
128 hours
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What’s the temperature?
Ref:
http://bit.ly/wrgSSF
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Graph of an analog quantity
analog
quantity: has continuous values
most natural quantities that we experience are analog:
temperature, speed, force, sound intensity, light intensity, …
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Sampling and quantisation
Sampling
takes snapshots of signal (generally at regularly spaced time intervals)
Quantisation
rounds the amplitude to the nearest predefined value
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Sampling and quantisation
Analog
Sampling
Quantisation
Digital
A
digital signal
takes one of a finite number of values at each
sampling interval
Analog
-
to
-
digital converter (ADC)
converts analog signal to
binary
(a digital form which has only two values instead of many) as a series
of 1s and 0s
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Analog versus Digital
•
As already explained, the real world is basically composed of
Analog signals (voltage, pressure, velocity, temperature etc.).
•
In other words, signals that are continuously changing
with time.
•
Digital signals are Discrete signals in that they can only have
specific values.
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2
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3
Analog signal
Digital signal
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Analog and digital signals
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A Binary Signal
•
A binary signal is a digital signal which has only two finite number of values
(normally two different voltage values represented by High/Low, or ON/OFF,
etc. see next slide).
•
A digital signal need not be constrained to two levels only. Can, in theory, have
generic m
-
ary signals (see previous slide).
•
However, binary format almost universal.
•
Binary system has just two digits: 1 and 0
•
Each digit is called a
bit
=
bi
nary digi
t and
8
-
bits = one
byte
•
We will focus on binary systems in this course.
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Describing binary signals
•
Have two possible states; terminology varies. For positive logic (used in this
course):
True
&
False
High
&
Low
On
&
Off
“1”
&
“0”
(most popular and used in this course)
+5 V (V
CC
)
&
0 V
(based on the TTL logic family) etc.
•
Use these terms interchangeably:
t
i
m
e
V
o
l
t
a
g
e
H
i
g
h
/
O
N
/
"
1
"
/
+
5
V
L
o
w
/
O
F
F
/
"
0
"
/
0
V
B
i
n
a
r
y
S
i
g
n
a
l
Used, as H & L, in most manufacture
data notes
(See 74138 TT)
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Describing binary signals ...
•
Occasionally use
inverted
or
negative
logic:
True
&
False
High
&
Low
On
&
Off
“0”
&
“1”
0 V
&
+5 V (V
CC
)
•
We will be using positive logic in this course.
•
Therefore we can now define the following terms:
–
Logic level:
A voltage level that represents a defined digital state.
–
Logic HIGH (or logic 1): The higher of the two voltages in a binary signal.
–
Logic LOW (or logic 0): The lower of the two voltages in a binary signal.
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Logic levels
•
Digital electronics uses circuits that have
two states
•
These states are represented by two different voltage
levels called
HIGH
and
LOW
•
The voltages represent numbers in the binary number
system
HIGH = 1
and
LOW = 0
•
If the voltage at any given point in our digital circuit is
within the unacceptable logic range, then the digital
circuit will misbehave.
•
There are many reasons why this could happen, but the
main ones are:
(i) Power supply connections not clean (i.e. free of
noise), not connected or of the wrong value
(see
lect1demo1.ewb)
(ii) Overloading of one of the outputs (i.e. the output is
connected to too many inputs
(iii) A short circuit between the track/conductor in
question and any other point.
(iv) Floating inputs (not connected inputs)
(v) Transition between logic states (i.e. 1
0 or 0
1).
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Logic levels…
Range of LOW and HIGH voltages
depends on the digital circuit
technology being used
One type of circuit technology is
“
CMOS
”
CMOS =
C
omplementary
M
etal
-
O
xide
S
emiconductor
For CMOS:
LOW range: 0V to 0.8V
HIGH range: 2V to 3.3V
+3.3V
+0.8V
+2V
0V
Logic HIGH (1)
Undefined logic
Logic LOW (0)
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Logic levels…
Another type of circuit technology is
“
TTL
” (which we will be using in
this course, i.e. in labs and
examples).
TTL =
T
ransistor
T
ransistor
L
ogic
For TTL:
LOW range: 0V to 0.8V
HIGH range: 2V to 5V
+5V
+0.8V
+2V
0V
Logic HIGH (1)
Undefined logic
Logic LOW (0)
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Logic levels…
•
In real life a logic probe or indicator will show the three levels as shown below:
•
However in Logisim here are not such problems, unless we leave a wire
disconnected:
+5V
+0.8V
+2V
0V
Logic HIGH (1)
Undefined logic
Logic LOW (0)
(MultiMediaLogic(MML) Switches & indicators, an alternative free software)
Logic gates (see later)
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Logic levels…
•
Real life switches are as shown below:
SWA
Normally open (A)
Normally closed (NOT A)
(See later)
So to obtain a logic 1 (HIGH), or logic 0 (LOW) we need to wire up
the switch like this:
Key = A
VCC
Key = A
VCC
LOW (0)
HIGH (1)
To rest of the cct
To rest of the cct
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Why use digital (binary)?
•
Easy to implement:
ON = +5 Volts (logic 1) or OFF = 0 Volts (logic 0)
•
Immunity to “noise”:
More immune to noise than analog.
We can reconstruct digital signal even if it is contaminated by (small amounts
of) noise by rounding to the nearest level.
•
Flexibility:
Can treat data, audio, video, images etc in the same way as each other
Can process, store, and transmit data more efficiently than analog
•
Cost:
Digital equipment is cheap, and getting cheaper
v
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1
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Logic level
threshold voltages
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How do we communicate in the real world?
Real
World
Analogue to
Digital
Converter
Digital
System
Digital to
Analogue
Converter
Real
World
i.e.
Transducer
Analogue
Signal
i.e. a voltage
ADC
i.e. computer
Binary
Signal
i.e. 01011001
1 = V
CC
0 = Reference
Binary
Signal
i.e. 01111111
1 = V
CC
0 = Reference
DAC
Analogue
Signal
i.e. a voltage
i.e. Relay,
Indicator, etc.
+ve logic used in this course
+12V
Relay ON
Ex.: D.E.:
Dig. systems 9/16
Dig. systems 8/16
Dig. systems 10/16
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26/10/2012
…and from digital back to analog
Digital
-
to
-
analog converter (DAC)
Digital information stored on compact
disc. Scale at bottom of figure shows
1µm intervals
Ref: M. G. Carasso et al., Compact disc: Digital
audio
, Philips Tech. Rev.
, 40(6):151
–
180, 1982
http://bit.ly/y8Ug2t
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Positive
-
going pulse:
LOW logic level to a HIGH level and then back
again
Negative
-
going pulse
: HIGH to LOW to HIGH
Digital waveforms
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Rise time
t
r
and
fall time
t
f
Measured between 10% to 90% of pulse amplitude
Pulse width
t
w
Measured between 50% points on rising and falling edges
Non
-
ideal pulses
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Digital waveforms
Digital waveforms: series of pulses, changing between LOW and
HIGH levels
These are
ideal pulses
: rising and falling edges change in zero time
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Waveform characteristics
Periodic
pulse waveforms
Composed of pulses that repeat in a
fixed interval called the
period (T)
•
measured in seconds (s)
The
frequency (f)
is the rate it repeats
•
measured in hertz (Hz)
T
f
1
f
T
1
Class exercise:
What is the period of a
repetitive wave if
f
= 1 GHz?
Period =
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Duty cycle
of a periodic waveform is the ratio of
t
W
to
T
•
often expressed as a percentage
•
measures fraction of period for which signal is HIGH
V
olts
T
ime
Pulse
width
(
t
W
)
Period,
T
Duty cycle
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Duty cycle:
Example
Duty cycle
=
t
w
/
T
= 1 / 10
= 10%
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A digital waveform carries binary information
In digital systems, all waveforms are synchronised with a basic
periodic timing waveform called the
clock
Example:
the speed of a computer is measured by the clock
frequency of it’s microprocessor, e.g. 3.5 GHz
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Time to transfer 8 bits in waveform A =
Clock frequency
= 1MHz
Clock exercise:
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A
timing diagram
is used to show the relationship between two or
more digital waveforms
A diagram like this can be observed
directly on a
logic analyzer
Timing diagrams
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Computer
Modem
1
0
1
1
0
0
1
0
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
Computer
Printer
0
t
0
t
1
1
0
0
1
1
0
1
Serial and parallel transfer of data
•
Data can be transmitted by either serial transfer or parallel transfer.
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Oscilloscopes: analog and digital
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1 V per vertical division
2 ms per horizontal division
= 2
×
10
-
3
s
Our Lab Oscilloscope: 2 channel
Tektronix Digital Oscilloscope
Coupling set to D.C.
No inversion
(Unless required)
Set to
×
1 (in our labs, as we are
using BNC
-
4mm cables
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Amplitude
=
Frequency
=
Duty cycle
=
Class exercise:
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Logic
•
Propositions:
statements which are true if certain
conditions are true
•
Example:
“The light is on” is true if:
the bulb is not burned out
AND
the switch is on
•
Boolean algebra
: formulate logic statements with symbols
named after Irish mathematician George Boole c1850s
•
Three basic logic operations: AND, OR, NOT
•
Just the basics today
–
lots
more in Weeks 3 and beyond
•
Logisim:
demo free software package for logic simulation
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True only if
all
input conditions
are true
True only if
one or more
input
conditions are true
Indicates the
opposite
condition
Basic logic operations and symbols
True/false conditions are represented by voltages:
HIGH = true
LOW=false
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NOT
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AND
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OR
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Why do we need to study logic gates?
•
Gates are made out of transistors.
•
Commercially available Integrated Circuits (I.Cs or chips,
see later) are made out of gates.
•
Custom I.Cs are made out of gates and I.Cs.
•
Semiconductor memories (e.g. RAM) are made of gates
as well.
•
Microprocessors are made out of a mix of the above.
•
Therefore if we understand the concepts and basics of
gates we will be able to analyse other more complex
circuits.
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Why do we need to study the basic gates?…
From these:
Q1
Transistor
U1A
AND
Gates
Integrated Circuits (I.C’s)
Memory
Surface mounted
devices
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Dual In line Packages (D.I.P.) and Integrated Circuits
(I.C.’s)
This in an I.C. The physical
package is called a D.I.P.
Notes:
1.
The distance between pins is 0.1” (adjacent) and
0.3” (across the I.C.)
2.
The pins are numbered anticlockwise. Pin 1 is the
first pin on the LHS of the top of the package.
3.
There is always some type of mark on the package
to show which is the top of the I.C.
4.
Most standard digital I.C’s have 0V on pin 7 and
+V
CC
on pin 14.
5.
The name of commercial I.C’s use a number to
specify their function (i.e. 7408)
6.
Gates within the I.C. must be differentiated in
circuits:
U2A
7408N
1
2
3
U2B
7408N
4
5
6
U2C
7408N
9
10
8
U2D
7408N
12
13
11
7408, Quad, two input
AND gate
Real life
DM7408
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Plastic
case
Pins
Chip
Cutaway view of DIP (
d
ual
i
n
-
line
p
ackage)
called DIP because of the two
rows of pins
Integrated circuits (ICs) = “chips”
Small outline IC (SOIC)
s
urface
m
ount
t
echnology
(SMT)
—
saves space
0.6”
0.1”
Pin 1
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SMT packages
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Quad 2
-
input AND gate chip
“Quad”
since there are 4 AND gates in one package
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Complexity classification
Small
-
scale integration (SSI)
up to 10
basic gates
Medium
-
scale integration (MSI)
10
–
100
encoders,
decoders
counters
Large
-
scale integration (LSI)
100
–
10,000
memories
Very large
-
scale integration (VLSI)
10,000
–
100,000
small
microprocessors
Ultra large
-
scale integration (ULSI)
more than 100,000
large
microprocessors
#gates
examples
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Pin numbering
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Laboratory prototyping
We’ll use prototyping
“breadboards” like this with
DIP chips in Labs 1 and 2
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Some applications
•
And
,
or
, and
not
elements can be combined to form various logic
functions. A few examples are:
•
Comparators
•
Mathematical functions like addition
•
Encoding
•
Decoding
•
Multiplexing/demultiplexing
•
Counting
•
Etc.
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Comparison
We’ll learn about binary
codes in Week 2
A
code
is a set of bits arranged in a
unique pattern
•
represents “information”
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Addition
We’ll learn how to design
logic circuits to perform
arithmetic in Week 6
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Encoding
We’ll learn about encoders
in Week 7
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Decoding
We’ll learn about decoders
in Week 7
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Multiplexing/demultiplexing
We’ll learn about
multiplexers and
demultiplexers in Week 7
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We learn about binary codes in Week 2
Counting
We’ll learn about counters
and other devices with
memory in weeks 8, 9 and 10
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Fix
ed OR
array and
output logic
Programmable
AND array
Programmable Logic
•
Programmable logic devices
(PLDs) are an alternative to fixed
function devices. The logic can be programmed for a specific
purpose. In general, they cost less and use less board space that
fixed function devices.
•
A PAL device is a form of PLD that uses a combination of a
programmable AND array and a fixed OR array:
26/10/2012
Week 1
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S
63
Basic setup for programming a PLD or FPGA
We’ll take a look at programmable logic in Week 11
PLD =
P
rogrammable
L
ogic
D
evice
FPGA =
F
ield
-
P
rogrammable
G
ate
A
rray
•
alternative to fixed
-
function ICs
•
PLD/FPGA: highly flexible; less
board space
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