Abstract - PG Embedded systems

feastcanadianSoftware and s/w Development

Dec 14, 2013 (3 years and 8 months ago)

78 views

Real
-
Time I/O Management

System with COTS Peripherals

Abstract


Real
-
time embedded systems are increasingly being built using commercial
-
off
-
the
-
shelf
(COTS) components such as

mass
-
produced peripherals and buses to reduce costs, time
-
to
-
market, and
increase performance. Unfortunately, COTS
-
interconnect

systems do not usually
guarantee timeliness, and might experience severe timing degradation in the presence of high
-
bandwidth I/O

peripherals. Moreover, peripherals do not implement any internal priori
ty
-
based
scheduling mechanism; hence, sharing a device can

result in data of high priority tasks being
delayed by data of low priority tasks. To address these problems, we designed a real
-
time I/O

Management system comprised of 1) real
-
time bridges with I/
O virtualization capabilities, and 2)
a peripheral scheduler. The proposed

framework is used to transparently put the I/O subsystem
of a COTS
-
based embedded system under the discipline of real
-
time

scheduling, minimizing the
timing unpredictability due to
the peripherals sharing the bus. We also discuss computing the
maximum

delay due to buffered I/O data transactions as well as determining the buffer size
needed to avoid data loss. Finally, we demonstrate

experimentally that our prototype real
-
time
I/O man
agement system successfully exports multiple virtual devices for a single physical

device
and prioritizes I/O traffic, guaranteeing its timeliness.











EXISTING SYSTEM

The COTS components are

already designed; a system’s time
-
to
-
market can be reduced

by reusing existing components instead of creating new

ones. Additionally, overall performance
of mass produced

components is often significantly higher than custom
-
made

systems. For
example, a PCI Express 1.0 bus can transfer

data three orders of magnitu
de faster than the real
-
time

SAFE bus. The main challenge when integrating COTS

peripherals within a real
-
time
system is the unpredictable

timing of the I/O subsystem since COTS components are

typically
designed paying little or no attention to worst

case
timing behaviors. In particular, we are
concerned

with I/O subsystems with high bandwidth requirements;

a modern real
-
time system
such as a search and rescue

helicopter may include several high
-
bandwidth

components such as
a Doppler navigation system, a

W
hile priority
-
based real
-
time scheduling is a standard

practice
for CPU task scheduling, it is currently not

supported by COTS peripherals and interconnect
systems. Due to the lack of real
-
time prioritization,

data I/O transactions traveling through the
CO
TS bus into or

out of main memory can suffer unpredictable delay and

cause deadline misses
Similarly, when a COTS device is

shared among multiple tasks, transactions requested by

critical
tasks cannot be prioritized and might be significantly

delayed by ot
her requests coming from low
priority tasks.


Disadvantages



Unfortunately, end
-
to
-
end real
-
time guarantees cannot be achieved unless both tasks and
I/O data transactions are properly processed in a prioritized manner.



This challenge by introducing a
real
-
time I/O management system that supports a wide
range of priority
-
based scheduling policies, retains backward compatibility with existing
COTS
-
based components, and achieves high real
-
time bus utilization without degrading
peripherals’ throughput.



The

design of a real
-
time I/O management system that supports a wide range of priority
-
based scheduling policies for COTS interconnect components



The extension of I/O device virtualization techniques to allow priority
-
based peripheral
sharing



PROPOSED SYSTE
M


The

work presented in one

of our previous
conference.
In particular, we

designed a new
real
-
time bridge with support for I/O

device virtualization that allows a priority driven device

sharing. The new design, which allows individual devices

to be
properly shared among tasks
with different real
-
time

criticalities, increases peripherals utilization and system

scalability
(reducing the number of physical devices

needed). To validate our theory, we also developed a
new

flow analysis and realized an imp
roved real
-
time bridge

prototype based on a faster Power
-
PC processor (compared

with the
Micro blaze

processor in our previous work), in

order to enable
software
-
based flow partitioning. Using this

prototype, we performed new experiments showing
how

we can

now avoid possible deadline misses, in case of

device sharing. However, these
results focus on deriving

the increase in task execution time while neglecting the effect

of delay
on communication flows. Modeling complex COTS

interconnections and estimating
delay and
buffer requirements

or peripheral flows can be done in an AADL
-
based

environment. An event
-
based model may be used to

estimate delay for both computation and communication

activities
in a
multicourse

system
-
on
-
chip (SOC
).


Advantages



The precise
knowledge of COTS behavior implies that these analyses must make
pessimistic assumptions, which can lead to high delay and buffer sizes.



The real
-
time I/O management system removes such unpredictability by creating an
implicit bus schedule.



Analysis
methodologies are available for existing real
-
time interconnections
.




Device virtualization is widely used by Virtual Machine Monitors (VMM) in order to
share a single device among multiple virtual machines.







Modules



Real
-
Time I/O Management



COTS peri
pherals



Prototype



Real
-
Time Bridge



Device Virtualization



Virtual network card interface



Interference among I/O Peripherals


Module Description


Real
-
Time I/O Management

The real
-
time I/O management system

for predictable I/O performance on a COTS
system,
we first

describe the way in which a COTS system typically works.

A COTS system may
include several commercial peripherals,

such as video acquisition boards or network cards,

plugged into standard buses, such as Peripheral Component

Interconnect (PCI) or P
CIe, on a
commercial

motherboard. Data from these boards travel through a

series of bridges and buses
(the specifics depend on the

model of the motherboard), until it reaches main memory,

where the
CPU can read it.


COTS peripherals


The CPU could write da
ta into main memory and instruct the COTS peripherals to
retrieve it. For example, a network card

could be instructed to upload packets which are stored in
RAM. Once an input or output transaction is queued in the

device, the most common policy is
First
-
In

First
-
Out (FIFO). Although our descriptions focus one possible architecture,

our method
is general enough to be applicable to a variety of different COTS systems (for example, where
the main

memory controller is integrated in the CPU die, or where the CPU

is connected to main
memory through a Front Side

Bus (FSB)), as long as main memory is a single resource shared by
the CPU and by peripherals
.



Prototype

The peripheral scheduler is built using the Xilinx ML505 Evaluation
Platform which

features a XC5VLX50T FPGA. We created VHDL hardware code to implement the rate
monotonic scheduling algorithm for strictly periodic tasks, as well the sporadic server algorithm
to schedule aperiodic peripheral bus traffic. The implementation itself is spl
it into two types of
hardware components: 1) servers for each real
-
time bridge,
and a

global scheduling algorithm.
Each server generates a READY signal, and the global scheduling algorithm in this case
executes the task with the highest static priority and

an asserted READY signal.



Real
-
Time Bridge

The real
-
time guarantees on bus communication,

bus access must be controlled according
to the

policy dictated by the peripheral scheduler. Moreover, in

order to safely share a peripheral
among real
-
time tasks

w
ith different criticalities, the device must process transactions

according
to their priorities.


Device Virtualization

In order to distinguish different

flows in the same real
-
time bridge, each packet has to be
read and assigned to its logical flow

before it is scheduled on the bus. Hence, new incoming

packets must be analyzed in the FPGA, while outgoing

packets will be filtered in the main
system. In our current

design, this filter logic is implemented in software

although, for incoming
traffic, a h
ardware module could

be used as well. In our prototype, we developed a driver for the
main system that generates a number of virtual Ethernet

devices equal to the number of flows
supported.


Virtual network card interface

The Sending packets out from the
main CPU works in a

similar way, but in the reverse
order. First, the task binds its

network connection (or datagram flow) with a specific

virtual
network card interface. In this way, the packets will be

prioritized according to the priority of the
corresp
onding

virtual device. As was the case with download, there are

two upload queues for
each virtual device, one for source

addresses and one for destination addresses.


Interference among I/O Peripherals

The goal of the first experiment is twofold. First,
we demonstrate that there is a problem
using COTS interconnect

for a real
-
time system with multiple I/O peripherals. We present an I/O
task set which results in I/O deadline misses when running on a standard COTS bus. Next, we
run the same I/O task set wit
hin our scheduling framework, and show that all deadlines are met.
This demonstrates the non
-
real
-
time nature of COTS interconnect, and validates the correctness
of our solution.


Flow Diagram











CONCLUSIONS

We have presented a framework for
providing real
-
time

control of the I/O peripherals in a
COTS
-
based embedded

system. This framework involves interposing real
-
time

bridges between
COTS peripherals and the COTS interconnect,

all of which communicate with a central
peripheral

scheduler. In t
his way, we are able to schedule bus

transactions within a peripheral
and among peripherals,

such that all I/O deadlines are met. Moreover, we can

prevent data loss
by buffering traffic of high
-
bandwidth

peripherals when bus access is prohibited.

We have
s
hown through experiments that an unmodified

COTS I/O system can cause excessive I/O delay

Leading

to deadline misses, while our
prototype
real
-
time

COTS
-
based I/O framework provides
deterministic delays

and meets all I/O deadlines. We demonstrated the way
in

which classical
uniprocessor scheduling theory can be

applied within our framework, and created hardware logic

To

implement the Rate Monotonic and Sporadic Server

scheduling policies on COTS peripheral
bus traffic. We

provided analysis to determine maxi
mum buffer size and

delay based on the
arrival and service curves of I/O traffic.

One direction for future work is to build upon our

current prototype. We can provide hardware
-
based preprocessing

and filtering on the real
-
time
bridge, which can

be used,
for example, to drop less important packets if the

main CPU is
overloaded.

Another direction we will pursue is expanding our

analysis of the I/O system. Some
transactions occur

between peripherals which do not involve main memory,

and these may be
able to
be scheduled in parallel without causing interference delay. Additionally, we can think of
a

scheduling scheme that allows multiple peripherals to

transmit at the same time if their
interference remains

predictable and bounded. Then, we need to avoid addit
ional

potential
bottlenecks instead of only main memory

bandwidth limits and single
-
device bandwidth limits.
For

example, PCI uses shared bus segments which can be a

bottleneck if multiple I/O
transactions compete for the

same segment.









REFERENCES

[
1] PCISIG, “Conventional pci 3.0, pci
-
x 2.0 and pci
-
e 2.0 Specifications,”

www.pcisig.com,
2009.


[2] K. Hoyme and K. Driscoll, “SAFEbus,” IEEE Aerospace Electronic

Systems Magazine, vol.
8, no. 3, pp. 34
-
39, Mar. 1993.



[3] J. Pike, “Hh
-
60g Pave Hawk,”
www.globalsecurity.org/military/

systems/aircraft/hh
-
60g.htm,
2009.


[4] M. Alvarez, E. Salami, A. Ramirez, and M. Valero, “A Performance

Characterization of High
Definition Digital Video Decoding

Using h.264/avc,” Proc. IEEE Int’l Workload

haracterization

Symp., Oct. 2005.


[5] M.Y. Nam, R. Pellizzoni, R.M. Bradford, and L. Sha, “ASIIST:

Application Specic I/O
Integration Support Tool for Real
-
Time

Bus Architecture Designs,” Proc. IEEE 14th Int’l
Conf.
Eng. Of

Complex Computer Systems (ICECCS), 2009.


[6] J.
-
Y.L. Boudec and P. Thiran, Network Calculus: A Theory of

Deterministic Queuing
Systems for the Internet. Springer, 2001.


[7] S. Bak, E. Betti, R. Pellizzoni, M. Caccamo, and L. Sha, “Real
-
Time

Control of i/o Cots
Peripherals for Embedded Systems,” Proc.

IEEE 30th Real
-
Time Systems Symp., Dec. 2009.


[8] R. Pellizzoni, B. Bui, M. Caccamo, and L. Sha, “Coscheduling of

CPU and I/O Transactions
in COTS
-
Based Embedded Systems,”

Proc. Real
-
Time Syste
ms Symp., pp. 221
-
231, Dec. 2008.


[9] R. Pellizzoni and M. Caccamo, “Impact of Peripheral
-
Processor

Interference on Wcet
Analysis of Real
-
Time Embedded Systems,”

IEEE Trans. Computers, vol. 59, no. 3, pp. 400
-
415, Mar. 2010.