Minutes of the 4.7.02 FED Meeting

fatfallenleafElectronics - Devices

Nov 15, 2013 (3 years and 10 months ago)

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Minutes of the 4.7.02 FED Meeting




Actions from before:


(1)

Fed association to crates still pending….

(2)

Some work needed on the TTC specs document..


A.
PCI vs VME
:
Geoff reports on a meeting happened between Sergio,


Sandro and

others who considered PCI vs VME for the tracker….it turns


out that apart from speed there were no advantages……John presented a


table comparing VME vs PCI. He estimated 4
-
6 months delay in the FED


schedule if we adopt the PCI stan
dard and Geoff asked him to expand his


table and provide more explanations. None in the meeting proposes to


switch to PCI and all prefer VME because of the delays in the FED


schedule (that the switch to PCI would cause) without any

clear


advantage to us since speed is not crucial to the FED.



B.
FE FED Schedule:
John presents the status of the FE module for the


FED. They have reviewed the FE module and they have routed the


sub
-
modules. But have not yet rou
ted the sub
-
modules with each other.


In Johns words:

Carried out internal review of schematics,


layout. Prior to final routing of complete module
(routed


within 3 sub
-
modules) List of (minor) modifications


compiled...Lot of work go
ne into de
-
coupling of FPGAs.


In the event that the opto
-
Rx is re
-
designed they are prepared to


accommodate a new Rx (settling time problems).


Extra work done on decoupling of FPGAs…..


Considering options on how to dissipate the h
eat from the opto
-
Rx.



Need 4 weeks to implement modifications and finish routing….


C. BE FED Status:
John presented the design. Drawing office has entered
signals 98% of BE
-
FPGA. Work is continuing on: TTC interface and
connector, fast signals. Th
e fast signals are driven to the P0 and P2
connectors. Costas wants to discuss this again….Work is also done on VME
interface and power (see John’s notes appended at the end)


Bill Gannon has started working again on the FE
-
FPGA firmware with

Emphasis on t
iming (speed) and implementing modifications.






D.
Schedule:

Several factors influence the scheduled the schedule


(decoupling capacitors, small details..).
At the moment



is appears that t
he first FEDs will come in the



second week in November.


E.
FED Tester at IC:

Matt presents his results on the temperature


sensitivity of the opto
-
Tx. The Tx output changes



by

90 mV/C
0
. Clearly measures have to be taken


to control the temperature of the Tx. Half and hour


of discussion. Ozman, Matt and Costas go away at



the end of the meeting to see what to do. After the


meeting there is agreement between then to:

(1)

Finish the one
-
channel tester board
without


any thermal control

(2)

Use it to investigate
methods for thermal
stability of the Tx modules. The first to try
will be a digital control system involving analog
electronics from Ozman, an ATMEL micro
-
controller and Matt’s method involving the
power resistor and thermistor. Measurements

From Matt, Jam
es show that this system can
achieve a 0.01 degree in temperature stability


NEXT FED MEETING ON MONDAY THE 22.7


at 9:30 @ RAL



John’s notes: CMS
-
FED Progress Report 04.07.02



FE Module :


Carried out internal review of schema
tics, layout.

Prior to final routing of complete module (routed within 3

sub
-
modules)


List of (minor) modifications compiled...

Lot of work gone into de
-
coupling of FPGAs.


Opto Rx:


Settling time problem

2 options allowed for : Extra controls / Capacit
or on output


Thermal. Discussions with Bergquist rep

Heat pads under OptoRx? Better choice would be liquid. Need to

discuss with assembly company.


FE Module now "on hold". But in good shape.

Implement mods and route within next 4 weeks.



BE Module :


3
"blocks":


Combined effort of Designer + Drawing Office


BE FPGA (2000) + QDR SRAMs + TTCrx + PIN DIODE + BUFFERS + J2 +

J0 (SLINK/TTS/VME)


Drawing office has entered signals 98% of BE
-
FPGA.

Decoupling done.

Differential PIN DIODE recommended by Bruce Ta
ylor.

Go with fibre lead from Front Panel connector to TTC at back

end.

Still to include TTC PIN DIODE circuit.

TTS is brought to both J2 and J0

Schematics back from Drawing Office expected for inspection

middle of next week.


VME FPGA (1000) + SYSTEM ACE
+ CONFIG EPROM + SER EPROM +

BUFFERS + JTAG + J1 (VME)


Designer has signal list for 80%. Completed by end of week.

Decoupling done.

Simplified FPGA configuration scheme. No need for second FLASH

memory device.

Simplified JTAG test/load chain.

Expect schem
atics back from Drawing Office for inspection by

middle of week after next.


POWER : PS SUPERVISOR + HOT SWAP CONTROLLERS + DC
-
DC
CONVERTERS

+ LINEAR REGULATOR + VOLTAGE MONITOR + RESET GENERATOR


Preliminary circuit reviewed.

Mods implemented.

Lots of fea
tures: Power from standard VME64x supplies.

Protection against Over Voltage, Under Voltage, Over Current,

Over temp, Monitoring

Drawing office will deliver schematics today.

Internal review Friday.

Publish circuit/documentation.



Lots of details still to

polish off.


Ordering Power block components,

Switch to VME Press fit connectors, VME64x Front Panel (handles), TTC

fibre bushing, component footprint clarifications...



FE
-
FPGA Firmware:


Bill Gannon available.

List of mods to implement...amongst which

Double data rate i/o.

Simplify header checking.

Remove autocal.

Expect to fit in 1500 device.

Rechecking timings with final pin constraints.



Schedule:

Reviewed shedule this week with Designers/Drawing office.

Progress on BE schematics slower than anticip
ated. No one

reason.

Finalising details of signals. More work on de
-
coupling scheme

for FPGAs. Power circuit is more sophisticated.

More detailed week by week schedule.

2 x Assembled cards at RAL : Looks like we slip from end of

September to 2rd week Novem
ber.

Largest uncertainty is time for layout & routing at board level

(allowed 4 weeks Drawing Office).



See web for schematics, docs, component datasheets...



AOB: LEB paper accepted for presentation.

RUWG: Proposal for use of VME64x features for board a
ddressing.