Digital Phase Locked Loops

fatfallenleafElectronics - Devices

Nov 15, 2013 (4 years and 7 months ago)


Digital Phase Locked Loops

Mike DeLong

13 May 2004


The topic for this technical paper will be FPGA implementation of digital phased
locked loops.


The objective of this paper is to explore the history, functionality, uses and FPGA
plementation of digital phase locked loops.


Phase locked loops were first written about but not implemented in the early
1930’s by a French engineer named de Bellescize. In 1932 a group of British engineers
started developing a receiver based

upon de Bellescize’s paper that would be simpler than
the superheterodyne receiver that was the best available at
the time. Their simple designe


a local oscillator, a mixer and an audio amplifier. When the input signal and the
local oscillator
were mixed at the same phase and frequency the original audio was
reproduced from its modulated form. The design was very clever but had its drawbacks.
Reception after a period of time became difficult due to frequency drift of the local
oscillator. The
ir solution to this problem incorporated a phase detector comparing the
input frequency to the frequency of the local oscillator. The phase detector would output
a differential voltage that was fed back into the local oscillator keeping it at the correct
frequency. This technique was the same technique that was developed for electronic
servo control systems at the time. This was the first iteration in the evolution of the phase
locked loop (PLL).

Generally considered better than the superheterodyne re
ceiver, the new phase
locked loop receiver did not see widespread adoption due to the fact that cost of the PLL
outweighed it advantages. With the development of the integrated circuit, the PLL
became available in low cost IC packages. This would drive t
he cost down and allow the
PLL to be adopted in applications outside of specialized situations where the advantages
outweighed the cost.

In the 1940’s the PLL started seeing widespread use in horizontal and vertical
sweep oscillators in television sets.

Since then it has been adopted in AM and FM
demodulators, FSK decoders, motor speed controls and just about anything that involves
a constant frequency that needs to be tracked.

Types of Phased Lock Loops

Before detailed discussion of the FPGA implementa
tion of the PLL can be
explored, the different types of phase locked loops need to be identified. There are
basically three types of phase locked loops, the PLL, DPLL and ADPLL.

First is the PLL. This is basically the original design

about in the

early ‘30s
by de Bellescize. It consists of all analog components and was the standard loop for
many years.

The next type of loop is the DPLL or the digital phase locked loop. This new
version of the PLL was developed in the 1970’s and contained both
analog and digital

On most of these type of phase locked loops, the phase detector was digital and the
oscillator and loop filter on the back end was analog.

The ADPLL or all digital phased locked loop came along a few years after the
DPLL and wa
s an implementation of the PLL with all digital components. Since the
FPGA is an exclusively digital device, the type of device that will be researched in this
paper will be the ADPLL.

Phase Locked Loop Basics

Any phase locked loop must have three basic
components, the phase detector, the
loop filter and the voltage
controlled oscillator. The diagram below shows the basic
setup for the PLL.

The components will differ depending on the chosen type of PLL.

The phase comparator portio
n of the loop compares the signal generated inside of
the phase locked loop to the received signal. In an analog PLL the comparator is simply
a multiplier. The output from the phase comparator will consist of a frequency
component at twice the intended l
ocking frequency and an offset component equaling the
sine of the phase difference between the two signals.

The low pass filter in a PLL filters out the unwanted double
frequency component
which contains no useful information. The constant phase offset

is then passed on to the
controlled oscillator setting it to and keeping it at the

correct frequency.

The ADPLL works differently but based upon the same concept. For a digital
phase locked loop, the input signal is some type of bit stream. T
he bit stream can have a
variety of sources including an analog to digital converter or a regular bit steam with
which the receiver must synchronize. Further Operation of the ADPLL will be discussed
in the next section.

All Digital Phase Locked Loop Desig

and Implementation

In the previous section, the operation of a classic analog phase locked loop was
discussed. And as stated before, operation has the same concept but works differently.
The three main parts of the phase locked loop are still present i
n the ADPLL but they are
designed and constructed differently due to the fact that the signals that they deal with are

and a FPGA is digital
. The input to the ADPLL is a digital stream normally
from an analog to digital converter

or a clock

n this section, the individual components of the ADPLL will be broken down
into their rudimentary components (i.e. counters, control bits, registers). These are the
types of components that can but implemented on FPGA’s therefore this section will be
t ADPLL loop design and FPGA implementation.

The first stage of the ADPLL is the phase detector as it was for the PLL. In the
case of the ADPLL the phase detector consists of either an EXOR gate or an edge
triggered phase detector. The EXOR type is simpl
y an EXOR logic gate.

Below is representation of this kind of gate.

This type of detector locks itself 90 degree behind the phase of the input signal. Two
drawbacks to this type of phase detector is that it has a phase error lim
it of + or

degrees and it is not sensitive to edges in the signal but rather the flat section. Below is
an example of the “locked” state.

One big advantage of this type of phase detector is its simplicity because it consists of
only on

logic gate.

The other type of phase detector is and edge triggered device. This device is a

edge triggered JK device. Its locked state is 180 degrees behind the phase of the input
signal as shown

The device is constructed as shown below.

Since this device is sensitive to the edges, the clock can be eliminated. This device can
be used in conjunction with a counter to output the phase error. This combination is
shown below.











In the configuration shown above, the U0 and U1 are binary values. The MF0 is an
integer multiple (M) of the reference signal

. The counter is reset on the rising edges
of U0 and is gated when the output of Q is logic 1. The ou
tput N of the counter is
proportional to the phase error.

The next stage of the loop is the loop filter. The loop filter that always works
with the EXOR and the edge triggered phase detectors is the K counter. The K counter is
shown below.

K Clock




This loop filter contains two separate counters both of which are counting upward. The
UP/DN bit determines which counter is running at any moment. The K clock is M*F0
where M is a large
integer (8, 16, 32) of the reference signal F0. The carry and borrow
outputs are the most significant bits of the counters and are only high when the contents
of a particular counter are greater than K/2. These values are used to control the DCO
ly controlled oscillator). The counters are reset when the contents reach a value of


The final part of the loop is the DCO (digitally controlled oscillator). In a digital
system, the oscillator is a modified counter. This part of the loop is sho
wn on the next

UP Counter

Down Counter

The DECR and INCR inputs are the carry and borrow outputs from the K counter

. This part of the loop operates in conjunction with a divide by N counter
that works to slow down this accelerated clock. The 2NFc input is t
he center frequency
of the loop (Fc) multiplied by 2N where N is the variable in the divide by N counter. The
two components working together are shown below.

The DECR input to the modified c
ounter causes the take one half
cycle out. Conversely,
INCR inp
ut causes one half
cycle to be taken out of the output. The adjusted
waveform is shown on the next page.

This adjustment is constantly assuring that the cycles stay phased locked.

All of the components discussed above are looped together formi
ng the phase
locked loop. The loop constantly adjusts the produced wave until it is in phase lock with
the input wave. Below is the entire loop wired together.

The phase detector component can be either discussed methods but the rest of the
are as they are shown.

Uses of All Digital Phased Locked Loops

The main uses for this type of digital phase locked loop are clock synchronization.
Clocks can be match or signals with embedded clocks (such as Manchester Encoding)
can be easily synchroniz
ed to. Also, any repeatable code (M
Code) could be
synchronized with a modified version of this loop.

For the loop to synchronize with a
repeatable code, a code generator with an identical code as the unit in the receiver must
be in the loop generating t
he internal code.

The phase detector would also have to be
modified to handle long strings of bits.

FPGA Implementation

Technically the topic of this paper, the FPGA implementation section will be
relatively short. The sections preceding this sectio
n spoke about the individual
components and their workings. Since the components have been broken down into their
rudimentary parts in the previous discussion, the implementation portion becomes
relatively easy. Each part of the loop will be spoken brief
ly about how it could be

The two types of phase detectors discussed earlier in this paper have relatively
simple implementations. The Exclusive
XOR gate has a simple, single gate
implementation. The other type is a JK flip flop. Earlier in

the paper two
D flip flops
and a

XOR gate were

used to build this device. The second part of that phase detector
was a counter with a clock enable and a reset. This is an IP Core part available in the
Xilinx library or a simply coded part consisting of
several embedded IF
ELSIF loops.
An example of this code is shown below.

IF (reset = ‘1’) THEN

Count <= 0;


IF (clk_en = ‘1’) THEN

Count <= Count + 1;





The second part of this loop is the K Counter (loop f
ilter). This part consists of
two reset able, clock enabled
. The implementation for both of these counters is
the same as the count discussed above

except that the reset is based on a maximum value
and both counters must be reset simultaneously.

The next part of this loop is the DCO (digitally controlled oscillator). In this loop,
it is simply a fast running clock that is modified by adding and deleting half cycles.

could be done with a section of code or a modified counter made to respon
d to the INCR
and DECR bits.

The last part of this loop is the divide by N counter. This is a simple counter
made to switch its output
logic level
after N clock cycles.

It can be seen that the FPGA implementation of a device like the one described in
is paper could be relatively easily built. Once the individual parts are analyzed and
broken down,
it can be seen how to build them in a digital system.

Further Studies

An interesting research topic to branch off of this paper would be an all digital ph
ase lock
loop tha
t locks to analog signals. The

in this research paper
synchronizes only
digital type signals. An analog signal could be taken through the analog to digital
converter and locked to in the loop before being retranslated through the di
gital to analog
converter back to analog.

All of the analog math in the analog phase lock loop could be
translated to discrete math and done in an FPGA.


A digital phase locked loop can have many uses. In spread spectrum, the
code or
clock s
ynchronization is an important step in the decoding process. If the
bits or
are out of phase then the decoded bits could be
decoded incorrectly. Also, if
the decoder tries to decode the bits

from the center of the bits then slight va
could cause the decoder to decode the wrong bit

The loop could also be used to
synchronize to a repeatable code. This could be important if the dispreading code needed
synchronized to the input.


Troha, Donald, G. “Digital Phase
Locked Loop Design Using SN54/74LS297.”
Application Notes

5 May 200

Digital Phase Locked Loop
. 5 May 200

Van Roon, Tony.
Locked Loops
. 5 May 2004