Introduction to Bioinformatics - North South University

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Oct 4, 2013 (3 years and 10 months ago)

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Lecture 11

ALU and Control Unit Design

Presented By

Dr.
Shazzad

Hosain

Asst. Prof. EECS, NSU

Hardwired Control Design


Eight Steps to follow

Step 1: Derive the Flow Chart


Start

Stop

R

0

M


Multiplicand via
inbus

Q


Multiplier via
inbus

R


R + M

Q


Q


1

Q=0

Outbus



R

no

yes

Step 2: Obtain register transfer description

Step 3: Specify processing hardware along with various components

Step 4: Complete the design of the processing section

M

L


C

D

C
0
: R ← 0

C
1
: M ←
inbus

C
2
: Q ←
inbus

C
3
: F ← r + l

C
4
: Q ← Q


1

C
5
:
outbus

← R

C
6
: R ← F

R

C

L


D

Q

L

D


C

4

4

C
0

4

4

4
-
bit

adder

F

C
1

C
2

C
3

C
4

C
5

C
6

Z

inbus

outbus

Step 5: Determine the block diagram of the controller

0


1


2


3


4


5


6

Step 6: Obtain the state diagram of the controller

T
0

T
1

T
2

T
3

T
4

T
5

Z=1

Z=0

State Diagram

Step 7: Specify the characteristics of the hardware for
generating the required timing signals

T
0

T
1

T
2

T
3

T
4

T
5

Z=1

Z=0

State Diagram

Step 7: Specify the characteristics of the hardware for
generating the required timing signals

T
0

T
1

T
2

T
3

T
4

T
5

Z=1

Z=0

State Diagram

Step 7: Specify the characteristics of the hardware for
generating the required timing signals

T
0

T
1

T
2

T
3

T
4

T
5

Z=1

Z=0

State Diagram

Step 8: Draw the logic circuit of the controller

Reset

1

3


to


8
Decoder

0


1


2


3


4


5


6


7

T
0


T
1


T
2


T
3


T
4


T
5

unused

C
0
, C
1


C
2


C
3
, C
4
, C
6



C
5

Sequence

Controller

(SC)

Enable


Clear


Load

Clock

Clock

O
2

O
1

O
0

d
2

d
1

d
0

L

Z

Logic Diagram of the unsigned multiplier controller

Sequence Controller Design

T
3

T
5

Inputs

Outputs

Z

T
3

T
5

L

d
2

d
1

d
0

0 1 x

1 0 1 0

x
x

1

1 1 0 1

Truth Table


_

L = Z T
3

+ T
5


d
2

= T
5



_

d
1

= Z T
3


d
0

= T
5


SC Alternative Design

Inputs

Outputs

Z

T
3

T
5

L

d
2

d
1

d
0

0 1 x

1 0 1 0

x
x

1

1 1 0 1

Truth Table

Z


T3


T5


_

L = Z T
3

+ T
5


d
2

= T
5



_

d
1

= Z T
3


d
0

= T
5


L

d
2

d
1

d
0

Micro
-
programmed Control Unit Design


Micro
-
programmed control unit contains programs
written using microinstructions


The programs written in ROM inside the CPU


The microprocessor reads each micro
-
instruction
into instruction register from external memory


The control unit translates the micro
-
instructions for
the microprocessor

Micro
-
instruction format


All micro
-
instructions have two fields


Control word


Indicates which control lines are to be activated


Next address


Specifies the address of the next instruction to be
executed


Design Decisions


Cost of CPU depends on size of control memory


Size depends on length of micro
-
instructions


Major design decision is to reduce the length of
micro
-
instructions


Length depends on two factors


Degree of parallelism: number of microinstructions
that can be activated simultaneously i.e.
control bits


The method by which the address of next micro
-
instruction is determined

Control Bit Organization


Several ways to organize


Assign a single bit for each control line,
unencoded

format


Allows full parallelism


No decoding is necessary


Assign
n

number of bits for 2
n

number of micro
instructions,
encoded
format


Decoding is necessary


Less parallelism

Unencoded

vs. Encoded Format

C
0
:
outbus



X

C
1
:
outbus



Y

1.
Each operation can be performed one at a time, because there is a one
outbus

2.
A single can be assigned for each transfer

Unencoded

format

Two operations are performed

Encoded format

Three operations can be performed

Unencoded

vs. Encoded Format Cont.


If there are eight (8) different operations then 8
different control bits

Ins. Number

C
0

C
1

C
2

C
3

C
4

C
5

C
6

C
7

Operation Performed

1

1

0

0

0

0

0

0

0

outbus



X

2

0

1

0

0

0

0

0

0

outbus



Y

*

*

*

*

*

*

*

*

*

********

8

0

0

0

0

0

0

0

1

X


outbus

Ins. Number


d
2

d
1

d
0

Operation Performed

1

0

0

0

outbus



X

2

0

0

1

outbus



Y

*

*

*

*

********

8

1

1

1

X


outbus

Unencoded

format

Encoded format

Horizontal microinstruction

Vertical microinstruction

Designing Micro
-
instructions


0

1

2

3

4



5

6

Designing Micro
-
instructions

Control Memory

(CM)

6 x 12

3

12

Condition
Select

Branch
Adder

Control
Functions

C
0

C
1

……… C
6

2

3

000 00 000 1100000

001 00 000 0010000

010 00 000 0001101

011 01 010 0000000

100 00 000 0000010

101 10 101 0000000

Micro
-
program

Counter (MPC)

Reset

Load/increment







MUX

0


1


2

1

Z

Vcc

CWR

(Control Word


Register)

Components


Micro
-
program Counter (MPC)


Holds the address of the next micro
-
instruction


Control Word Register (CWR)


Contain three fields


Condition select


Branch address


Control function


MUX (Multiplexer)

References


Chapter 7, Fundamental of Digital Logic and
Microcomputer Design


by M.
Rafiquzzaman