New Substrate for High Performance Graphene transistors

dehisceforkElectronics - Devices

Nov 2, 2013 (3 years and 9 months ago)

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New Substrate for High Performance
Graphene transistors


Kolla
Lakshmi Ganapathi, Navakanta Bhat and
Sangeneni
Mohan

Centre for NanoScience and Engineering (CeNSE), Indian Institute of Science,

Bangalore
-
560012, India


SiO
2
(300 nm)
/Si substrate
has been
extensively used

for

b
ack
-
gate
d

graphene transistors,
because graphene can be easily visualized using optical microscope
on a 300nm SiO
2

layer on
Silicon,
due to optical interference.

But this substrate can limit the device performance
due to

low
gate coup
ling
,

resulting from

low dielectric constant and high thickness
of SiO
2

gate dielectric. This
in turn

requires high gating (switching) voltages.

We
optimized
HfO
2
films
for high performance back
-
gated graphene transistor
,

using
electron beam evaporation. Bilayer graphene

is exfoliated

on

HfO
2
(32nm)/
Si
substrate, and

ide
ntified using optical microscopy

and subsequently confirmed with Raman spectroscopy. High
performance HfO
2

back
-
gated graphene transistor has bee
n fabricat
ed.
We demonstrate highest
transconductance reported till date (60

S

at
V
ds
=100mV
), for back
-
gated bilayer graphene transistor
.
The transconducatance is about 20 times higher than SiO
2
(300 nm)/Si substrate.
The
optimized HfO
2

films also result in slightly lower tarp density compared to
SiO
2
.

For
details:

Kolla Lakshmi Ganapathi, Navakanta Bhat, and Sangeneni Mohan, Appl. Phys. Lett.
103
, 073105
(2013).

http://dx.d
oi.org/10.1063/1.4818467





Fig.
(a)
Bilayer graphene transistor on 3
2

nm
HfO
2
/Si substrate (b) C
-
V characteristics on HfO
2

indicating
high
-
k value
(18.9)

(c)
I
ds

V
g

/V
gmax
curves at V
ds

= 10 mV,
(
inset
HfO
2
/Si,
V
ds

= 100 mV
)
.

(d
)
g
m

V
g

/V
gmax

curves at V
ds

= 10 mV,
(
inset HfO
2
/Si, V
ds

= 100 mV
)
.
(Note: V
gmax
=80V for SiO
2

and
V
gmax
=
4V for HfO
2
)