Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
1
Semiconductor
diode
(pn

junction)
25
December
2012
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
2
The goal.
The goal of this
experiment
is to
measure the
Current

Voltage (I

V) and
Capacitance

Voltage (C

V)
characteristics of
semiconductor diode
(at room temperature and under heating conditions)
and
extract
from the measurements
basic
physical
parameters
/ characteristics
of the
device.
You will
use
Keithley
SCS 4200
measurement system and Agilent 4284A C

R

L
analyzer.
T
he following parameters will be
acquired
from the
I

V
measurements
:
Saturation current
Parasitic series resistance
The following parameters will be
acquired
from the C

V
measurements
:
Built

in voltage of
pn

junction
,
Doping densities
and
Total d
epletion layer
length
and
depletion layers lengths
,
on each side of
the
junction
Total
electric
charge
(per unit area) over the junction
and
electric charges (per unit
area)
on each side of the junction
, namely
and
.
Debye length
for electrons and
holes
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
3
Short theoretical background.
D
iode
[
1
]
is a two

terminal electronic component that conducts electric current in only one
direction.
The term usually refers to a semiconductor diode, the most common type today. This is a
crystal
line piece of semiconductor material connected to two electrical terminals. The most
common function of a diode is to allow an electric current to pass in one direction (called the
diode's forward bias direction) while blocking current in the opposite dire
ction (the reverse
direction).
The semiconductor diode (representing physically a
p

n
junction) is of fundamental importance in
microelectronics. It can be used as
a
rectifier, isolator and voltage

dependent capacitor. Special
modifications of semiconductor diodes are used as solar cells, photodiodes, light emitting diodes
(LEDs) and laser diodes.
pn

junction is also an essential part of Metal

Oxide

Silicon Field

Effec
ts

Transistors (MOSFET) and Bipolar Junction Transistors (BJT).
A p

n junction consists of two semiconductor regions with opposite doping type as shown in
Figure
1
. The region on the left is p

type with an acceptor
density
, while the region on the right is n

type with a donor
density
. The dopants are assumed
to be shallow, so that the electron
s
(hole
s
) density in the n

type (p

type) region is approximately equal to the donor (acceptor) density
(
i.e.
)
.
Figure
1
. Cross

section of a p

n junction
(after [
4
])
.
See
L
ist of symbols for the designation details.
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
4
pn
–
junction at t
hermal equilibrium (zero

biased).
To reach the thermal equilibrium, electrons/holes close to the metallurgical junction diffuse across
the junction into the p

type/n

type region where hardly any electrons/holes are present. This
process leaves the ionized donors (acceptors) behind, creatin
g a region around the junction, which
is depleted of mobile carriers. We call this region the depletion region, extending from
to
. The charge due to the ionized don
ors and acceptors creates built
–
in
difference i
n
potentials
between the two sides of the pn

junction,
(built

in potential). This built

in potential is
also expressed by
the existence of the
built

in
electric field, which in turn causes a drift of carriers
in the opposite
direction. The diffusion of carriers continues until the drift current balances the
diffusion current, thereby reaching thermal equilibrium (zero total current) as indicated by a
constant Fermi energy. This situation is shown in
Figure
2
:
Figure
2
. Energy band diagram of a p

n junction in the thermal equilibrium
(after [
4
])
.
The built

in potential
can be expressed in terms of thermal voltage
and concentrations of
donors
, acceptors
and intrinsic carriers
:
(
1
)
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
5
The typical value of
for a standard Si diode with the typical concentration of dopants (say
and
):
.
C
apacitance
of
the
pn
–
junction at zero
bias
,
,
corresponds to the
total
width
of the depletion
layer
,
,
and
the
dielectric constant
of the semiconductor,
,
as follows:
(
2
)
(where
is a cross

section area of the pn

junction)
The latter expression allows us to estimate the depletion layer width
at
zero bias.
Biased pn

junction
.
Depend
ing
on
the
applied external voltage
,
, t
here are two modes of
diode biasing
:
forward
biased conducting mode and reverse biased blocking mode.
Band diagrams of forward

and
backward

biased pn

junction are shown on
Figure
3
.
Figure
3
. Energy band diagram of a
p

n junction under reverse and forward bias
(after [
4
])
.
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
6
Figure
4
shows
sketch of
I

V characteristics of ideal diode under forward and reve
rse bias.
Figure
4
:
I

V characteristics of ideal diode under forward and reverse bias
(after [
6
])
.
I

V characteristics of
the
biased pn
–
junction.
The current
via the ideal pn

junction (a
ccording to Shockley model
)
has a form
:
(
3
)
where
is a
saturation current
,
is an electron charge
and
is a
thermal voltage.
Note that for
the
room temperature
,
,
. Note also, that
for
and
for
. In our case
,
the condition
corresponds to the
external
voltage
,
while
corresponds to
the
. This means that
for
the
forward biased junction with
,
(
4
)
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
7
while for
the
reverse biased junction with
(
5
)
In other words, for reverse biased junction, current
quickly reaches its saturation value
and stays constant for a long range of the voltages
(up to pinch through).
As opposite to
former, there is no current saturation for the forward bias.
Typical values of the
saturation current
are:
for silicon diodes
for germanium diodes.
Parasitic series resistance.
More accurate
so

called “second

order”
diode
I

V
analysis
predicts that
“real” diode
should
suffer from
the
parasitic
serial resistance
(see
Figure
5
)
. This reduces the voltage that is available to the junction from the external applied
to
the
. Thus, Eq.
(
3
)
should be re

written as:
(
6
)
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
8
Figure
5
. Sketch of I

V characteristics of "ideal" and "real" pn
–
junction
(after [
7
])
.
From Eq.
(
4
)
, in the “far” forward biased
region
, the latter equation can be approximated by
(
7
)
Transformation of this equation
gives:
(
8
)
This allows
us
to
express the series resistance
as follows
:
(
9
)
Thus,
is expected to be a linear function of
.
T
ypical
values of
for
Si diode
are:
.
Capacitance of
the
biased pn
–
junction
.
It is possible to show that
capacitance
(per unit
area)
of
a
biased
pn

junction
,
,
depends on
the
applied
bias
as
follows
:
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
9
(
10
)
where
is a voltage

dependent
total
charge over the pn

junction
, and
is a junction’
cross

section area
.
From Eq.
(
10
)
,
is a linear function of the applied
voltage
:
(
11
)
Built

in voltage
over the junction,
.
From the latter equation
, when
(
i.e.
). This allows
one to
find
the built

in voltage
from the C

V measurements
,
as shown on
Figure
6
.
is obtained at the intersection of the
curve and the horizontal (
i.e.
voltage) axe
.
Figure
6
. Typical graph
s
of C and 1/C
2
for pn
–
junction
(after [
4
])
.
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
10
Dopant densities
and
.
D
oping densities
and
c
an
be obtained from the slope of
the graph
(see e.g.
Figure
6
)
and Eq.
(
1
)
. The slope
is given by:
(
12
)
Th
erefore
,
(
13
)
F
rom Eq.
(
1
)
,
at room temperature
(
i.e.
)
,
for known built

in voltage
and
known intrinsic
carriers’
concentration
(see List of symbols in
Appendix 1
for details)
)
we get
another expression, connecting between the doping densities
:
(
14
)
Thus, from the two independent equations for
doping densities
(Eq.
(
13
)
and Eq.
(
14
)
)
,
one can find
and
of the
device
.
Depletion layer width.
The total width of the depletion layer
for biased
pn

junction also
become
s
voltage

dependent. In particular,
for reverse

biased pn

junction
(
)
holds:
(
15
)
The width of the depletion layers
o
n
the
p

and n

sides
,
and
correspondingly
,
(
for reverse

biased pn

junction
)
is:
(
16
)
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
11
Electric charge over the junction
for reverse bias
.
The total electric charge over the
junction
(
for reverse biase
)
is given by
:
(
17
)
where
is
the
junction
cross

section
area
.
Thus, the total electric charge
per unit area
and electric
charges
per
unit area
on both sides of the junction are:
(
18
)
Debye
length
.
The k
nowledge of
the
dopant densities
,
and
,
allows
one
to estimate
the Debye length (see List of definitions (Appendix 1) for details) for both electrons and holes:
(
19
)
Diode response vs. temperature.
Diode performance is strongly affected by the temperature factor. Consider again the Shockley
model,
in Eq.
(
3
)
has a form:
(
20
)
where:
is an electron charge,
and
are the diffusion coefficients of the electrons on the
p

side and the holes on the n

side,
and
are the diffusion lengths of the electrons on the
p

side and the holes on the n

side,
A
is the pn

junction cross

section area,
are the donors
and acceptors concentrations and
is the intrinsic concentration of Si.
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
12
For simplicity, assume, that
,
,
and
are temperature
independent
. Nevertheless,
the current
in Eq.
(
20
)
does depend
on the temperature, since
is
strongly dependent
on the
temperature. It is possible to show, that
increases approximately
for 7% for each temperature
degree
. Thus, f
or two different temperatures
T
1
and
T
2
holds:
(
21
)
Since
,
there is a mnemonic rule, which says, that
doubles itself
each 10 degrees:
(
22
)
The higher the temperature, the faster grows the forward branch of the I

V characteristics and the
larger the absolute value of the breakdown voltage at the reverse bias.
Figure
7
illustrates the
aforesaid.
Figure
7
. Diode
response
vs. temperature.
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
13
Assignments and analysis
.
Part I.
Room temperature measurements
.
1.
Acquire I

V measurements
of diode using Keithley me
a
surement system. (See
Appendix 2
for details about pin connections and Keithley program
parameters.)
2.
Acquire C

V measurements of diode using Agilent R

C

L meter and Keithley
measurement system. (See
Appendix
3
for details about pin connections
and Keithley program parameters.)
Transfer all the acquired data to Excel.
E
valuation
of physical
parameters
of the diode
from I

V measurements
.
3.
Saturation current
:
the (
averaged
)
current
in the “far” negative
region
.
4.
Parasitic
series
resistance
:
in
the “far” positive
region, from the
graph
and Eq.
(
9
)
,
it is possible to find the range of
,
corresponding to the ideal diode (red line) and another range,
corresponding to the diode with series resistance (blue line).
It is also
possible to find the
itself.
To
do this
:
make in Excel graph
and find (visually) the sections, corresponding to the red
and to the
blue
lines.
make
on the datasheet 3
new
separate
data
columns
:
for the
“blue”
range.
p
lot
graph
for the “blue” range
.
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
14
on the plot
use
“
a
dd
t
rendline”
option
(with “show equation”
box
marked)
,
to
get the
linear equation
, corresponding to the
experimental data
.
(Note th
at
in our case
is
the
“y”
axe
and
is
the
“x”
axe
).
f
rom
the
Eq.
(
8
)
, the slope of the graph
is
, while the
free term is
.
O
n the basis of the linear equation from the previous item, find
for all
the values of
in the “blue” range (make
a
new column
,
“
”
,
in the datasheet)
make
2
additional
plot
s
:
and
.
Evaluation of physical parameters of the diode from
C

V measurements.
5.
Built

in junction
potential
,
.
This potential should be
obtained
at the intersection of the
curve and the horizontal
axe
(
voltage).
In order to get
:
in Excel
,
build the graph
as a function of
voltage
.
add to the graph
the
trend line
with marked option “show equation”.
f
rom the
trend line
equation
,
find
(n
ote th
at
in our case
is “y”
axe
and
is “x”
axe
).
6.
Dopants
’
concentration
and
.
If the slope
, the built

in voltage
,
the intrinsic
carriers’ concentration
and the cross section area of the pn

junction
are known (
see List
of symbols in
Appendix 1
and
Appendix 3
for details))
–
one can find
and
by solving
Eq.
(
13
)
and Eq.
(
14
)
:
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
15
t
he b
uilt

in voltage
was found
on
the previous
step
.
the slope
was also found
on the previous step
from the l
inear fit of
.
and
f
or
the specific diode could be found elsewhere (see e.g.
Appendix 1
).
pn

junction’ cross

section area
,
: f
or 1N4148 Si diode
,
assume
.
7.
Depletion layer w
idth as a function of
the
applied voltage
for reverse bias
.
Using the
known values of
,
,
and
:
compute and
make graph of
depletion layer
total
width
as a function of the applied
reverse
voltage
(see Eq.
(
15
)
).
compute and
add to the
same plot
graphs of
the depletion layers
width
in p

and n

regions,
and
respectively, as a function of
(see Eq.
(
16
)
).
8.
Electric charge over the junction for reverse bias.
On the basis of
the
previous
computations of
and
as a function of
, and
Eq.
(
18
)
,
compute and plot on single graph
the total electric
charge
per unit area
and electric charges
per
unit area
on both sides of the junction,
namely
and
.
9.
Debye length
.
Using
Eq
.
(
19
)
,
compute the
Debye length for electrons
and
holes
.
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
16
Part II.
Measurements under h
eating conditions
.
F
or
the
room temperature AND 3

4
different heating temperatures
, a
cquire
the
I

V measurements
of
the
diode using Keithley measurement system. (See
Appendix
2
for details about
the
pin connections and
the
Keithley program
parameters.)
Note:
in order to
automatically process
measured data with
Matlab
program, after measurements at
each of the temperatures,
save
(from Keithley program):
forward biased
measurement
in the Excel file named
ivfNo
.xls (where No is a serial
number of the measurement);
backward biased
measurement
in the Excel file named ivbNo.xls (where No is a serial
number of the measurement);
For example, assume, that there were
5
measurements at
5
different temperatures, namely
and
. In this case,
data (forward and backward bias)
for
must be saved in
Excel files named
ivf1.xls and ivb
1.xls .The same data, corresponding to the
, must be saved in Ex
cel
file
s named ivf5.xls and ivb5
.xls . Thus, finally you must
get
5
files
ivf
and
5
files
ivb
:
After finishing
the measurements, you can
automatically process the data using Matlab program.
To do this:
1.
Double

click on the zip

file
“Diode heating processing.zip”. In the
newly opened window, folder “
Diode
heating processing” will appear.
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
17
2.
Drag this folder to the Desktop of your computer.
3.
Copy in this folder
all
your Excel files vds.xls and vgs.xls:
4.
Double

click on the file proc
essed_data_
DIODE
.m in the directory “
Diode
heating processing”. This will start Matlab. Wait for 1

2 minutes to allow
Matlab start.
5.
Go to the Matlab Editor window and run the file processed_data_
DIODE
.m
(press F5 or Debug
Run on the Editor menu b
ar)
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
18
6.
The program will ask you to input the temperatures, at which you measured the
diode
. Input the
temperatures in the square parentheses with the spaces between the different valu
es, e.g. [25 35
45 55 65
]. Press Enter to continue.
7.
Wa
it for
approximatel
y
1
minute,
until the program will finish the processing of the measured data.
8.
The results of the computations (Excel file processed_data.xls, Matlab files and figures) are located
in the subfolder Results.
The final report must include the following graphs
with explanations
:
[1]
The graph of forward biased
measurements for all
the temperature
s
.
(
Single figure,
5 different curves
for 5 different temperatures
.
)
[2]
The graph of backward biased
measurements for all the temperatures.
(Single figure, 5 different curves for 5 different temperatures.)
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
19
[3]
The graph of the
saturation current
as a function of temperature,
.
(Single graph, 5 points, corresponding to 5 different temperatures.)
[4]
The graph of the
relative variation of the anode current
versus anode voltage
(forward bias)
for different temperatures.
[5]
The graph of the relative variation of the anode current versus anode voltage
(backward bias)
for different temperatures.
[6]
The graphs of Debye length for electrons and holes
and
as a func
tion of
temperature (two different figures).(The Debye length can be evaluated from
Eq.
(
19
)
.)
[7]
The graph of the total width of the depletion layer
at zero bias
as a function of temperature
.
(The
total width of the depletion layer
can be evaluated from Eq.
(
2
)
.)
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
20
Experimental set

up
and
samples to be studied
T
he experimental setup includes
Keithley matrix and Agilent L

C

R analyzer
(
Figure
10
)
.
(a)
For the room temperature measurements, you will use
Test fixture p
robe station
(
Figure
8
)
(
with dual
in

line package (18 pins) for diodes on Teaching chip No 3,
or
two

pins
connection table
for standard
stand

alone diodes)
, connected
by
the triax cables No 9,10,11,12
to the Keith
ley switching matrix
.
(b)
For the
measurements under
the
heating conditions, you will use the temperature controlling oven
(
Figure
9
)
connected by the triax cables No 5,6,7,8 to the Keithley switching matrix.
Table
1
. Diode samples for available for study
.
Test chip No 3
1N4148 diode
1N4001 diode
Appendix 3
datasheet
Keithley 708A
Switching
Matrix
M
onitor
Figure
10
. Keithley and Agilent L

C

R
measurement setup.
Figure
8
. Test fixture probe station.
Figure
9
. Temperature controlling oven.
Agilent 4284A
LCR meter
Keithley SCS 4200 I

V
AND Parameter analyzer
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
21
Acknowledgement
Electrical Engineering Department of Braude College would thank to
Alexander Goldenberg, Vadim
Go
y
hman, Adi Atias and Moran
Efrony
for
their
extensive help in preparation of this laboratory
work.
Several
parts of this guide were adapted from the
pn

junction
manual of the Advanced
Semiconductor Devices Lab (83

435) of School of Engineering of Bar

Ilan University. We would like
to thank Dr. Abraham Chelly for the granted manual.
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
22
Appendix 1 :
List of symbols and definitions
.
List of symbols
.

pn

junction’ cross

section area
(See
Appendix 3
for the details about the cross

section area of different diodes on the Teaching chip No 3). For the 1N4148 Si diode assume
.

built

in potential
(voltage)
.

intrinsic carriers concentration
. The following table presents
for the basic
semiconductors
at
the
room temperature (T = 300 K)
:
Si
Ge
GaAs
AlAs

holes (electrons) concentration on the p

(n

) side on the pn

junction
.

acceptors (donors) average doping concentration (density)
on
the
p

(n

) side of the
pn

junction
.

parasitic serial resistance in diode
[
]

Debye length
for holes (electrons)
(free path length of non

equilibrium
minority carriers
,
see also List of definitions below)
.

relative dielectric constant
of a semiconductor
[
dimensionless
]
.
The following table
presents relative dielectric constants of the basic semiconductors:
Si
Ge
GaAs
AlAs
11.9
16
13.1
10.9

permittivity of vacuum.

pn

junction capacitance

pn

junction capacitance at zero bias
and

diffusion coefficients of the electrons on the p

side and the holes on the n

side
of the pn

junction
.

saturation current
.
and

diffusion lengths of the electrons on the p

side and the holes on the n

side of
the pn

junction
.

external voltage applied to pn

junction (anode voltage)
.

thermal voltage
.
, where
is a thermal energy (i.e. energy, associated
with the temperature of the object,
). For
the
room temperature
:

total depletion layer width
.
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
23
,

depletion layers width in the p

and n

regions
.
.

max width of the depletion layer in the p

and n

regions
.

Boltzmann constant

temperature
[
deg. K
]

electron charge
.

Fermi and intrinsic Fermi level in semiconductor
.

Fermi level on the p

(n

) side of the pn

junction
.

energy of the bottom of the conduction band and the top of the valence band
.

total charge over the pn

junction
. Note that
is
voltage

dependent
.

total electric charge
per unit area
and electric charges
per unit area
on the
p

and n

sides of the pn

junction
List of definitions
n
+
(n

) semiconductor
n

type semiconductor with high donor density
(
)
and with
low donor density
(
)
correspondingly.
p
+
(p

) semiconductor
p

type semiconductor with high acceptor density
(
)
and with
low acceptor density
(
)
correspondingly.
Inversion

change of carrier type in a semiconductor obtained by applying an external
voltage.
Inversion layer

the layer of free carriers of opposite type at the semiconductor interface
(layer of
electrons in p

type semiconductor and layer of holes in n

type semiconductor).
Debye length

characteristic length
over which the carrier density in a semiconductor changes
by a factor e (~2.71).
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
24
Appendix
2
: Kite settings for
I

V
and C

V
measurements
.
1.
pin
connection scheme:
2.
I

V Keithley settings
Connect pins
SMU 1
(cable 9)
SMU 2 (cable 10)
I

V
measurement
s
LoPin
(cable
12
)
HiPin
(cable 1
1
)
C

V
measurement
s
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
25
forward bi
a
s settings
Expected results
–
forward bi
a
s
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
26
backward bias settings
Expected results
–
backward bias
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
27
3.
C

V Keithley settings
Expected
results
–
C

V measurements (10 kHz)
frequency 1kHz
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
28
Appendix 3 : Teaching chip No 3 diodes specifications
Diodes’ details
and pins
Chip appearance
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
29
Bibliography and internet links
1
Diode at wikipedia:
http://en.wikipedia.org/wiki/Diode
.
2
B. Streetman, S. Banerjee, “Solid state electronic devices” (6th edition), Prentice Hall, 2005.
3
К.В. Шалимова, «Физик
а полупроводников» (3е издание), Энергоатомиздат, 1985.
4
B. Van Zeghbroeck, “Principles of semiconductor devices”, Lectures
–
Colorado University, 2004.
5
A. Chelly, “
pn

j
unction
”, Lab manual

Advanced Semiconductor Devices Lab (83

435), School of
Engineering of Bar

Ilan University.
6
J. Singh, “Semiconductor devices: basic principles”, Whiley, 2001.
7
A. del Alamo. “pn diode characterization”
–
project in the framework of
course
“Microelectronic
Devices and Circuits” (6.012), MIT, 2003.
8
D. Neamen, “Sem
iconductor Physics and Devices: Basic Principles” (3rd edition), McGraw Hill, 2003.
9
S. Kasap, “pn

junction: the Shockley model”. An e

booklet (2001).
10
pn

junction Simulation using Java Applet:
http://jas.eng.buffalo.edu/education/pn/iv/index.html
11
pn

junction properties calculator:
http://www.ee.byu.edu/cleanroom/pn_junction.phtml
2 mm
Silicon chip with PN
junction
Department
of
Electrical and Electronic Engineering
ORT Braude College
Advanced Laboratory
for Characterization
of
Semiconductor Devices
–
31820
Dr. Radu Florescu Dr. Vladislav Shteeman
30
Preparation Questions
1.
Explain (in short) the principle of diode operation
2.
Plot the qualitative graph of diode I

V characteristics
3.
Plot the qualitative graph of diode C

V characteristics
4.
How can you find from the I

V characteristics:
a.
saturati
on current
b.
series resistance
5.
How can you find from the C

V characteristics:
built

in voltage of the pn

junction
doping densities
and
total depletion layer length
and
depletion layer lengths
,
on both sides of the
junction
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