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dehisceforkElectronics - Devices

Nov 2, 2013 (3 years and 7 months ago)

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1)

a)

With a control signal S you should be able to choose which one of the two signals A and B
to be sent to an output Y. When S = 0 you get Y = A and when S = 1 you get Y = B.

Draw a logical sheet for the system. You are free to make
a symbol for a
non
-
inverting tri
-
state buffer and use this symbol in the form.


b)

A microcontroller has an input
WINT

(W for "Wake"). When the microcontroller

is
in sleep mode, a low level on this input
will wake the

microcontroller. Three

external modules should be able
to awaken the microcontroller. They each have their output

W0, W1 and W2, and these output stage
s
are of the "open drain" type.

Create a
sheet

of the links between the modules and the microcontroller.


2)

A logical sheet for a single system is shown in figur
e below :


Figure 1


a)

How many transistors
does the
system
contain?


Create
function table for the system. Then create
a logical expression
with the help of
the

SOP method.

Compared with what you found in
the first question (how many
transistors does the system contain)


b)

You can
make

a logical expression directly from the logical
sheet

in Figure
1
.

Simplify

the expression
with the help of B
oolean

algebra. Compare it

with what you
found in

a) and comment.

Dr
aw the logical form based on this expression. How many transistors
do you need
now?


c)

Logical form for a slightly la
rger system is shown in Figure 2 :




Repeat a) and b) for this system.



3)


a)


Show that:




b)

minimize the following Boolean expression




4)

a)

1
.

Set up a function table 4 → 1
-

multiplexer where

with the help of signals S0 and S1
can
discharge through the output Y one of the input signals X0
-

X3.

2
.

Set up logical equation for Y.

3
.

Drawn up a logical diagram that realizes
the multiplexer. Do no
t
use tri
-
state buffer in this
real realization.




Figure 3




b)

1
-

Set up a function table and logic equation for the simple logic module

Figure 3
.

2
-

The backlog for
the invert

is tP1 and tP2 for OR gate.

Both signals A and B goes from low to high
level at time t0 = 0

At time
t
1
>
t
P1

+
t
P2

goes both signals A and B low again.

Drawn up a
time

diagram for the logic module.


3
-

What can you say about the behavior com
pared to the function table set
up in section
1?