CRCD IN MACHINE LEARNING
EEL4851

ENGINEERING DATA STRUCTURES
Version A1, modified 23 May 2003
Course Module on: “Graph and Network Data Structures for Evolvable Hardware”
EEL4851 is offered to junior

level students in Computer Engineering and Elec
trical
Engineering at the University of Central Florida. The class focuses on the design and
analysis of algorithms and data structures using object

oriented high

level languages such
as C++ and Java. The objective of this machine learning module is to app
ly the concepts
of
Evolvable Hardware
to illustrate various
graph representation
schemes and their
characteristics. The students should already be familiar with linked lists, matrices, and
Boolean logic functions. In this laboratory assignment, the studen
ts are provided with a
fully operational C++ program to evolve a working circuit for a 1

bit adder using two
input Boolean gates. The program evolves a circuit that the students learn to represent as
an adjacency matrix and an adjacency list, and observe h
ow these change during
evolution.
1. Laboratory Assignment Overview
This lab provides hands

on experience with some data structures commonly used to
represent graphs or circuits. Rather than using hypothetical examples, these data
structures used will b
e employed in the context of a machine learning application.
Specifically, circuits will be evolved for a configurable logic architecture using the code
provided. The student will then interpret and compare the resulting data structures
corresponding to
these circuits.
2. Evolvable Hardware Concepts
Evolvable Hardware (EHW)
techniques apply machine learning methods to the
automated design, configuration, or repair of electronic devices. While EHW is a new
and growing field, it has been successfully a
pplied to obtain useful results in a variety of
digital logic and arithmetic circuit applications as well as amplifier circuits, antenna
designs, and other areas. In this laboratory assignment, we will consider using EHW
techniques to design binary adder
circuits in programmable logic architectures such as
Field Programmable Gate Arrays (FPGAs)
.
Here, the fundamental concept behind EHW is to use
Genetic Algorithms (GAs)
to obtain
FPGA configurations autonomously. GAs employ computer programs that repeate
dly
utilize the similar processes that have been observed during natural evolution in
biological systems. GAs view this evolution process as an optimization method where
nature selects the best

suited offspring from the current generation. Through this
s
election process, the useful traits of the individuals in the current generation become
more likely to be propagated to future generations.
In a population

based GA, a computer program is written to perform this process
repeatedly. Population

based GAs
for EHW start out with a random or semi

random
population of designs, each of which constitute potential candidates designs that solve the
problem at hand. These designs are then optimized by applying
genetic operators.
Genetic operators include
crossove
r
of useful traits from 2 existing designs and random
mutation
that adds new traits to individuals in the population. Ideally, after applying
these genetic operators and selecting the best circuits that result from them, each solution
is more optimal than
its predecessors.
3. Operation of EHW Techniques
The EHW technique used here operates as follows:
1.
First, an
objective for the EHW procedure
is specified. In this lab, the objective is
to design a 1

bit adder circuit with carry input. This adder sh
all compute as many
outputs correctly as possible when given a range of inputs. When setting an
objective for the EHW procedure, is important to realize that since EHW relies on
probabilistic techniques, a fully correct design cannot always be guaranteed
especially for complex applications. Although for the 1

bit adder, finding a fully
correct solution is very likely.
2.
Second, a
hardware platform used for the evolution
of the design is selected. In
this lab, an FPGA with programmable logic cell functions
and interconnections
will be used as described below. In order to conduct this lab without any specific
hardware devices or development boards, software programs will be provided to
each student that are capable of simulating the FPGA architecture used o
n a
standard Pentium PC.
3.
Third, the
input parameters are determined and the GA is executed
. In this lab,
fully operational parameterized code is provided to each student that can be
compiled and executed for this purpose without major modification.
4.
Fourth
, the
resulting design represents the desired hardware configuration
. For
example, once obtained then desired configuration can be downloaded to the
specified FPGA chip. In this lab, instead we will be manually interpreting the
program’s output and the r
esulting circuit it obtained in terms of various data
structures.
Let’s consider each of these 4 steps in detail in sections 3.1

3.4 below, starting with a
specification of the desired operation of a 1

bit adder.
3.1 Specification of Circuit Input/Outp
ut Behavior
Consider 1

bit adder circuit without a carry input called a
Half

Adder
. Based on the
truth table and Boolean equations of the relationship between its inputs and outputs, the
half

adder computes the binary sum of two bits. The half

adder ha
s two inputs
X
and
Y
with two outputs
Sum
and
Carry
as shown by the block diagram depicted in Figure 1.
The relationship between its inputs and outputs is specified in Table 1.
Table 1: Truth Table for Half

Adder
X
Y
Sum
Carry
0
0 0
0
0
1 1
0
0
1 1
0
1
1 0
1
Figure 1: Half

adder Block diagram
Thus, one possible design that might be obtained that is fully correct is:
Figure 2: Human

designed Half

adder
3.2 Selection of Hardware Platform for which the Design is Evolved
The hardware device being evolved is a simple FGPA archite
cture. This FPGA has a
rectangular array of cells. Each cell has a programmable function. The possible
functions of each cell include the Boolean logic functions such as {AND, OR, XOR,
NAND, NOR}. The programmable cells in an FPGA are called
Look

up Ta
bles (LUTs).
Each LUT used here has 2 inputs and 1 output. These inputs and outputs are
programmable and can be routed to any of the other LUTs in the FPGA. As with
commercially

available FPGAs, the LUTs are organized into groups of cells to form a
Conf
igurable Logic Block (CLB)
. In this lab, there are 2 LUTs per CLB organized into a
1x2 array of CLBs on the FPGA. Thus, the circuit being evolved must be realized within
these available resources.
3.3 Evolution of the Hardware Design
X
Y
X
Carry
Sum
Half Adder
Y
X
Since steps 1 an
d 2 above are determined, let’s examine step 3 in more detail of how the
GA operates to evolve a hardware design. You will be provided with a program that
performs the following steps, and will be asked to compile and execute it. The GA
procedure perform
ed is as follows:
GA_Procedure ()
{
Initialize the Population_of_Chromosomes;
Calculate the Fitness_Function;
While (Fitness_Value != Optimal_Value)
{
Perform Selection;
Perform Crossover;
Perfom Mutation;
Calculate the Fitness_Function;
}
Out
put the Circuit_Design having the Optimal_Value;
}
Initialization
The procedure begins with the initialization of the chromosomes in the population. In
EHW, a
chromosome
is a data structure used to represent the important characteristics of
a digital har
dware design such as the logic gates used and their input/output connections.
One chromosome is instantiated for each individual in the population. The GA can
evaluate the
fitness,
or relative suitability, of an individual by interpreting the fields
comp
rise that individual’s chromosome. Thus each instantiation of a chromosome
represents a possible solution to the problem. In other words, the chromosome encodes
the design of a specific digital circuit. In this lab, the
representation
to encode the
chro
mosome is a binary string with fields indicating the type of logic gate functions
(AND, OR, , NOR, NAND, XOR, etc.) being used and also the interconnections between
these gates. Examples will be provided below.
During the initialization step, the initial
population of chromosomes is created by
choosing random numbers to occupy the contents of the fields in each individual’s
chromosome. This creates the initial generation of the population of designs to be
considered. Although a random initial population
is used in this lab, an alternative used
in other applications is to seed the initial population with some human

engineered
designs.
Calculation of fitness function
An evaluation mechanism for the assessing the suitability of each individual design in th
e
population is utilized called a
fitness function
. A fitness function computes how well a
particular design performs in terms of some specific metrics. In general, those
chromosomes with higher fitness values are interpreted to be better solutions to t
he
problem than those with lower fitness scores. In this laboratory, there fitness of a design
is equal to the number of correct values that the circuit computes. In this case, the
maximum fitness is 8 because there are 4 input pairs and each must genera
te a Sum and a
Carry output correctly.
Selection
The
selection
process chooses individuals from the current generation based on their
fitness. A number of different selection methods are available depending on the objective
and technique used. During th
is process
elitism
may be employed. Elitism retains the
best few individuals in the current generation unchanged for the next generation. This
prevents loss of the yet

best

found solution as evolution progresses.
Crossover
Crossover
is a genetic operato
r that selects subparts from two parent chromosomes and
creates a new offspring chromosome that has characteristics of each. For instance,
chromosomes of two parents can be split into two halves. The halves are interchanged
and combined to form the child
chromosome to be included in the next generation as
follows:
Chromosomes before crossover:
Parent1
100110  0100
Parent2
011001  0110
Chromosomes after crossover:
Offspring1
100110  0110
Offspring2
011001  0100
Mutation
When searching through t
he range of possible designs, it can be useful to also consider
new possibilities that are not necessary represented in the current population. Thus after
crossover is performed, certain bits in the chromosome may be randomly inverted using
mutation
. Thes
e are shown in bold typeface below:
Chromosomes before mutation:
Offspring1
1001
1
0  0110
Offspring2
01100
1
 0100
Chromosomes after mutation:
Offspring1
1001
0
0  0110
Offspring2
01100
0
 0100
Summary of GA Algorithm Procedure
The GA repeats the a
bove steps in order to create iteratively better designs. This can be
continued until a fully correct circuit is obtained. In this lab, the code to perform the
above will be provided to you so you can observe the output as the circuit evolves. The
progr
am is already configured to evolve the desired circuit and you should compile and
execute it as described in the Laboratory Procedure section below.
3.4 Interpretation of the Resulting Design
Once a sufficiently correct hardware design has been evolved,
the resulting circuit can be
employed. In this lab, we seek to understand the data structures that are used to represent
these circuits. Consider an array of 2 CLBs where each CLB contains 2 independent
LUTs show in Figure 3.
Figure 3.
.
In Figure 3,
there a total of 8 outputs labeled
0

7
inclusive. The outputs
0
and
1
correspond to the input X and input Y, respectively, of the adder. The numbers
2 3 4 5
are the outputs for each of the LUTs in CLB0 and CLB1 respectively. The functions of
each LUT de
noted by
{AND. OR, NOR, XOR, NAND}
and each cell’s two inputs denoted
by
A
and
B,
respectively.
For example, given the labeling above then the design output by the GA is in the form of:
CLB 0 LUT 0
inputs: 1 0
function: XOR
CLB 0 LUT 1
inputs: 0 1
function: AND
CLB 1 LUT 0
inputs: 3 2
function: OR
CLB0
CLB1
CLB 1 LUT 1
inputs: 3 3
function: AND
FPGA 0 output
inputs: 3 2
This means CLB 0 contains LUT 0 which has its input A and its input B both connected
to ‘1 0’ which means input 0 in Figure 3. In
put 1 in Figure 3 denotes external input Y to
de the adder and input 0 in Figure 3 denotes external input X to the adder. In this LUT,
the cell function is set to XOR, which corresponds to A XOR B. In similar way LUT 1 in
CLB 0 has input connected to ‘0
1’, where the cell function is set to AND, which
corresponds to A AND B. Meanwhile, LUT 0 in CLB 1 has inputs connected to ‘3 2’
where the cell function is set to OR, which corresponds to A OR B. The ‘3’ designates
the output reference 3, and ‘2’ designa
tes the output reference 2. Finally, LUT 1 in CLB
1 has input connected to ‘3 3’, where the cell function is set to AND, which is A AND B.
The output of the FPGA is designated by ‘3 2’ which correspond to CLB 0 LUT 0 and
CLB 0 LUT 1, respectively
4. Da
ta Structures for Representing Circuits and Graphs
It is very common programming requirement in many applications to need to represent
arbitrary graphs or circuits. One such circuit or graph would be the connections between
LUTs as listed in the previous
example. In this section we will define some data
structures used to represent graphs and circuits. Some definitions from graph theory used
to identify these techniques are listed below:
A graph
consists of a set of vertices,
, and edges,
. An edge is a pair
where
.
A vertex
is adjacent to
iff
.
A path
in a graph is a s
equence of vertices
such that
for
Consider some data structures that might be used to represent the graph shown in Figure
4 as discussed below.
Figure 4: Sample graph for data str
ucture representation
4.1 Adjacency Matrix data structure
An
Adjacency Matrix
uses a 2

dimensional array to specify the
topology,
or layout, of a
directed graph. For each edge
in the graph, set A
equal to 1.
This
representation consumes a lot of space unnecessarily if the graph is not dense. The space
complexity is of order
. For example, the Adjacency matrix representation for
Figure 4 is shown in Figure 5.
Figure 5: Adjacency Matrix
4.2 Adjacency List data structure
The
Adjacency List
data structure utilizes an array of linked lists for each vertex. The list
has the destination vertex numbers for which there exist an edge emanating from that
source
vertex. By using this data structure we can find the vertices that are adjacent to a
particular vertex quickly but must maintain the linked list structure whenever the graph is
modified. The Adjacency list representation for Figure 4 is shown in Figure 6.
Figure 6: Adjacency List
5. Laboratory Procedure
Circuits will be evolved for the configurable logic device architecture using the code
provided based on Section 3. The student will then interpret and compare the resulting
data structures corr
esponding to these circuits based on Section 4.
5.1 Compile and Execute the Code
For this assignment you will be provided a fully operational C++ code for EHW to
evolve the circuit as specified in Section 3. The source code contains 5 files. All of them
must be included when building the executable as follows:
./ecFPGA.cpp

This is the main file.
./types.h

This is where the classes and structures are defined.
./functions.cpp

This is where the test functions are defined.
./FPGAfunction
s.cpp

This is where the FPGA specific functions are defined.
./GAfunctions.cpp

This is where the GA functions are defined.
The code includes the following input text files:
./FPGA_test_params.txt

First file called and is hard coded to be in
the same path
as the executable.
./FPGA_test_graph_fitness.txt
./FPGA_Specification.txt
./One_Bit_Adder_Test.txt
./GA_params.txt
11
/**random number seed**/
./FPGA_Specification.txt

This is the FPGA design specification
FPGA configuration for one

bit functions
2 /*number of inputs to FPGA !must match type of function! */
2 /*number of outputs from FPGA !must match type of function! */
2 /*number of Configurable Logic Blocks */
2 /*number of
Look up tables (LUTs) per CLB*/
2 /*number of LUT select lines */
./One_Bit_Adder_Test.txt

Location of the desired I/O pairs used for comparison
4 /*Number of test pairs */
/ *Input Output Test Sequence*/
/*Input A B and D
esired Output1 Output2*/
0 0
0
0
0 1
0
1
1 0
0
1
1 1
1
0
./GA_params.txt

Location of the parameters for the Genetic Algorithm
/*Simple GA parameters.
/*This file provides the parameters used by the Sim
ple Genetic Algorithm.*/
/*It includes the following parameters:*/
40 /*population size*/
40 /*offspring population size*/
0.01 /*mutation rate*/
100 /*number of generations*/
3.) The program creates two output files:
./FPGA_output.tx
t

The primary location for output from the project
./FPGA_test_graph_fitness.txt

Location for an easy to graph fitness output
The hard coded path
./FPGA_test_params.txt
must be in the same location as
executable.
Place the executable in any direc
tory along to four input text files and execute. For
instance, this program with the parameters for 1

bit adder evolved a complete solution for
the circuit at generation 16 in less than 15 seconds wall clock time on a Pentium at 2.0
GHz.
5.2 Observe Pro
gram Outputs and Draw FPGA Cell Diagrams
Examine the files created by the program for generations 1, 15, <best_fitness>. For
example, FPGA15 corresponds to the design at generation 15. Refer to section 3.4 for a
description of the program output and its
meaning.
For your execution output please list (or cut and paste into your lab report) the output
designs generated at generations 1, 15, and <best fitness> from the file FPGA_output.
Manually draw the three FPGA Cell Layout diagrams similar to Figure
3 corresponding
to the designs at generations 1, 15, and <best fitness>.
5.3 Compose Adjacency Matrices
Using the FPGA Cell Layout diagram you produced in Section 5.2, manually compose
the adjacency matrix data structure that would correspond to the
connectivity in the
circuit at generation 1.
5.4 Compose Adjacency Lists
Using the FPGA Cell Layout diagram you produced in the Section 5.2, manually
compose the adjacency list data structure that would correspond to the connectivity in the
circuit at
generation 15.
5.5 Compose Logic Diagram
Using the FPGA Cell Layout diagram you produced in Section 5.2, manually draw the
resulting circuit at <best_fitness> generation using Boolean AND, OR, NOR, NAND,
XOR gates accordingly.
5.6
Verify Correct Circ
uit Function
Using the circuit produced in Section 5.4, verify the truth table produced by your circuit
matches the correct output for all inputs as listed in Table 2. Explain your work and
verification results.
6.0 Sample Results
6.1 Compile and Execu
te the Code
The code was compiled and executed to generate the design shown in Figure 3. Refer to
section 3.4 for details of the output and resulting FPGA design.
6.2 Observe Program Outputs and Draw FPGA Cell Diagrams
The sample FPGA Cell Diagram is a
lready shown in Figure 3. Note that for the design
defined in Figure 3, we can draw its graph representation as follows:
Figure 7
6.3 Example Adjacency Matrix
By using the data of the output defined in figure 4 we can draw its Adjacency Mat
rix
representation as follows:
Figure 8
6.4 Example Adjacency List Representation
By using the data of the output defined in figure 4 we can draw its Adjacency List
representation as follows:
Figure 9
6.5
Example Logic Diagram
The logic from Figure 3 is shown as follows:
Figure 10
4
7
X Y
6
Sum
Carry
3
2
0 1
5
7.0 Report format and Grading
7.1 Items to be Submitted
Submit a complete report with each item listed in Section 5. Include a brief introduction
and co
nclusion. In your conclusion, comment briefly on the relative advantages and
disadvantages of the various circuit/graph representation methods covered in this lab.
7.2 Grading Policy
Drawing of FPGA Cell Diagrams
15%
Providing Correct Adjacency Matr
ices
20%
Providing Correct Adjacency Lists
20%
Providing Correct <Best_Fitness> Boolean Logic Circuit diagram
15%
Verification of Correct Circuit Function
15%
Report write

up and comments on your observations
15 %
The assignment must be handed
in due date for the full 100% grade. Late assignments
will be downgraded by 50%.
Bibliography
1.
[Miller, J.F., Thompson, P., Fogary, T., 1997} Designing Electronic Circuits
Using Evolutionary Algorithms. Arithmetic Circuits: Case Study, John Willey &
Sons
Ltd. 1997.
2.
[Miller, J., Thompson, P., ] Aspects of Digital Evolutions: Evolvability and
Architecture, Departmentof Computing, Napier University, 219 Colington Road,
Edinburgh, EH14 1DJ, UK.
3.
[Housell, B., Arslan, T, ], A Novel Genetic Algorithms for the Au
tomated Design
of Performance Driven Digital Circuits, Department of Electronics and Electrical
Engineering The University of Edinburgh
4.
[Poli, R., Langdon, W.], Sub

machine

code Genetic Programming. Chapter 13
5.
[Joglekar, A., Tungare,M., ], Genetic Algorith
ms and their use in the design of
Evolvable Hardware. Fr. Conceicao Rodrigues College of Engineering Badra
Mumbai
–
400 050
6.
[Singleton, A. 1994], Genetic Programming with C++,BYTE Articles.
7.
Genetic Algorithms,
http://www.cis.upenn.edu/~hollick/genetic /node2.html
8.
Reinforcement Learning: An Introduction Richard S. Sutton and Andrew G.
Barto. MIT Press, Cambridge, MA, 1998
Assessment and Evaluation Form
Purpose
:
This lab provides hands

on experience with some data structures commonly used to
represent graphs or circuits in C++ programs. Rather than using hypothetical examples,
these data structures used will be employed in the context of a machine learning
application. Specifically, c
ircuits will be evolved for a configurable logic device
architecture using the code provided. The student will then interpret and compare the
resulting data structures corresponding to these circuits.
Learner Outcomes
:
1.
Introduce basic concepts of Evolva
ble Hardware: 4 step EHW process, FPGA LUT
and CLBs, functionality of Half

Adder circuit
2.
Understand basic concepts of Genetic Algorithms: GA procedure, fitness function
3.
Understand how to build the adjacency matrix and adjacency list representations
4.
Be abl
e to interpret the output of an EHW technique and see the design change and
improve over time as evolution progresses.
Mark One box for each question
How hard did you
find the homework
Very Hard
Hard
Normal
Easy
Very Easy
Comments:
Di
d you enjoy doing
the homework
A lot
Yes
A bit
No
Not at all
Comments
Was the assignment
useful to exercise for
learning data
structures for graphs
Very Useful
Useful
A bit
Useful
Not
Useful
No, it was
detrimental
Comments:
On a scale of 1 to 5.
5 meaning a lot, 1 not
5
4
3
2
1
at all, how much do
you think the
homework related you
to machine learning
Comments:
Would you be
interested in knowing
more about machine
learning
Very
Interested
Intereste
d
Just
curious
Not
interested
Comments:
Evaluation, related to Learner Outcomes
:
1.
Did you understand the concepts related to Evolvable Hardware? If you found it
difficult to acquire this concept what was the reason? Please explain.
2.
Di
d you understand the concepts related to Genetic Algorithms? If you found it
difficult to acquire this concept what was the reason? Please explain.
3.
Did you understand the concepts of Adjacency Matrix and Adjacency Lists? If you
found it difficult to acquir
e this concept what was the reason? Please explain
4.
Were you able to interpret the output design of an EHW technique and see the design
change and improve over time as evolution progresses?
Demographics:
Level: Sophomore []Junior [] Senior []
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