VLSI VLSI Design Design Methodology Methodology

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Nov 26, 2013 (3 years and 8 months ago)

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HCMC University of Technology 「VLSI Design Methodology 」
VLSI
VLSI
Design
Design
Methodology
Methodology
Dr. DINH-DUC Anh-Vu
http://www.dit.hcmut.edu.vn/~anhvu/VLSI DM
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HCMC University of Technology 「VLSI Design Methodology 」
Outline
14.
14.
Appendix
Appendix
7.
7.
Logic synthesis
Logic synthesis
13.
13.
Intellectual Property (IP)
Intellectual Property (IP)
6.
6.
Functional verification
Functional verification
12.
12.
Design for test
Design for test
5.
5.
HDL
HDL
11.
11.
Signal integrity
Signal integrity
4.
4.
Critical issues in VLSI design
Critical issues in VLSI design
10.
10.
Layout
Layout
3.
3.
Cutting edge design flow
Cutting edge design flow
9.
9.
Low power design
Low power design
2.
2.
LSI Device
LSI Device
8.
8.
Delay and timing verification
Delay and timing verification
1.
1.
Introduction
Introduction
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HCMC University of Technology 「VLSI Design Methodology 」
Silicon Lattice

Transistors are built on a silicon substrate

Silicon is a Group IV material

Forms crystal lattice with bonds to four neighbors
Si SiSi
Si SiSi
Si SiSi
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HCMC University of Technology 「VLSI Design Methodology 」
Dopants

Silicon is a semiconductor

Pure silicon has no free carriers and conducts poorly

Adding dopants increases the conductivity

Group V: extra electron (n-type)

Group III: missing electron, called hole (p-type)
As SiSi
Si SiSi
Si SiSi
B SiSi
Si SiSi
Si SiSi
-
+
+
-
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HCMC University of Technology 「VLSI Design Methodology 」
p-n Junctions

A junction between p-type and n-type
semiconductor forms a diode.

Current flows only in one direction
p-type n-type
anode
cathode
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HCMC University of Technology 「VLSI Design Methodology 」
nMOS Transistor

Four terminals: gate, source, drain, body

Gate – oxide – body stack looks like a capacitor

Gate and body are conductors

SiO
2
(oxide) is a very good insulator

Called metal – oxide – semiconductor (MOS) capacitor

Even though gate is
no longer made of metal
n+
p
GateSource Drain
bulk Si
SiO
2
Polysilicon
n+
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HCMC University of Technology 「VLSI Design Methodology 」
n+
p
GateSource Drain
bulk Si
SiO
2
Polysilicon
n+
D
0
S
nMOS Operation

Body is commonly tied to ground (0 V)

When the gate is at a low voltage:

P-type body is at low voltage

Source-body and drain-body diodes are OFF

No current flows, transistor is OFF
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HCMC University of Technology 「VLSI Design Methodology 」
nMOS Operation Cont.

When the gate is at a high voltage:

Positive charge on gate of MOS capacitor

Negative charge attracted to body

Inverts a channel under gate to n-type

Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
n+
p
GateSource Drain
bulk Si
SiO
2
Polysilicon
n+
D
1
S
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HCMC University of Technology 「VLSI Design Methodology 」
pMOS Transistor

Similar, but doping and voltages reversed

Body tied to high voltage (V
DD
)

Gate low: transistor ON

Gate high: transistor OFF

Bubble indicates inverted behavior
SiO
2
n
GateSource Drain
bulk Si
Polysilicon
p+
p+
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HCMC University of Technology 「VLSI Design Methodology 」
Power Supply Voltage

GND = 0 V

In 1980’s, V
DD
= 5V

V
DD
has decreased in modern processes

High V
DD
would damage modern tiny transistors

Lower V
DD
saves power

V
DD
= 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
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HCMC University of Technology 「VLSI Design Methodology 」
Transistors as Switches

We can view MOS transistors as electrically
controlled switches

Voltage at gate controls path from source to
drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF
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HCMC University of Technology 「VLSI Design Methodology 」
Complementary MOS

Complementary MOS logic gates

nMOS pull-down network

pMOS pull-up network

a.k.a. static CMOS
pMOS
pull-up
network
output
inputs
nMOS
pull-down
network
X (crowbar)0Pull-down ON
1Z (float)Pull-down OFF
Pull-up ONPull-up OFF
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HCMC University of Technology 「VLSI Design Methodology 」
Series and Parallel

nMOS: 1 = ON

pMOS: 0 = ON

Series: both must be ON

Parallel: either can be ON
(a)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
OFF OFF OFF ON
(b)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
ON OFF OFF OFF
(c)
a
b
a
b
g1 g2
0
0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b
1
a
b
1
1 0 1
a
b
0
0
a
b
0
a
b
1
a
b
1
1 0 1
a
b
g1 g2
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HCMC University of Technology 「VLSI Design Methodology 」

Complementary MOS gates always produce 0 or 1

Ex: NAND gate

Series nMOS: Y=0 when both inputs are 1

Thus Y=1 when either input is 0

Requires parallel pMOS

Rule of Conduction Complements

Pull-up network is complement of pull-down

Parallel → series, series → parallel
Conduction Complement
A
B
Y
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HCMC University of Technology 「VLSI Design Methodology 」
CMOS I nverter
1
0
YA
V
DD
A Y
GND
A Y
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HCMC University of Technology 「VLSI Design Methodology 」
CMOS I nverter
01
0
YA
V
DD
A=1 Y=0
GND
ON
OFF
A Y
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HCMC University of Technology 「VLSI Design Methodology 」
CMOS I nverter
01
10
YA
V
DD
A=0 Y=1
GND
OFF
ON
A Y
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HCMC University of Technology 「VLSI Design Methodology 」
CMOS NAND Gate
1
1
0
0
A
1
0
1
0
YB
A
B
Y
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HCMC University of Technology 「VLSI Design Methodology 」
CMOS NAND Gate
1
1
0
0
A
1
0
1
10
YB
A=0
B=0
Y=1
OFF
ON
ON
OFF
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HCMC University of Technology 「VLSI Design Methodology 」
CMOS NAND Gate
1
1
0
0
A
11
0
1
10
YB
A=0
B=1
Y=1
OFF
OFF
ON
ON
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HCMC University of Technology 「VLSI Design Methodology 」
CMOS NAND Gate
1
1
0
0
A
11
10
1
10
YB
A=1
B=0
Y=1
ON
ON
OFF
OFF
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HCMC University of Technology 「VLSI Design Methodology 」
CMOS NAND Gate
1
1
0
0
A
11
10
01
10
YB
A=1
B=1
Y=0
ON
OFF
OFF
ON
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HCMC University of Technology 「VLSI Design Methodology 」
CMOS NOR Gate
1
1
0
0
A
01
00
01
10
YB
A
B
Y
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HCMC University of Technology 「VLSI Design Methodology 」
3-input NAND Gate

Y pulls low if ALL inputs are 1

Y pulls high if ANY input is 0
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HCMC University of Technology 「VLSI Design Methodology 」
3-input NAND Gate

Y pulls low if ALL inputs are 1

Y pulls high if ANY input is 0
A
B
Y
C
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HCMC University of Technology 「VLSI Design Methodology 」
CMOS Gate Design

Activity:

Sketch a 4-input CMOS NOR gate
A
B
C
D
Y
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HCMC University of Technology 「VLSI Design Methodology 」
CMOS Gate Design

Activity:

Sketch a 4-input CMOS NAND gate
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HCMC University of Technology 「VLSI Design Methodology 」
Compound Gates

Compound gates can do any inverting function
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HCMC University of Technology 「VLSI Design Methodology 」
Compound Gates

Step to construct single-stage combinational CMOS logic cell
1.
Draw a schematic icon with an inversion (bubble) on the last cell (the
bubble-out schematic). Use de Morgan’s theorems —“A NAND is an
OR with inverted inputs and a NOR is an AND with inverted inputs”—
to push the output bubble back to the inputs (this the dual icon or
bubble-in schematic).
2.
Form the n -channel stack working from the inputs on the bubble-out
schematic: OR translates to a parallel connection, AND translates to a
series connection. If you have a bubble at an input, you need an
inverter.
3.
Form the p -channel stack using the bubble-in schematic (ignore the
inversions at the inputs—the bubbles on the gate terminals of the p -
channel transistors take care of these). If you do not have a bubble at
the input gate terminals, you need an inverter (these will be the same
input gate terminals that had bubbles in the bubble-out schematic).
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HCMC University of Technology 「VLSI Design Methodology 」
Compound Gates
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HCMC University of Technology 「VLSI Design Methodology 」
Example: AOI 22

(AND-AND-OR-INVERT, AOI22)Y A B C D= +i i
A
B
C
D
A
B
C
D
A B
C D
A B
C D
B
D
Y
A
C
A
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
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HCMC University of Technology 「VLSI Design Methodology 」
Example: O3AI

( )
Y A B C D= + + i
A B
Y
C
D
DC
B
A
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HCMC University of Technology 「VLSI Design Methodology 」
Signal Strength

Strength of signal

How close it approximates ideal voltage source

V
DD
and GND rails are strongest 1 and 0

nMOS pass strong 0

But degraded or weak 1

pMOS pass strong 1

But degraded or weak 0

Thus nMOS are best for pull-down network
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HCMC University of Technology 「VLSI Design Methodology 」
Pass Transistors

Transistors can be used as switches
g
s d
g
s d
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HCMC University of Technology 「VLSI Design Methodology 」
Pass Transistors

Transistors can be used as switches
g
s d
g = 0
s d
g = 1
s d
0 strong 0
Input Output
1 degraded 1
g
s d
g = 0
s d
g = 1
s d
0 degraded 0
Input Output
strong 1
g = 1
g = 1
g = 0
g = 0
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HCMC University of Technology 「VLSI Design Methodology 」
Transmission Gates

Single pass transistors produce degraded
outputs
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HCMC University of Technology 「VLSI Design Methodology 」
Transmission Gates

Single pass transistors produce degraded
outputs

Complementary Transmission gates pass both
0 and 1 well
g = 0, gb = 1
a b
g = 1, gb = 0
a b
0 strong 0
Input
Output
1
strong 1
g
gb
a
b
a b
g
gb
a b
g
gb
a b
g
gb
g = 1, gb = 0
g = 1, gb = 0
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HCMC University of Technology 「VLSI Design Methodology 」
Tristates

Tristate buffer produces Z when not enabled
11
01
10
00
YAEN
A
Y
EN
A
Y
EN
EN
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HCMC University of Technology 「VLSI Design Methodology 」
Tristates

Tristate buffer produces Z when not enabled
111
001
Z10
Z00
YAEN
A
Y
EN
A
Y
EN
EN
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HCMC University of Technology 「VLSI Design Methodology 」
Nonrestoring Tristate

Transmission gate acts as tristate buffer

Only two transistors

But nonrestoring

Noise on A is passed on to Y
A Y
EN
EN
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HCMC University of Technology 「VLSI Design Methodology 」
Tristate I nverter

Tristate inverter produces restored output

Violates conduction complement rule

Because we want a Z output
A
Y
EN
EN
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HCMC University of Technology 「VLSI Design Methodology 」
Tristate I nverter

Tristate inverter produces restored output

Violates conduction complement rule

Because we want a Z output
A
Y
EN
A
Y
EN = 0
Y = 'Z'
Y
EN = 1
Y = A
A
EN
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HCMC University of Technology 「VLSI Design Methodology 」
Multiplexers

2:1 multiplexer chooses between two inputs
X11
X01
1X0
0X0
YD0D1S
0
1
S
D0
D1
Y
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HCMC University of Technology 「VLSI Design Methodology 」
Multiplexers

2:1 multiplexer chooses between two inputs
1X11
0X01
11X0
00X0
YD0D1S
0
1
S
D0
D1
Y
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HCMC University of Technology 「VLSI Design Methodology 」
Gate-Level Mux Design


How many transistors are needed?
1 0
(too many transistors)Y SD SD= +
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HCMC University of Technology 「VLSI Design Methodology 」
Gate-Level Mux Design


How many transistors are needed? 20
1 0
(too many transistors)Y SD SD= +
4
4
D1
D0
S
Y
4
2
2
2
Y
2
D1
D0
S
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HCMC University of Technology 「VLSI Design Methodology 」
Transmission Gate Mux

Nonrestoring mux uses two transmission gates
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HCMC University of Technology 「VLSI Design Methodology 」
Transmission Gate Mux

Nonrestoring mux uses two transmission gates

Only 4 transistors
S
S
D0
D1
Y
S
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HCMC University of Technology 「VLSI Design Methodology 」
I nverting Mux

Inverting multiplexer

Use compound AOI22

Or pair of tristate inverters

Essentially the same thing

Noninverting multiplexer adds an inverter
S
D0
D1
Y
S
D0
D1
Y
0
1
S
Y
D0
D1
S
S
S
S
S
S
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HCMC University of Technology 「VLSI Design Methodology 」
CMOS Fabrication

CMOS transistors are fabricated on silicon
wafer

Lithography process similar to printing press

On each step, different materials are deposited
or etched

Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process
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HCMC University of Technology 「VLSI Design Methodology 」
I nverter Cross-section

Typically use p-type substrate for nMOS
transistors

Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+
p+
SiO
2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
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HCMC University of Technology 「VLSI Design Methodology 」
Well and Substrate Taps

Substrate must be tied to GND and n-well to V
DD

Metal to lightly-doped semiconductor forms poor
connection (used for Schottky Diode)

Use heavily doped well and substrate contacts / taps
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+p+
substrate tap
well tap
n+ p+
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HCMC University of Technology 「VLSI Design Methodology 」
I nverter Mask Set

Transistors and wires are defined by masks

Cross-section taken along dashed line
GND V
DD
Y
A
substrate tap
well tap
nMOS transistor
pMOS transistor
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HCMC University of Technology 「VLSI Design Methodology 」
Detailed Mask Views

Six masks

n-well

Polysilicon

n+ diffusion

p+ diffusion

Contact

Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
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HCMC University of Technology 「VLSI Design Methodology 」
Fabrication Steps

Start with blank wafer

Build inverter from the bottom up

First step will be to form the n-well

Cover wafer with protective layer of SiO
2
(oxide)

Remove layer where n-well should be built

Implant or diffuse n dopants into exposed wafer

Strip off SiO
2
p substrate
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HCMC University of Technology 「VLSI Design Methodology 」
Oxidation

Grow SiO
2
on top of Si wafer

900 – 1200 C with H
2
O or O
2
in oxidation furnace
p substrate
SiO
2
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HCMC University of Technology 「VLSI Design Methodology 」
Photoresist

Spin on photoresist

Photoresist is a light-sensitive organic polymer

Softens where exposed to light
p substrate
SiO
2
Photoresist
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HCMC University of Technology 「VLSI Design Methodology 」
Lithography

Expose photoresist through n-well mask

Strip off exposed photoresist
p substrate
SiO
2
Photoresist
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HCMC University of Technology 「VLSI Design Methodology 」
Etch

Etch oxide with hydrofluoric acid (HF)

Seeps through skin and eats bone; nasty stuff!!!

Only attacks oxide where resist has been
exposed
p substrate
SiO
2
Photoresist
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HCMC University of Technology 「VLSI Design Methodology 」
Strip Photoresist

Strip off remaining photoresist

Use mixture of acids called piranah etch

Necessary so resist doesn’t melt in next step
p substrate
SiO
2
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HCMC University of Technology 「VLSI Design Methodology 」
n-well

n-well is formed with diffusion or ion implantation

Diffusion

Place wafer in furnace with arsenic gas

Heat until As atoms diffuse into exposed Si

Ion Implanatation

Blast wafer with beam of As ions

Ions blocked by SiO
2
, only enter exposed Si
n well
SiO
2
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HCMC University of Technology 「VLSI Design Methodology 」
Strip Oxide

Strip off the remaining oxide using HF

Back to bare wafer with n-well

Subsequent steps involve similar series of
steps
p substrate
n well
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HCMC University of Technology 「VLSI Design Methodology 」
Polysilicon

Deposit very thin layer of gate oxide

< 20 Å (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of silicon
layer

Place wafer in furnace with Silane gas (SiH
4
)

Forms many small crystals called polysilicon

Heavily doped to be good conductor
Thin gate oxide
Polysilicon
p substrate
n well
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HCMC University of Technology 「VLSI Design Methodology 」
Polysilicon Patterning

Use same lithography process to pattern
polysilicon
Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well
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HCMC University of Technology 「VLSI Design Methodology 」
N-diffusion

Use oxide and masking to expose where n+
dopants should be diffused or implanted

N-diffusion forms nMOS source, drain, and n-
well contact
p substrate
n well
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HCMC University of Technology 「VLSI Design Methodology 」
N-diffusion (cont.)

Pattern oxide and form n+ regions
p substrate
n well
n+ Diffusion
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HCMC University of Technology 「VLSI Design Methodology 」
N-diffusion (cont.)

Historically dopants were diffused

Usually ion implantation today

But regions are still called diffusion
n well
p substrate
n+n+
n+
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HCMC University of Technology 「VLSI Design Methodology 」
N-diffusion (cont.)

Strip off oxide to complete patterning step
n well
p substrate
n+n+
n+
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HCMC University of Technology 「VLSI Design Methodology 」
P-Diffusion

Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate
contact
p+ Diffusion
p substrate
n well
n+n+
n+
p+p+p+
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HCMC University of Technology 「VLSI Design Methodology 」
Contacts

Now we need to wire together the devices

Cover chip with thick field oxide

Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+n+
n+
p+p+p+
Contact
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HCMC University of Technology 「VLSI Design Methodology 」
Metalization

Sputter on aluminum over whole wafer

Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+n+
n+
p+p+p+
Met al
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HCMC University of Technology 「VLSI Design Methodology 」
Layout

Chips are specified with set of masks

Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)

Feature size f = distance between source and drain

Set by minimum width of polysilicon

Feature size improves 30% every 3 years or so

Normalize for feature size when describing design
rules

Express rules in terms of λ = f/2

E.g. λ = 0.3 µm in 0.6 µm process
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HCMC University of Technology 「VLSI Design Methodology 」
Simplified Design Rules

Conservative rules to get you started
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HCMC University of Technology 「VLSI Design Methodology 」
I nverter Layout

Transistor dimensions specified as Width / Length

Minimum size is 4λ/ 2λ, sometimes called 1 unit

In f = 0.6 µm process, this is 1.2 µm wide, 0.6 µm long
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HCMC University of Technology 「VLSI Design Methodology 」
Summary

MOS Transistors are stack of gate, oxide, silicon

Can be viewed as electrically controlled switches

Build logic gates out of switches

Draw masks to specify layout of transistors

Now you know everything necessary to start
designing schematics and layout for a simple chip!