VLSI Packaging Technique Using Liquid-Cooled Channels

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ISEE TRANSACTIONS 0N COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. CHMT-9, NO. 4, DECEMBER 1986
VLSI Packaging Technique Using Liquid-Cooled
Channels
TOHRU IUSHIMOTO
AND
TAKAAKI OHSAKI
Abstract-A new packaging technique which employs innovative
indirect liquid cooling is described. The technique involves mounting very
large-scale integrated (VLSI) chips on a multilayered alumina substrate
which incorporates very fine coolant channels. In particular, an investiga-
tion into the optimal structure for the cooling section by computer
simulation and by experiment involving the physical implementation of
this structure is discussed. The numerical solution of the coolant flow
distribution obtained ensures that the coolant distributor and collector
structure dimensions can be determined to meet the uniform velocity
distribution condition. Additionally, the channel cross section is designed
to be 800 pm wide
x
400 pm high to achieve a lower thermal resistance.
An outline of an indirect liquid cooling package fabricated based on the
results of these structures is presented. The package mounts a 5 x 5 array
of 8-mm* VLSI chips on a substrate measuring 85 mm x 105 mm. The
substrate features 29 very fine coolant channels, six conductor layers, and
900 input/output (I/O) pins. The technique permits the realization of an
allowable heat dissipation higher than 400 W per package at a flow rate of
1.0 I/min. Furthermore, since the thickness of the cooling section is
smaller than 1.0 mm, the volume power density increases 17 kW/I or
more. This cooling capability is tenfold greater than that obtained by
conventional indirect water cooling.
C
ONTINUAL ADVANCES in the speed and integration
scale of the integrated circuits used in high-performance
systems have created even greater demands for higher density
packaging to ensure reduced wiring delay for improved
electrical performance. In high-performance electronic equip-
ment,
effectively removing the considerable. amount of heat
generated is important for increasing the circuit speed and
ensuring the high reliability of an electronic circuit.
At present, most of the high-performance systems use
forced air convection cooling or indirect liquid cooling, of
which the latter promises higher power dissipation and more
compact packaging. Recently, the use of indirect water
cooling for the central processing unit of a high-performance
computer system has been reported [ 11, [2].
Although quite suitable for two-dimensional packaging,
conventional liquid cooling systems are not well suited to
three-dimensional or high-density stack packaging. This is
because
the application of these systems results in complicated
and bulky modules as well as inevitably increasing the
interconnection length for high-density stack packaging.
Therefore, it is essential to develop a liquid-cooled package
Manuscript received March 22, 1986; revised July 14, 1986. This paper
was presented at the 36th Electronic Components’Conference, Seattle, WA,
May 5-7, 1986.
The authors are with the Electrical Communications Laboratories, Nippon
Telegraph and Telephone Corporation, 3-9-l 1, Midoricho, Mnsashimo-shi,
Tokyo 180, Japan.
IEEE Log Number 8611125.
having a higher cooling capability and a better suited high-
density stacked package.
In line with this, the present paper describes a new
packaging technology which employs innovative indirect
liquid cooling. The technique involves the mounting of very
large-scale integrated (VLSI) chips on a multilayered alumina
substrate which incorporates very ’ fine coolant channels
comprising a cross section of less than 1 mm*. This paper
first describes the design procedure for the innovative liquid
cooling technique, that is, the fabrication of very small cross-
section channels which achieve lower thermal resistance. It
also discusses the design for the coolant distributor and
collector structure which work together to realize a uniform
liquid flow distribution. It then takes a look at the actual
fabrication process for the newly proposed package. Finally, it
presents an evaluation of cooling capability for the fabricated
package based on experimental and numerical methods.
STRUCTURE
Fig. l(a) shows the cross-sectional arrangement of the
newly proposed indirect liquid cooling package, and Fig. l(b)
illustrates the high-density stacked system conception. Very
fine coolant channels having a cross section of less than 1 mm2
were formed into the lower portion and between the buried
via-holes of a multilayered alumina substrate. Interconnection
pads were fabricated on the front and rear surfaces of the
substrate to permit connection of the substrate to the wiring
boards which were located on three sides of the package. The
coolant distributor and collector were formed in two opposite
edges of the multilayered alumina substrate. These were
fabricated using the same punching process as is employed in
via-hole formation.
In the cooling process itself the coolant is supplied from the
coolant inlet port and distributed to each coolant channel by
the coolant distributor, thereby ensuring a uniform velocity
profile. The heat generated in the chips is conducted to the
coolant channels by way of the alumina substrate, where it is
transferred to the liquid flow. The warmed coolant is
subsequently collected by the coolant collector after flowing
through the coolant channels. It then flows out through the
coolant outlet port. The upper and lower stack packages are
connected in series by piping.
This new cooling technique offers four principal structural
advantages. First, the cooling channels and the conductor
layer sections can be formed into a single substrate by the
same punching process as is used in via-hole formation.
Second, a high cooling capability is realized by fabricating
channels just inside the multilayer alumina substrate. Such a
0148641 l/86/1200-0328$01 .OO 0 1987 IEEE
KISHIMOTO AND OHSAKI: VLSI PACKAGING TECHNIQUE
329
Interconnection pad
Chip
/
iion
pad
Coolant distributor
(a)
Wiring board
l/O
onnector
(b)
Fig. 1.
(a) Schematic of new VLSI package using innovative indirect liquid
cooling technique. (b) High-density stack-packaged system.
structure affords a lower thermal resistance because of the
very short thermal path and the high heat transfer coefficient
obtained through miniturized coolant channels. Third, high-
density stack packaging can be realized because of the minimal
thickness of the cooling channels. Finally, when replacement
or inspection of VLSI chips is needed, performance tests can
be carried out under the same conditions as those, of an actual
operating system because the cooling section is formed within
the same substrate [3].
Using this innovative indirect liquid cooled package enables
the realization of an attractive cooling system. Furthermore,
such a package is suitable for high-density stack-packed
electronic equipment which uses a large number of high-power
dissipation chips.
DESIGN
Cooling capability depends on the thermofluid dynamic
characteristics of very fine coolant channels, as well as on
coolant distributor and collector structures. In this section, we
present the design procedure for the cooling section in which
the channel cross section was determined based on the decision
to attempt to achieve a substantially lower thermal resistance.
Additionally, the coolant distributor and collector structures
were determined to satisfy the condition of a uniform velocity
distribution for the liquid flow through the channels.
Channel Cross Section
To obtain the optimal channel cross se&ion, we evaluated
the thermal resistance
R,
as a function of channel height,
channel width, and pressure ‘drop along the cooling channel.
We define
R,
as a reciprocal of the product of the cooling
channel’s surface area S and the average heat transfer
coefficient
h,.
We evaluated the thermal resistance based on
the pressure drop because a marked increase is indicated under
the constant flow rate condition as the channel cross section
gets smaller. In general, conventional pumps are ineffective
for driving coolants through very narrow channels.
The average liquid velocity V, related to the pressure drop
ti from the inlet to the outlet channel, is given by Poiseuille’s
and Blasius’s formulas. Using V, the average heat transfer
coefficient can be derived from empirical equations (1) and (2)
below.
When the liquid flow is laminar, the average heat transfer
coefficient
h,
is written as [4]
h,=% pc [1.10+0.555 (PrRe g$)““]l (1)
where h is the liquid thermal conductivity,
d
is the equivalent
diameter of a channel defined as 2ZW/(Z + W) such that W
is the channel width and Z is the channel height, ‘E is the aspect
ratio defined as Z/W, Pr is the Prandtl number, Re is the
Reynolds number, and L. is the channel length. The expression
is valid for a Reynolds number of less,than 2300.
In the Re > 2300 region the flow is turbulent such that the
following relationship is written [5]:
Re”.*
h,=; 1.11 ~
[ 1
0.275
0 023 Re0.8Pr0.4.
(L/d)0.8 ’
(2)
The unit channel surface area S is written as
S=Z(W+Z)L.
(3)
Using (l)-(3), and neglecting the fin efficiency, the final form
of the thermal resistance per unit channel
R,
is expressed as
l/(h,S).
Fig. 2 shows the thermal resistance
R,
as a function of the
channel .width
W
when the channel height Z changes. In this
figure, taking conventional pump use into consideration, the
pressure drop AP is chosen to be 2000 Kgf/m2.
As can be seen, the channel width giving rise to the
maximum thermal resistance exists. In the region where the
channel width is less than the value which maximizes
R,,
the
thermal resistance decreases depending on the increase of the
average heat transfer coefficient. This is caused by the thermal
boundary layer becoming thinner. On the other hand, in the
region where the channel width is greater than the maximum
point of
R,,
the thermal resistance decreases depending on the
enlargement of the channel’s surface area and on the increase
of the heat transfer coefficient. This results from the increase
in the liquid flow rate. Furthermore, the thermal resistance is
lowered when the channel height increases because of the
enlarging channel surface area.
Since reducing the channel height is desirable for ensuring a
330
IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. CHMT-9, NO. 4, DECEMBER 1986
I
I I I
s
0
200 400 600 800 1000
Channel width,W(pm)
Fig. 2. External thermal resistance per unit channel as function of channel
width W with channel height Z as parameter.
shorter via-hole length, we selected a channel height of 400
pm. In addition, although the thermal resistance can be
lowered in regions where the channel width is small, it is fairly
sensitive to channel width changes in such regions. Where the
width exceeded 800 pm, the decrease in the thermal resistance
becomes less and finally levels off. On the other hand,
enlarging the channel width is undesirable in maintaining
sufficient via-hole clearance.
Taking these thermal resistance and via-hole clearance
relationships into consideration, we therefore decided upon a
final channel width of 800 pm. Under this condition we
achieved a thermal resistance of OS”C/W, which is almost
equal to that obtained by conventional liquid cooling [l].
Coolant Distributor and Collector Structures
It is recognized that a uniform liquid flow distribution is
essential to maintaining a nearly isothermal device tempera-
ture,
which in turn achieves uniform electrical characteristics.
Because the liquid flow distribution is sensitive to the coolant
distributor and collector dimensions, we designed an optimal
structure incorporating the continuous flow model as well as
the results from a discrete flow distribution system. In our
procedure, we dealt only with the counter flow type because
the parallel flow type is generally undesirable for obtaining a
uniform velocity profile.
A mathematical model which assumes that the branching
flow can be replaced by a narrow rectangular duct flow is
shown in Fig. 3. The individual branching channels at a
distance AL are replaced by an equivalent rectangular slot
having length
L
=
NAL
and width
Nd/L,
where N is the
number of channels. Applying the continuity and momentum
equations to a control volume element of the model and
incorporating friction loss yields the following differential
equations for velocities, Vi and V,, which are in the X-
direction in the distributor and collector, respectively.
Assuming that ‘V, equals zero, the following equation can be
written for the distributor:
2
Al z= -2PA1 v, %-A,E g q
(4)
1
p”1
,$ontrol Volume
Channd
Fig.
3. Mathematical model of complete flow distribution system.
where A I is the cross-sectional area of the distributor,
PI
is the
pressure,
D1
is the equivalent diameter, p is the liquid density,
and [ is the friction loss factor.
Using the velocity component V,, which joins the branching
flow, and the collector flows which are assumed to be (Y, V
where (Y, generally takes the value of 0.4, the following
equation can be written for the collector:
where
A2
is the cross-sectional area,
P2
is the pressure, and
D2
is the equivalent diameter.
The flow rate qd at discrete channels which relates (4) and
(5) is written as
d’V, qd ca
-= --=-
dx
Al AIM
Ca
=-
-42u
=---=-
(6)
where C is the flow coefficient and
a
is the cross-sectional area
of the discrete channel. Since it is difficult to obtain a general
solution for the simultaneous equations
(4)-(6),
the numerical
calculation was performed using the Milne method.
The nonuniformity ratio, defined as the ratio of the
maximum to minimum flow rate for the individual channel, is
shown in Fig. 4 as a function of the equivalent diameter ratio,
defined as the’ channel equivalent diameter
d
divided by the
distributor equivalent diameter
D.
Here the collector equiva-
lent diameter was chosen to be equal to that of the distributor.
As is clear, a completely uniform flow has a nonuniformity
ratio equal to unity. An increase in the equivalent diameter
ratio or in the number of the branch channels results in a larger
nonuniformity. When the number of branch channels is
increased, the equivalent diameter ratio should especially be
small to obtain a uniform flow. An equivalent diameter ratio of
less than 0.1 is therefore chosen.
KISHIMOTO AND OHSAKI: VLSI PACKAGING TECHNIQUE
331
5
0 0.1 0.2 0.3 0.4 0.5 0.6
L Equivalent diameter ratio (d/D)
Fig. 4. Nonuniformity ratio versus equivalent diameter ratio with number of
branching channels N as parameter.
Under a channel cross-section condition of 400 pm high
x
800 pm wide as indicated in the prior section, the equivalent
diameter
d
of each channel becomes about 533 pm. Assuming
the distributor and collector widths to be 10 mm, for example,
the coolant distributor and collector heights become 3.6 mm.
Fabricating the coolant distributor and collector is easy using
the same punching process ‘as is employed in via-hole or.
channel formation. Therefore, the coolant distributor and
collector can be formed into a single body within the substrate.
PACKAGE FABRICATION
A conventional and improved process flow outlines for
package fabrication are compared in Fig. 5. To strengthen the
metallic mold for channel punching, the mold pitch has been
chosen to be 5.08 mm, which is twice that of the via-hole or I/
0 pin center spacing. This meant, of course, that channel
punching had to be performed twice during the channel
formation operation. Furthermore, the coolant channels were
arranged into a staggered two-story construction so that a cross
section of several channels would be equalized, with the
punching action of the channels prevented from negatively
influencing the location of the via-hole formation.
The process flow consists of five steps. First, green sheet 1
is channel-punched. Second, green sheet 2 is channel-punched
shifting the position 2.54 mm compared with that for green
sheet 1. Third, via-hole punching is done following green
sheet 1 and 2 stacking to ensure accurate alignment. Fourth,
the conductor layers and lid cover are stacked onto green
sheets 1 and 2. Finally, the I/O pins are co-fired and brazed
into the substrate.
The process shown in Fig. 5(b) represents an improvement
over the process in Fig. 5(a). The cross section of several
channels, in particular, the channel width, could be better
equalized compared with the process of fabricating all
channels into a single green sheet. This improvement is
dramatically shown in Fig. 6. When the channels were
punched into one identical green sheet, the width of the
initially punched channels was enlarged, while that of the
subsequently punched channels was narrowed by the shear
stress resulting from the second punching.
By cutting open the center portion of a package, the flow
rate distribution was measured using a collector tube to collect
Conventional
process
Improved
process
Co -firing
Brazing
!---I
I/O pins
Fig. 5. Package fabrication process. (a) punching channels into same green
sheet. (b) Improved channel-punching process. (c) Via-hole punching
process by which green sheets 1 and 2 are stacked after via-hole punching.
(d) Improved via-hole punching process.
z 1000
z 900
r
E
800
3
700
6
z
600
‘I
0
6
5001
0 5 IO I5 20 25 30
Channel location
(a)
= 900
z
5
800 t
%i
I
I
i SOOt
5
500’
I I
I
I
I
I
0
5 lo 15 20 25 30
Channel location
@I
Fig. 6. Channel width versus channel location. (a) Using process shown in
Fig. 5(a). (b) Using improved process shown in Fig. 5(b), with coolant
channels arranged into staggered two-story construction.
the outflow from each channel. The flow distribution obtained
for each channel is shown in Fig. 7. The flow rate ratio was
determined by the flow rate of each channel divided by the
average flow rate over all channels. The solid curve represents
the analytical result by numerically solving simultaneous
332
IEEETRANSACTIONSONCOMPONENTS,HYBRIDS,ANDMANU~ACTURINGTEcHNOLOGY,VOL.CHMT-9,NO.4,DECEMBER 1986
$ 1.2
0 1.0
.-
p 0.8
0, 06
5
0.4
4 0.2
1
A
uooou
*I---
-Calculated
0 Measured
Total flow rate 0.9 literlmin
0 5 IO 15 20 25 3c
Channel locat ion
Fig. 7. Flow rate ratio versus channel location when total flow rate is 0.9 I/
min.
.
equations (4)-(6). As can be seen, the flow rate excursion was
small, and an almost completely uniform flow distribution
could be realized due to the equalization of most of the channel
cross sections. The maximum excursion shows an approxi-
mate five-percent increase, and a maximum eight-percent
decrease. Furthermore, the agreement between the experimen-
tal and the calculated results is excellent. This confirms that
the continuous flow model is a valid means to designing the
coolant distributor and collector structure.
Because the via-holes are fabricated after the channels are
punched, it is possible to avoid the discrepancies often
occurring between layers. In fact, excellent interconnection is
actualized as shown in Fig. 8. Furthermore, we confirmed
experimentally that no water permeability exists, and that the
fabrication of the coolant channels near the via-hole does not
negatively influence electrical performance.
COOLING CAPABILITY
Using the aforementioned design procedure, an indirect
liquid cooling package was constructed which could be used to
assess the cooling capability. The fabricated package dimen-
sions were 85 mm wide
x
105 mm long on which a 5
x
5
array of chips (10 mm* maximum) was mounted. The
substrate featured 29 very fine coolant channels, six conductor
layers, and 900 I/O pins. Table I lists the specifications of the
fabricated package.. A photograph of the overall package is
shown in Fig. 9, with the lids for the coolant distributor and
collector removed. Fig. 10 is a closeup of the package
demonstrating that a uniform cross section of several channels
was realized.
The cooling capability was measured using this fabricated
package and was evaluated by computer simulation. The
simulation was accomplished by the three-dimensional finite
difference method (FDM). The heat balance equation was
written for each node established in the center of the control
volume. The equation for each node is written as
N 1
(7)
where
T
is the temperature,
R,
is the thermal resistance, Q is
the amount of heat absorbed, and subscripts i and j are the
number of nodes. The nodal
Ti
temperature is unknown, and
there are N unknowns for N nodes. These simultaneous
Contientional process
Improved process
(4
(b)
Fig. 8. Photograph of fabricated via-hole. (a) Using process shown in Fig.
5(c). (b) Using improved process shown in Fig. 5(d), in which excellent
interconnection is actualized.
TABLE I
FABRICATED PACKAGE SPECIFICATIONS
Chip chip size
10 mm square maximum
mounting chips
5 X 5 array
number of I/O pins per chip
124
Substrate outside dimensions
85 mm wide x 105 mm
long
x
2 mm high
outside dimensions of coolant 7 mm wide
x
77 mm
distributor and collector
long
x
1 mm high
number of conductor layers 6
number of I/O pins
900 (30 x 30)
I/O pin center spacing
2.54 mm
via-hole diameter 200
pm
Cooling number of channels
29
section channel pitch 2.54 mm
channel length
86
mm
channel width
8OOpm’
channel height
400 Pm
Fig. 9. Photograph of fabricated package.
KISHIMOTO AND OHSAKI: VLSI PACKAGING TECHNIQUE
333
-m
10
Collector 1 ( 1 ]
Fig. 10. Close-up of fabricated package; coolant channels are 800 pm wide
and 400 pm high.
equations for N are solved numerically. Equations (1) and (2)
are used for calculating the heat transferred from the channel
surface to the liquid flow.
Experimental Setup
The experimental setup shown in Fig: 11 was constructed to
assess the cooling capability. A 5
x
5 array of chips
measuring 8 mm2 was bonded onto the package using high
thermal conductivity epoxy resin. The heat generated in the
package was transferred to the coolant, eliminated by an air-
cooled heat exchanger having 1.5 kW heat removal capability.
The coolant temperature deviation was maintained at less than
2°C. The cooling liquid was supplied to the package through a
miniaturized pump.
Thermal Resistance
The excursion of thermal resistance from a chip junction to
the inlet coolant is shown in Fig. 12 as a function of the chip
location (see Fig. ll), which is perpendicular to the coolant
flow. The solid curves represent the analytical results by
FDM, assuming a completely uniform flow. It is clear that
agreement between the experimental and analytical results is
excellent. Because a completely uniform distribution of flow is
achieved as shown in Fig. 7, it was possible to maintain the
thermal resistance excursion at less than ten percent.
On the other hand, Fig. 13 shows the thermal resistance
from a chip junction to the inlet coolant as a function of the
chip location parallel to the coolant channel. It is clear that the
thermal resistance increases along with the coolant flow
because of the increase in the coolant temperature rise. When
the total flow rate is increased, the thermal resistance is
lowered, however, since the coolant temperature rise de-
creases due to the increase in the heat capacity and in the heat
transfer coefficient as well.
Assuming that the allowable temperature rise is 5O”C, the
allowable heat dissipation per package at 0.3 Umin is 300 W,
and 380 W at 0.8 l/min of flow rate. Neglecting the thermal
diffusion, the temperature rise of the liquid coolant passing
through the channels is almost 5°C at 0.8 l/min of flow rate.
At 0.3 l/min, however, the coolant temperature rise increases
to as much as 20°C. Therefore, the total flow’rate must be 0.8
l/min or more to ensure a reduction in the coolant temperature
rise.
Fig. 11. Experimental setup to assess cooling capability.
6
t
-Calculated
0 q
A Meowed
4
0.3litcrhnin
2
t-
063lilerlmin
08liter/min
5
E
0)
I
6 II
.I6 21
Chip location
Fig. 12. Thermal resistance versus chip location perpendicular to coolant
flow with total flow rate as parameter.
I-
Chip locat ion
Fig. 13. Thermal resistance versus chip location along coolant channel.
Allowable Heat Dissipatidn
The allowable heat dissipation may be calculated to satisfy
the upper limit of the chip junction temperature of 85°C. This
chip junction temperature is obtained using the equation
Tj = Tn + A Ta~ow
+ATc=r,+Rj-cP+ATc s 85”~ (8)
where
Tj
is the chip junction temperature,
Ti,
is the inlet
coolant temperature,
AT,
is the temperature rise of the
334.
IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. CHMT-9, NO. 4, DECEMBER 1986
coolant,
Rj-,
is the overall thermal resistance per chip, and
P
is the amount of heat generated in a chip. In general,
Tin
is
maintained at less than 25 “C since the heat is drawn, off
through an externally provided heat. exchanger, and
T,
is kept
below 10 or 15°C when three or four packages are connected
in series [6]. Therefore, from (8) the allowable temperature
rise A
Tallow
is 50 or 55°C.
The allowable heat dissipation for the fabricated package is
shown in Fig. 14 as a function of the total flow rate. In this
case the allowable temperature rise is assumed to be 50°C and
the highest possible value of
Rj-,
is used. The allowable heat
dissipation increases when the total flow rate increases
because
Rj-,
decreases as shown in Fig. 13.
This coqling system allows the chip to dissipate up to 16 W
and the package itself to dissipate up to 400 W at a flow rate of
1 .O l/min. This value is equal to or larger than that for
conventional indirect water cooling.
Discussion
The allowable heat dissipation depends on the thickness tif
the conductor layer since the heat generated in the chips is
conducted from the device junction to the channel surface by
way of the multilayered alumina substrate. The allowable heat
dissipation dependent on the conductor layer thickness was
calculated by FDM with the calculated results shown in Fig.
15. The solid curves represent the results of a 5 x 5 array of 8-
mm* chips mounted on the substrate, while the dotted curves
represent the results for lo-mm* chips. The open circle
represents the experimental results. In this case the total flow
rate is chosen to be 1.0 l/min.
When the multilayered substrate thickness is increased, the
allowable heat dissipation decreases because of the increase in
the internal thermal resistance. At a 6-mm thickness (about 35
layers), however, the package can dissipate up to
12
W per
chip (8 mm*) and 300 W per package using epoxy resin as a
die bonding material. Furthermore, reducing the internal
thermal resistance increases the allowable heat dissipation.
Moreover, enhancing the die bonding area using a higher
thermal conductivity medium lowers the internal thermal
resistance as well.
Changing the bonding medium from epoxy resin to Sn/Pb
solder, for example, increases the allowable heat dissipation to
14.5 W per chip and to 360 W per package. Thus the cooling
capability limit can be extended by over 20 percent through a
reasonable design change. Additionally, enlarging the chip
size to 10 mm* increases the allowable heat dissipation to 450
W per package, owing to the increase in conduction area, and
extends the cooling capability by over 50 percent.
To further clarify the advantages of this innovative cooling
technique, we compared the currently obtainable volume
cower densities (the allowable heat dissipation for a package’s
outward volume) as shown in Fig. 16. The measured volume
power density for the proposed -technique exceeds 17 kW/l
(300 W/(10.5 cm
x
8.5 cm. -x 0.2 cm)) with dramatic
improvement being actualized over the conventional cooling
techniques. This density represents a tenfold increase over
conventional indirect liquid cooling and equals that of immer-
sion cooling [7].
c
0 Measured
100
I
I I I I
0
02 0.4 0.6 08 1.0
Total flow
mte
( I iter/min)
Fig. 14. Allowable power dissipation per package as function of total flow
rate, when allowable temperature rise is 50°C.
g 7001
8
f 600 -
n
$ 500-
n
-g 400-
.s
.; 300-
-0
b
.g
xX3-
0
$ -loo-
CI
\
\
\
\
\
-5x5 array of 8mm
s&are chip
----IOmm square chip
Total flow rate I.0 literlmln
:
I I I I
2
O-2 4 6 8 I
Conductor layer thicknesstmm)
Fig. 15. Allowable power dissipation per package as function of conductor
layer thickness with chip size and die bonding material as parameters.
Proposed Liquid
Cooling Technique I[
Immersion Cooling I-
i o-’
I o- ’
IO0 IO' IO2
Volume Power Density (KW/liter)
Fig. 16. Volume power density for various cooling technologies.
KISHIMGTG
AND OHSAKI:
VLSI PACKAGING TECHNIQUE
CONCLUSION
A new technique for increasing the cooling capability and
for effecting high-density stack packaging for multichip
package application has been developed. The technique
mounts VLSI chips on a multilayered substrate which incorpo-
rates very fine coolant channels.
The optimal structure for cooling sections was investigated
by computer simulation and experiment, with the former being
implemented. The obtained numerical solution of the coolant
flow distribution ensured that the coolant distributor and
collecter structure dimensions could be determined to meet the
uniform velocity distribution condition. Additionally, the
channel cross section was designed to be 800 pm wide
x
400
pm high to achieve a lower thermal resistance.
Based on the results of these structures, an indirect liquid
cooling package was fabricated which mounted a 5 x 5 array
of VLSI chips on a substrate measuring 85 mm x 105 mm.
An allowable heat dissipation higher than 400 W per package
(mounting 8 mm2 chips) was realized at a flow rate of 1.0 I/
min. Furthermore, since the thickness of the cooling section is
smaller than 1 mm, the volume power density was found to
increase to 17 kW/l or more, a value tenfold greater than that
335
obtained by conventional indirect water cooling and equal to
that obtained by immersion cooling.
This new packaging is thus particularly suited to. future
needs, especially in terms of its excellent cooling capability,
high-density packaging which reduces the overall wiring
length, chip size enlargement, increased the number of
conductor layers, and so on. Accordingly, this technique will
find broad application to large-scale high-density stacked
multichip packaging.
Ul
[a
131
[41
PI
161
171
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