Trends in VLSI Design :

connectionbuttsElectronics - Devices

Nov 26, 2013 (3 years and 4 months ago)

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TrendsinVLSIDesign:
MethodologiesandCADTools
Presenter:RajSingh
ICDesignGroup
CEERI
Pilani333031
Tel:01596-242359
Fax:01596-242294
Email:raj@ceeri.ernet.in
ViewofVLSIDesign
ViewofVLSIDesign
Algorithm
Technology
CAD Tools
Architecture
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VLSIDesignComplexityIssues
VLSIDesign:ProblemDomainComplexity
•Competingorcontradictoryrequirements(speed,power,area).
•Applicationareaspecializationandknowledge.
•Changing/evolvingspecications.
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VLSIDesignComplexityIssues
VLSIDesign:Design/DevelopmentProcessComplexity
•Rapidlychangingtechnology.
•Largetaskrequiringmulti-disciplinaryteam.
•Largedesignspace.
•Shortdesigncycle.
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VLSIDesignComplexityIssues




VLSIDesign:Design/DevelopmentProcessComplexity
•First-timesuccessrequirement.
•Multipleviews/representationseachwithdifferentcharacterization.
•Inadequatedocumentation.
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VLSIDesignComplexityIssues
VLSIDesign:ComplexityDuetoManyChoices
•Manytechnologies/implementationchoices(NMOS,CMOS,...)
•Manymethodologies(FPGA,Semi-custom,Fullcustom,ASIC,...)
•Manylogicforms(Dynamic,2-phase,4-phase,Static,...)
•Combinatorialexplosionasonegoesdowninabstractionlevel.
•Manypossiblepartitionsateachlevel.
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VLSIDesignComplexityIssues
VLSIDesign:OtherComplexities
•ClockingandTimingissues.
•Concurrencyofhardwareoperations.
•Testing-relatedissues.
•Packaging-relatedissues.
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VLSIDesignProcessOverview
SynthesisandAnalysis
VLSIdesignactivityis
Synthesis
andthen
Analysis
atseveralsuccessivelevelsofdesignabstraction.
SynthesisPhase:Proposingasolutionofthedesignproblematacertain
levelofabstraction.
AnalysisPhase:Checkingthatsolutionforitsvalidityaswellasitscon-
sistencywithsomeotherdesignrepresentation(usuallyatadifferentlevelof
abstraction)andthecharacterization/evaluationofthedesignsolution.
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VLSIDesignProcessOverview




SynthesisandAnalysis
Ateachlevelofdesignabstraction,synthesisandanalysismaybeusedina
loop(iterativeprocedure)toarriveatanoptimalsolution.
Synthesisinvolves
creativity
and
newconcepts.
Analysis(exceptwhendevelopingnewmethodsofanalysis)involves
applying
knownmethods
forcheckingthedesignandprocessingoflargedata
using
known/standardmethods.
Thus,synthesishastraditionallybeentheprerogativeofhumans,whileanal-
ysishastraditionallybeenthersttasktohavebeenhandedovertothecom-
putersviacreationofCADtools.
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VLSIDesignProcessOverview




SynthesisandAnalysis
Synthesistoolsarecreatedwhenthesynthesisprocesscanbeexpressed
asamethod.
Analysistoolsalsoimproveasaresultofhumancreativityandexploration.
Therefore,thedivisionoflabourinVLSIdesignisclear:
Humansdothecreativepartsandcomputers(CADtools)dothecumber-
somedetailedwork.
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VLSIDesignProcessOverview
.
.
.
. . .
. . .
. . .
Top Level of Abstraction
Lower Level of Abstraction
Lowest Level of Abstraction
More Abstract Level
Synthesis
(Check)
Analysis
(Consistency)
Less Abstract Level
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TraditionalVLSIDesignFlow
TraditionalVLSIDesignFlow
Design VerificationDesign Entry /
OK ?
Design Output
Design Entry /
Design Output
Yes
No
No
Yes
OK ?
No
Yes
Design Output
OK ?
No
Yes
Design Output
OK ?
No
Yes
Design Output
Specification From User
OK ?
Design Verification
Through Simulation
Design Synthesis
Design Synthesis
Design Synthesis
Design Entry /
Transistor/Circuit Level
Layout/Physical Level
Design Entry /
Design Synthesis
Design Verification
Through Simulation
Logic/Gate Level
Design Verification
Through Simulation
Design Verification
Through Simulation
Design Entry /
Design Synthesis
Register-Transfer Level
Through Simulation
Behavioural Level
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HDL-BasedDesignFlow
HDL-BasedDesignFlow
Code Organization Choice
Architectural Choice
Logic Implementation Choice
Placement and Routing Choice
Behavioral Description in HDL
RT-Level Description in HDL
Physical Design
Specifications + Constraints
Gate-Level Netlist
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VLSIDesignMethodologies
VLSIDesignMethodologies
Systematicdesignmethods(called
designmethodologies
)arenecessaryfor
successfullydesigningcomplexdigitalhardware.
Differentdesignmethodologiesdifferintheir
choiceofnumberandlevels
of
designabstractionsusedduringthedesignprocessandthemannerofcon-
straintsonthetranslationsbetweentheabstractionlevels.
Theseconstraintsareusuallyintheformofuseofaparticularstructuretype
atthelowerlevelofdesignabstractionwhiletranslatingthedesigndescription
thatexistsatahigherlevelofabstraction.
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VLSIDesignMethodologies




VLSIDesignMethodologies
Forexample,whiletranslatingfromthelogiclevelabstractiontophysicallevel,
populardesignmethodologiesare:
1.FPGA.
2.Gate-Array.
3.Standard-Cell.
4.Full-Custom.
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VLSIDesignMethodologies




VLSIDesignMethodologies
Thepopularmethodologiesforimplementingthecontrolpartare:
1.HardwiredControl.
2.MicrocodedROM-basedControl.
3.PLA-basedControl.
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Design-CAD-FoundryInterfaces
Design-CAD-FoundryInterfaces
Fabricated Design
CAD Tools
Back-end
CAD Tools
Front-end
Proprietary Design Tools
and Libraries
Design for Fabrication
Vendor
Foundry
CAD Tools
Design
CenterUsers
Chip
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CADTools
CADTools:ReducingRiskofFailure
•Simulateperformancebeforefabrication.
(simulation)
•Explorevariousalternativesandcharacterizethemintermsofcost,per-
formance,...
(designspaceexploration)
•Checkagainstallpossibleknownfabricationprocessviolationsbefore
dataisgiventomanufacturing.
(designsign-off)
CADtoolshelpdiscoverproblemssothattheycanbecorrectedatmin-
imalcost,bothintermstimeandresources.
(catcherrorsasearlyas
possible)
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DesignMethodologiesandCADTools
CADToolsatVariousLevelsofDesignHierarchy
Design Entry (HDL)
Design Entry (C, C++, ...)
Design Entry (HDL)
Design Entry (Schematic)
Specification From User
Behavioural Simulation
Behavioural Level
Behavioural Synthesis
RTL Simulation
Analysis
Synthesis
Synthesis
Logic Simulation, LVL,
Static Timing Analysis, ERC
AnalysisSynthesis
Design Entry (HDL)
Design Entry (Schematic)
DFT Insertion, ATPG
Logic Synthesis
Register-Transfer Level
Logic/Gate Level
Circuit Synthesis
Design Entry (Schematic)
Design Entry (SPICE)
Circuit Simulation,
Power Analysis,
Delay Estimation
Transistor/Circuit Level
AnalysisSynthesis
Layout/Physical Level LVS, DRC,
Circuit Extraction
AnalysisSynthesis
Design Entry (Layout),
Floor Plan,
Place-and-Route
Flash Analysis
AnalysisSynthesis
PG File Creation
Fracturing, Sorting,
Process Simulation, Lithography Simulation
Analysis
Logic Optimization
Layout Synthesis
Mask Level
Foundry
Yield Prediction, Tester File Creation
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DesignMethodologiesandCADTools
VLSIDesignandCADTools
System Design and Behavioral Design
Layout Design
STRUCTURAL
DOMAIN
BEHAVIORAL
DOMAIN
DOMAIN
PHYSICAL
System Structure
Processors, Buses
RAM, Registers, ALUs
Gates, Flip-flops
Transistors
Transistor Layouts
Cell Layouts
Block Layouts
Chips, Floorplans
Boards, MCM, System Partitions
Transistor Functions
Boolean Expressions
Register Transfers
Flow charts, Algorithms
System Behavior
RTL Design and
Logic Design
Transistor Design
Cell Design
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DesignMethodologiesandCADTools
CADToolsClassication:Interaction-Based
Front-endTools:
DesignEntry,Editors,Simulation,Synthesis,TimingAnalysis,DFTInsertion,
TestGeneration,...
Back-endTools:
FloorPlanning,Place-and-Route,Extraction,LVS(Layoutvs.Schematic),LVL
(Layoutvs.Logic),ERC,DRC,PatternGenerators,FormatConverters,Mask
Graphics,...
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DesignMethodologiesandCADTools
CADToolsClassication:Function-Based
DesignCaptureTools:
Editors,VHDL,SystemVerilog,SystemC,StateCharts,FSMCapture,...
SynthesisTools:
BehavioralSynthesis,RTLSynthesis,FPGASynthesis,LogicSynthesis,Phys-
icalSynthesis,Module/CellGenerators(ROM,PLA,RAM),Data-pathCom-
piler,Adder/MultiplierGenerators,DSPSynthesis,...
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DesignMethodologiesandCADTools




CADToolsClassication:Function-Based
AnalysisTools:
•Checkers:DRC,ERC,NetCompare,RatioChecker,Short-circuitChecker,
Fan-in/Fan-outChecker,PowerChecker,...
•Veriers:TimingVerier,Simulators,ICE/HardwareSimulators,Formal
Verier,...
TestingRelatedTools:
ATPG,DFTTools,...
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TrendsinDesignMethodologiesandCADTools
DesignMethodologiesandCADTools:FirstEpoch(1959-1979)
Full-customdesignmethodology.
Layoutleveltools,Circuitleveltools.
TechnologyatSSI,MSI,LSIlevels.
Designer,UserandToolsDeveloperallatasinglecompany(monolithic).
Productivityofdesigner(notionally)=10transistors/day.
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TrendsinDesignMethodologiesandCADTools
DesignMethodologiesandCADTools:SecondEpoch(1980-1989)
Standard-Cell/Gate-Array/ASICdesignmethodology.Shortersynthe-
sis/analysisloop.
Logicleveltools,Macrogenerators,Modulecompilers.
TechnologyatLSI,VLSIlevels.
User/DesignerseparatedfromToolsDeveloperi.e.separatecompaniesselling
toolscomeintobeing.
Productivityofdesigner(notionally)=10gates/day.
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TrendsinDesignMethodologiesandCADTools
DesignMethodologiesandCADTools:ThirdEpoch(1990-1999)
HDL-baseddesignmethodology.FPGA-basedprototyping.Designexplo-
rationmadeeasier,Estimatorsforperformancebecomeavailable.
RT-levelsynthesis,PreliminaryBehaviouralsynthesistools;HDL-basedde-
signentry,HDLCodeanalyzers/advisers.
TechnologyatVLSIlevels.Deep-submicron(DSM)issues.
User,DesignerandToolsDeveloperbecomeseparategroups/companies.Fa-
blesscompanies.
CADtoolsmovetowardsPCplatforms.
Productivityofdesigner(notionally)=10linesofVHDLcode/day.
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TrendsinDesignMethodologiesandCADTools




DesignMethodologiesandCADTools:ThirdEpoch(1990-1999)
Low-powergainsimportance.Mixed-signaldesignissues.
ToolsfordesigningMEMSandEmbeddedsystemsappear.
IntellectualProperty,DesignRe-use,RecongurableComputing,Cores,ASIP,
ASSP,DSP,...
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TrendsinDesignMethodologiesandCADTools
DesignMethodologiesandCADTools:FourthEpoch(2000-...)
System-on-Chipdesignmethodology.Block-levelchipdesign(usingcores,
IPblocks).
System-levelsynthesis,MEMSdesigntools.Mixed-signaldesigntools.
ConsolidationamongEDAcompanies.
TechnologyatVLSI,ULSIlevels.Deep-submicron(DSM)andpower-leakage
issues.Coppermetallization,newdielectricmaterials,newdevicestructures.
Productivityofdesigner(notionally)=10linesofspecicationcode/day.
RFICDesign,Hardware-SoftwareCodesign,Web-basedCADtoolsandde-
signenvironment.
MethodologyandToolsforNon-SiliconbasedDesigns?Nano-technology?
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Trends:CodesignandEmbeddedSystems
WhatisHardware-SoftwareCodesign?
Integrateddesignofelectronicsystemsimplementedusinghardwareandsoft-
warecomponentsdeveloped
concurrently
and
cooperatively
.
Itisapartofthesystem-leveldesignwhichmayconsistofmechanical,elec-
tricalorchemicalpartsinadditiontoelectronics.
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Trends:CodesignandEmbeddedSystems
AdvantagesofHardware-SoftwareSystems
•Familyofproductsonacommonhardwareplatform.
•Upgradationandefcientevolutionpathofproductthroughupdatingsoft-
ware.
•Chip/circuit'shighcostreducedbyprovidingfunctionalityinsoftware.
•Rangeofsystemcostsandperformancesfrom(highcost+highperfor-
mance)to(lowcost+lowperformance).
Embeddedcore,ASIC/FPGA,Microprocessor+Software,...
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Trends:CodesignandEmbeddedSystems
ApplicationAreas
•Largesystemse.g.Aircraft,Telecommunication.
•Computingsystemse.g.Supercomputer,Workstation,PC.
•Strategic/Defencesystemse.g.Radar,Missile.
•Embeddedsystems.
Controle.g.automobile,medical,industrial.
Hand-helde.g.cellularphone,PDA.
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Trends:CodesignandEmbeddedSystems




ApplicationAreas
Consumere.g.microwaveoven,washingmachine.
Musicsystemse.g.MP3players,M4aplayers,Oggplayers.
Soundrecordinge.g.phone-answeringmachine.
Speechprocessinge.g.voicesynthesis.
Graphicsprocessinge.g.laserprinter,X-terminal.
Videoprocessinge.g.VCD,DVD,DigitalTV,HDTV.
RoboticsandMechatronics.
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Trends:CodesignandEmbeddedSystems
TypicalEmbeddedSystemArchitecture
INPUT(S)
OUTPUT(S)
Sensors
Actuators
Processor
Memory
ASIC
Glue
Logic
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Trends:CodesignandEmbeddedSystems
EmbeddedSystemDesignSteps
•System-levelModelingandSimulation.
•Hardware-SoftwarePartitioning.
•Concurrently,
HardwareSynthesis.
InterfaceSynthesis.
SoftwareCodeGeneration.
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Trends:CodesignandEmbeddedSystems
EmbeddedSystemCodesignEnvironment
System Model
Partitioning
INTERFACE
NetlistNetlist ?Code
CO-SIMULATION
Optimization
TranslatorSynthesis ?Synthesis
SOFTWAREHARDWARE
uP, uC, DSP, ...ROM, Glue LogicFPGA, ASIC, ...
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Trends:RecongurableComputing
WhatisRecongurableComputing?
RecongurableComputingisanapproachthatallowsrecongurableaspects
ofhardware(e.g.FPGAs)tobeasexibleassoftware.
Itcanbeimplementedeither
statically
(congureandthenrepeatedlyexecute)
or
dynamically
(repeatedlycongure-and-execute).
Itrequiresextensivekowledgebaseandquantitativeapproachforevaluat-
ingdifferentsystemarchitecturaloptionsvis-a-visthesystemrequirements
(intermsofspeed,power,cost,user-interface,congurability,...).
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Trends:RecongurableComputing
WhyRecongurableComputing?
•Reducedtime-to-market.
•CheaperthanASICsorprocessors.
•Moreapplicationspecicadaptationthanprocessors.
•Lowersystemlife-timecostandupgradeableintheeld.
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Trends:RecongurableComputing
TypesofRecongurableComputing
•Processor+FPGA(EmbeddedSystems).
•RecongurableCompiler.
•RapidPrototyping.
•HardwareAccelerator;HardwareEmulator.
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Conclusion
Conclusion
•VLSIDesignisacomplextask.
•DesignmethodologiesandCADtoolsareimportantpartnersoftheVLSI
designerinovercomingthiscomplexity.
•CADtoolsfreetheVLSIdesignerfromeasy-to-dotasksandallowthe
designertoconcentrateoncreativetasks.
•DesignmethodologiesandCADtoolsevolvebasedondesigner'sneeds.
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