Selecting Colors for Representing VLSI Layout

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Selecting Colors for Representing VLSI Layout 
Giordano Bruno Beretta
Selecting Colors for Representing VLSI Layout
Giordano Bruno Beretta
EDL·88·7 December 1988 [P88·00226j
©
Copyright 1988 Xerox Corporation. All rights reserved.
Abstract: A palette of colors for the representation of VLSllayout is described. These colors,
called
discriminable,
maximize the readability of layout. The benefit of using these colors is not
limited to the display on a color video monitor. With some precautions, they can be utilized also
for printing. Finally, a scalable printing technique which can permit an entire chip to be scaled
to the size of a book page, is discussed.
CR Categories and Subject Descriptors: B.7.2 [Integrated Circuits]: Design Aids­
graphics;
0.2.2 [Software Engineering]: Tools and Techniques -
user interfaces.
Additional Keywords and Phrases: functional colors, IC layout, printing
Xerox Corporation
XEROX
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304
1
1. Introduction
1. Introduction
Color is increasingly supplanting the use of black and white stipples to render VLSI layout The
function of color. as it was for the stipples. is to allow the reader to recognize in which layer features are
drawn. The problem is that in most design automation systems the aspect of readability is rarely
considered because the choice ofcolors is purely
ad
hoc.
It
is not possible here to reproduce in facsimile the VLSI layout color rendition of common
plotting packages. If one browses. for instance. though the May 1988 issue of
VLSI System DeSign.
one gets a cross section of popular systems and may note a sad state of affairs regarding printing VLSI
layout
Because it is much harder to describe layout strategies in words than with illustrations. the ability
of rendering VLSI layout is important. Because the same method is used also to produce checkplots.
the clarity of the colored rendition is crucial. An equivocal representation oflayout is a potential source
of errors.
The problem of color selection has already been studied in the design automation community in
the context of printed circuit board design [I). Frome showed experimentally that it is possible to find
a universally accepted color palette which increases the designer's readability of PCB layout by a
statistically significant level.
The color conventions used to represent VLSI layout vary from one layout editor to another. In
this paper there is no attempt
to
advocate one convention in favor of another. Instead. a general
methodology on how to think about the use of colors in the context of VLSI layout representation is
presented. As an example. the colors proposed by Mead and Conway [2) for the NMOS process. and
listed in table
1.
are used as a starting point throughout this paper.
diffusion green
transistor channels green
ion implantation yellow
polysilicon red
metal blue
contact cuts black
Table 1. Colors proposed by Mead and Conway for the representation of layout.
Why is there no natural choice in the first place? VLSI layout editors show an abstraction of the
actual layout, and the colors are purely functional. i.e.• their purpose is to distinguish the different
interconnect levels more unmistakably than black and white stipple patterns would do.
A chip die consists of silicon. diffusion. and aluminum. which are grey materials. In principle. the
colors to represent the various layers can be chosen at random. However. when a die is observed under
a microscope. colors are seen. Visible light has a wave length between 0.38
I'm
and 0.78
I'm.
and the
XEROX PARCoEDL-88-7. DECEMBER. 1988
2
Selecting Colors for Representing VLSI Layout
thickness of some of the physical layers created on a silicon wafer falls within this range. Therefore,
when white light is shone through a wafer, the physical layers act as dichroic filters. Where different
layers overlap, interference at the intralayer boundaries creates additional colors.
Typically, the colors adopted in layout editors are inspired by these colors. However, since the
thickness of one and the same layer is different from one manufacturing process to another, there is no
canonical choice of the colors.
The questions that have to be answered in a practical implementation include the following:
Which ROB values should be used? Which area fill method (solid, stipples, dithering) should be used?
How should intersections be treated? Should the same colors be used on the video monitor and on the
plotter?
In the remainder of this paper, a robust methodology for choosing ROB values is described. The
proposed color palette meets sufficient quality criteria such that the same ROB values can be used for
printing and still reproduce VLSI layout in the most readable form.
While the discussion in this paper is limited to a CMOS technology, the methodology can be
applied to any other technology, such as the bipolar and BiCMOS technologies.
2. Construction of a Color Palette
In many VLSI CAD systems, the user's recognition of layout is an iterative process. Color is a hint
of the layout components, and the user must first interpret a concomitant monochromatic stipple
pattern [3] or crosshatching. Next, the user applies knowledge about the object's layout (e.g.,
transistors) to fully disambiguate the geometry by context.
A key idea in this paper is to choose a palette of colors which would allow the geometry
to
recognized by color alone, thus allowing the user to read layout faster and eliminate possible
interpretation errors. The need for stipple patterns is thus eliminated, avoiding their menial and
empirical selection to produce reasonably discriminable overlappings.
For esthetic and performance reasons, it is preferable to use solid polygon filling instead of
dithering. Due to the limited number of entries available in color maps or lookup tables, especially in
systems that concurrently run several applications, the color palette should be as small as possible.
The next section will introduce first a basic palette to represent the various layers. Subsequently
the treatment of intersections will be discussed.
2.1. ABasic Color Palette
A basic color palette can be obtained by starting from Mead and Conway's conventions and
distributing the chromaticity values more or less uniformly in an (x, y) chromaticity diagram [4], as
shown in figure l. Clustering of colors is avoided because of the problems this would cause when the
same palette is used for a device with a completely different color gamut, such as a printer. Indeed,
XEROX PARC, EDL-88-7, DECEMBER,1988
3
2. Construction of a Color Palette
Basic
Figure 1.
(x,
y) chromaticity diagram of the
basic color palette. The triangle delimits the
colors that can be displayed on a color video
monitor.
colors that were different on one device could merge on a different device. Table 2 lists the ROB
values used to represent the various layers as defined this way.
Note that the color proposed for metal 1, Cyan
l
,
is quite different from the color for metal 2,
Lightish Vivid Purple Magenta. If more colors are needed, e.g., for additional polysilicon or metal
layers, an orange and a yellow green can be added.
To a fair extent, the association of layers with ROB values in table 2 is arbitrary. The circuit would
be equally readable, if, for instance, the ROB values for polysilicon and diffusion, or for metal 1 and
metal 2 were interchanged.
2.2. Coloring the Intersections
The intersections are the regions where two or more layers overlap. The usual model of
considering the layers to be transparent [3] is not adequate, because the designer's model of layout is
that of a three dimensional layering. For instance, with such an approach transistor channel wells look
like a veil over the area they cover, while in reality they are an ion implantation in the silicon substrate.
A different problem is that of concealing other layers. For instance. in CMOS the second metal
layer can be represented using the color Lightish Vivid Purple Magenta. However, when metal 2
occurs over some material other than a well, the user needs it to be rendered in a more transparent
A variant [5] of the color naming system proposed by the National Bureau ofStandards [6] is used to generate English
language descriptions of the ROB values. Such color names are capitalized to distinguish them from color names used more
informalIy.
XEROX PARC, EDL-88-7, DECEMBER,1988
1
4
Selecting Colors for Representing VLSI Layout
diffusion (0.55, 0.97, 0.16) Lightish Vivid Yellow Green
N-well (1.00, 1.00, 0.70) Light Vivid Yellow
polysilicon (1.00, 0.133, 0.10) Lightish Vivid Orange Red
metal-1 (0.17,0.75,0.82) Cyan
metal-2 (0.91. 0.27, 0.98) Lightish Vivid Purple Magenta
metal vias (0.04, 0.25, 0.93) Vivid Cyan Blue
contact cuts (0.00, 0.00, 0.00) Black
Table
2.
Some RGB values for the representation of single CMOS layers.
interconnect "wires" from hiding the contents of cells over which they are routed. On the other hand.
if Light Strong Magenta Purple is used on all occasions, features such as routing regions become more
difficult to read.
This problem of layers concealing other layers becomes worse as the technologies improve and
more layers are made available to designers, such as double layer polysilicon, triple layer metal. and
twin-well CMOS. In technologies such as BiCMOS, which have even more layers, the problem is
worse.
The question that has to be asked is
How do deSigners read layout?
Designers read layout by
tracing the interconnect that corresponds to circuit signals. Therefore. the main criterion for selecting
colors for the intersections is to make the interconnect traceable.
It is convenient to divide the interconnect layers into two classes. The first class,
cl,
consists of the
interconnect in the polysilicon and diffusion layers. The geometry of this interconnect consists mostly
of narrow and dense tracks in areas of active logic. The second class,
c2,
consists of the various metal
interconnect layers. The geometry of these interconnects consists mostly of wide tracks and possibly
runs on top of cells to distribute power, ground, and clock signals. This latter interconnect class is used
prominently for the routing.
To a first approximation the human visual system is more sensitive to changes in lightness than to
changes in chromaticity [7]. For this reason, the colors in the basic palette are not only different in their
chromaticity (see figure 1), but also in their lightness (as it can be verified from table 2). Indeed, an
even stronger statement can be made. If the VLSI layout is viewed at a reasonable illumination level.
sensitivity to changes in lightness is orthogonal to changes in chromaticity [7]. In other words, lightness
and chromaticity can be used as independent quantities to make regions discriminable.
When the colors for the intersections oflayers are selected, three principles can be used:
1.  The lightness of
cl
geometry is kept constant.
2.  The dominant wavelength of c2 geometry is varied as little as possible.
3.  When it is important to discriminate two different intersection types, the colors should be
as perceptively distant as possible.
XEROX PARe. EDL-88-7. DECEMBER. 1988
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2. Construction of a Color Palette
The first principle allows the designer to trace the geometry pertaining to a
cl
circuit signal by its
intensity alone. making it very easy to follow such geometry when it runs under c2 geometry.
The second principle takes advantage of the typical width of c2 geometry. Such interconnect is
global in nature and its hue is sufficient to trace it.
The
dominant wavelength
of a color can be determined graphically using the
(x.
y)-chromaticity
diagram [4]. White is used as the achromatic reference color. When the point corresponding to the
basic color of a c2 element is connected with a straight line to this reference color. the intersection of
this line with the spectrum locus (the horseshoe-shaped line in the diagram) is the dominant
wavelength. The colors along this line between the achromatic reference color and the spectrum locus
differ only by saturation.
The third principle complements the second. Two colors differing slightly in saturation may not
be discriminable. It is convenient to represent the colors in the CIELAB space [4]. which is uniform.
Uniform means that the Euclidean distance of two colors is proportional to their perceived distance. In
this space the colors can be tweaked until their discrimination is "easy."
As a first step. the lightness of the colors obtained by the second principle is distributed more
uniformly. as shown in figure 2.
It
is interesting to compare this lightness distribution with the one
used by a state-of-the-art VLSI editor (ChipNDaie [8]) for display on a video monitor and shown in
figure 3. Note. that a large number of different colors is used and many colors have the same lightness.
Discriminable
<0."",,,,,..
100
Figure 2. Lightness distribution in a palette of
discriminable colors.
As a second step. the chroma
2
is adjusted so that the coordinates in CIELAB space for two colors
are not too close. Figure 4 shows the chroma for a palette of
discriminable colors
for a double layer
metal technology. Note. that only two dozen different colors are necessary. A list of the colors can be
found as an appendix in [9].
XEROX PARC, EDL-88-7, DECEMBER, 1988
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Selecting Colors for Representing VLSI Layout
(MosA
ConriICcillibriltio,..
Figure 3. Lightness distribution in a palette
used by the ChipNDale VLSI editor.
2.3. A Color for Transistor Gates
This is a controversial issue. According to the traceability paradigm, transistor gates should be in
the same color as polysilicon. The fact that polysilicon over diffusion forms a transistor gate is less
important than the ability to easily read the circuit signal ramifications in the polysilicon interconnect.
However, some designers are used to VLSI editors that represent transistor gates in yellow, the
additive sum of red and green. When yellow is used only in a Vivid Yellow shade, features in this color
stand out optically. Since transistors are the active devices in a circuit, when a VLSI designer looks at
the layout of a cell, he can quickly recognize the cell's function by matching the prominent pattern
formed by the gates.
Caught between these two opposing arguments, a choice between the two possibilities was given to
a group of designers. They preferred that the palette render the transistor gates in yellow for their day­
to-day work, but for journal publications, the preference was for rendering in the same hue as the
polysilicon interconnect.
Degree
to
which a chromatic stimulus differs from an achromatic stimulus of the same brightness. This differs from
saturation, which is independent of brightness.
XEROX PARC, EDL-88-7, DECEMBER, 1988
2
•
•
7
3.
Printing VLSI Layout
.:--+'
•
I
•
•
•
-+-i
•
Figure 4. Chroma for a palette of
discriminable
Discriminable
Con,.ucaUb,.tion
colors
plotted as points in the CIELAB space.
3. Printing VLSI Layout
In section 2.2 there was an infonnal statement about "tweaking colors until their discrimination is
easy." This vagueness was kept to cover the printing case.
The gamut variation from color video monitor to color video monitor still pennits one to specify
minimum distances between colors as generally discriminable. Printer gamuts, however, are very
different from one technology to another (e.g., from electrostatic to thennal transfer), so that it does not
make sense to specify a minimal distance. On the other hand, the time to produce a print is less critical
than the time to paint the display on a video monitor, so that some other tactics can be applied.
On a color video monitor; a designer can easily discriminate about 7000 colors [10]. Hence, if
some small neighborhood is considered around the color points in CIELAB space, these
neighborhoods should have an empty intersection. For the practical purposes of rendering VLSI
layout on a monitor, a radius of 7 units is sufficient to avoid the costly operation of outlining borders
suggested by Trimberger [3]. The reader interested in the mehtods for deriving such values can find a
detailed discussion on visual equivalence in Chapter 5 of reference [4].
3.1. Outlining Region Borders
J
The gamut of colors available on printed paper under office illumination conditions
is
smaller than
the gamut of a color video monitor. The implementor can increase the radius for the above
neighborhoods, but there is still a difficulty. Indeed, a sufficiently large distance in CIELAB space
does not yet guarantee that two regions can be told apart
XEROX PARCo EDL-88-7. DECEMBER, 1988
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8
Selecting Colors for Representing VLSI Layout
Edge detection [11, 12] is the most prominent process in vision pertaining to the readability of
VLSI layout Adjacent regions can be told apart if a border is visible between them. Unfortunately,
border visibility does not depend simply on the distance in CIELAB space of the two colors, but on
their lightness difference and on their tritanopic purity difference, which is the relative stimulation of
the red and the green sensitive cones in the retina [7].
The obvious precaution is to outline the regions by an explicit border in a slightly different (e.g.,
more saturated) color. However, there is a simpler and more subtle technique for outlining than to use
a color slightly different than the outlined region's inside area suggested in [3].
Due to lateral interactions in the neural network of the brain's visual system, so called Mach bands
are perceived near the border of two juxtaposed fields of different luminance [4]. On the dark field, a
darker band is perceived, and on the light field, a lighter band is perceived. Figure 2 shows that the
colors in the discriminable palette do not cluster in lightness and that the lightness values are high.
This suggests that a black line separating any two regions that are not contact cuts will assure that Mach
bands are perceived, thus aiding edge detection.
In summary, the traceability is sustained by the
continuity
of interconnect, achieved through the
appropriate choice of lightness and hue. Recognition of regions (that is,
discontinuities)
is facilitated at
the vision level by inducing Mach bands. This contrasts to the common iterative approach mentioned
in the first paragraph of section 2.
3.2. The Resolution Problem
In section 2, the values of the red, green, and blue (or cyan, magenta, yellow, and black for a
printer) components of a color were considered to be real values in the interval [0, 1]. It is clear how to
produce the binary values 1 and 0: ink and no ink. How are the intermediate grey values generated?
Many printers do not permit continuous tone printing. An additive model is used to mix the
colors of the inks with the white of the paper. This additive model combines with the subtractive
model of the ink mixing, forming a mosaic of eight different colors [13].
One technique to generate the intermediate grey values, called
halftoning,
consists in using ink
spots of variable area. Conceptually, for each of the four color separations (cyan, magenta, yellow, and
black) the image is subdivided in a raster of square buckets, which is called a
halftone screen.
For each
bucket, a spot with area proportional to the lightness of the color is deposited on the substrate (paper or
film).
Many digital printers cannot produce ink spots of variable area. On such printers, a group of
pixels can be used to approximate a dot This technique is called
halftone approximation
[14]. Accurate
algorithms have been devised to obtain the same halftoning quality as in traditional methods [15].
Unfortunately, halftone approximation substantially reduces the printer's effective resolution. For
instance, if the printer has a resolution of 1200 pixels per inch and 12 pixels are used to approximate a
dot, the resulting resolution is 100 dots per inch.
XEROX PARC, EDL-88-7. DECEMBER. 1988
9
3. Printing VLSI Layout
While such a resolution may be sufficient for realistic images. it is often not acceptable for VLSI
layout. Interconnect geometry can be thinner than a spot of such size. hence the interconnect geometry
becomes fuzzy and very hard to trace.
Distributing the Iightnesses of the colors in the palette uniformly in each color separation allows
the use of smaller groups of pixels per dot. thus increasing the device resolution.
The fuzziness of the interconnect geometry can be further reduced by using a halftoning algorithm
where. for increasing lightness. the pixels are "turned on" from left to right and top to bottom in a
regular pattern. I f a 3 X 3 pixel matrix is used for each dot. the following threshold matrices have been
"
used in conjunction with the discriminable colors presented in section 2:
.4.5.6
.6.1.7
C:
.1
.3
.2
M:
.5
.3 .8
.7.8.9 .4.2.9
.5
.8
.3
.1.6.4
Y:
.9.2.6
K:
.7.2.9
.1
.7
.4
.5
.8.3
Such dots have the advantage of degrading gracefully in images with elements of sub-dot size
when they are observed at large magnifications. The disadvantage is that putting marks of this size on
paper is much more difficult than for the traditional halftone dots. For most inks. the image will look
"smeary." because not all pixels will receive the same amount of ink. A careful choice of the color
palette is mandatory.
3.3. The Maximal Resolution
For applications in which an even larger resolution is needed. such as illustrating books with
images of entire chips. line art can be used. The separations are then printed in multicolor instead of
full color. avoiding halftoning. In conjunction with a high resolution printer [16J. this allows the
printing of VLSI layout with a feature size of 42
ILm
(600 lines per inch). in which even the layout of a
large chip is readable with the use of a good magnifying glass when it is printed at the size of a book
page. For comparison. the resolution of a typical halftoned picture - such as a microphotograph of a
chip die - is 169
ILm
(150 lines per inch).
It should be noted that the resolution limit is not in the printing press. which in the case of offset is
typically adjusted to a resolution of 13
ILm
[17J. but on the digital printer used to produce the films
from which in turn the offset plates are fabricated.
For multicolor printing it is desirable to use only four separations to control printing costs. because
non-opaque quality inks are required. The following colors have yielded good results:
polysilicon: RT6 red metal-I: C28 blue
diffusion: GT4 green
metal-2:
M3512
magenta
XEROX PARe. EDL-88-7. DECEM BER. 1988
10
Selecting Colors for Representing VLSI Layout
Contact cuts and metal vias can be imaged in three of the separations
to
appear black. At the scale
at which line art becomes interesting. the other layers in the CMOS process. such as wells, can be
omitted without hampering readability for a VLSI designer. As an example of the application of line
art, the cover of
Physical design automation of VLSI systems
[I8J
can be examined, which has been
produced with this technique.
4. Conclusions
A methodology for selecting a color palette for rendering VLSI layout has been presented. It is
based on the maximization of layout readability as quantified by the traceability of the interconnect
implementing the circuit's nodes. Selecting discriminable colors, the same palette can be used for
displaying layout on a color video monitor and for plotting it on a hardcopy device. The use of solid
color filling permits one to avoid the empirical process of designing stipple patterns.
In a prototype implementation the corner-stitching algorithm
[19J
has been used to determine the
intersections. While a short but reasonable delay has to be taken into account for the initial creation of
the corner-stitched data structure, painting the screen is slightly faster than with a traditional method.
In total, no significant performance degradation has been observed in painting the screen compared to
traditional methods.
Corner stitching allows an efficient implementation of the region-finding algorithm. The
disadvantage is that it is restricted to Manhattan geometry. The most efficient algorithm for arbitrary
geometry, as it is frequently used in the bipolar technology. is plane sweep
[20J.
When plane sweep is
used for scan-converting polygons, it is trivial to add a border to regions of arbitrary complexity,
because it simply means that a pixel has to be set at the end of each interval when a scan line is
produced
[21. 22J.
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4. Conclusions
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