Integrated VLSI Systems I

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Nov 26, 2013 (3 years and 10 months ago)

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Integrated VLSI Systems I





Laboratory Assignments






Name: ____________________________

Group: _________






Department of Microelectronics and Nanoelectronics
Faculty of ICT



University of Malta
Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

2
Assignment 1: Fundamentals


Figure 1

MOSFET DATA (M1 & M2): L = 0.9 µm W = 20 µm

[1] Determine the D.C. operating points (including V
D
, I
D
, V
G
, V
GS
) for
the two transistors M
1
and M
2
.





















Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

3
[2] Suppose that W is increased by a factor of 2, determine the new
operating points.


















[3] Obtain the magnitude and phase Bode plots using a 1 mV
sinusoidal peak input. Hence identify the –3dB points.






















Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

4
[5] Determine the output waveform for the input square-wave shown
below.



Figure 2

[6] Determine the approximate linear input range for the amplifier.
(Hint: short-circuit C
1
and C
2
and apply a DC sweep to the input).













[7] Determine the total harmonic distortion (T.H.D.) obtained when a
1 mV peak sinusoidal signal of frequency 10 kHz is applied to the input of
the amplifier.














Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

5
[8] Repeat question [7] for an input of 0.1 V peak, and comment on the
result, comparing it with that obtained in [7].









































Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

6
Assignment 2: Operational Amplifiers

The circuit below shows a 2-stage CMOS op-amp with p-channel input
transistors:



Figure 1

Width/Length Parameters: M1: 120µ/8µ M2: 120µ/8µ
M3: 50µ/10µ M4: 50µ/10µ
M5: 150µ/10µ M6: 100µ/10µ
M7: 150µ/10µ M8: 150µ/10µ

[1] Using the voltage-controlled voltage source (VCVS) method shown
below, perform a balanced differential DC sweep on the input. Plot the
op-amp output node voltage, and hence determine the:

(i) linear range
(ii) offset
(iii) open loop gain












Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

7









Figure 2


[2] By applying a differential AC (sinusoidal) input, with appropriate
magnitude chosen such that the op-amp is sure to operate in its linear
range, determine the open loop magnitude and phase response of the
op-amp.

[3] From [2], determine the open loop phase margin and gain margin.
Hence comment on the stability of the op-amp when it is used as a unity
gain non-inverting buffer.












Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

8






[4] Repeat [2] and [3], with the frequency compensation network R–C
C

disconnected. How does this network affect the frequency response and
stability?






































Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

9
[5] Connect the op-amp as an inverting adder as shown in the diagram
below:


Figure 3

Apply a 10 kHz 1mV pk input to node 10 and a 30 kHz 1mV pk input to
node 11. Perform TRANSIENT analysis and hence FOURIER analysis
(using a 10 kHz base frequency) on the output node. Comment on the
Fourier results obtained: does the op-amp show any considerable
MULTIPLICATIVE mixing effect due to non–linearities?

Hint: Recall that:
( )
(
)
(
)
(
)
(
)
(
)
tttt
212121
coscossinsin2 ωωωωωω +−−=

























Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

10
Assignment 3: Applications of Operational Amplifiers

The following circuits use the CMOS op-amp which has been defined as a
sub-circuit in tutorial sheet 2.


Figure 1

[1] Using the arrangement shown in Figure [1] below, determine the
output resistance of the op-amp.
























Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

11
[2] The circuit shown in the figure [2] shows the input part of a 3-bit
A/D flash converter (encoder part missing). By sweeping the input voltage
source, verify the outputs V
D1
to V
D7
.

[3] Figure [3] shows a 4-bit D/A converter utilizing an R-2R ladder
network.

Apply the following pulses voltages in the time domain:
Vd1 14 0 PULSE (5 0 1ns 1ns 0.5ms 1ms)
Vd2 14 0 PULSE (5 0 1ns 1ns 1.0ms 2ms)
Vd3 14 0 PULSE (5 0 1ns 1ns 2.0ms 4ms)
Vd4 14 0 PULSE (5 0 1ns 1ns 4.0ms 8ms)



Plot the input voltages V
d1
to V
d4
together with the output voltage v(1) in
order to verify the DAC operation.

A
n3
n2
n1
B
Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

12


Figure 2




Figure 3


Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

13
Assignment 4: Digital Integrated Circuits

[1] The diagram below shows a 2-input NAND gate implemented using
CMOS technology:

Figure 1

MOSFET DATA:

M1 & M3: L=5µ, W=30µ
M2 & M4: L=5µ, W=15µ


[2] Connect the NAND gate as shown in Figure 2, with C
L
representing
the load capacitance:


Figure 2
Apply a fixed 5V to one input and a d.c. sweep (0 to 5V) to the other input.
Hence obtain a plot of the output waveform. Repeat this test, this time
interchanging the input connections. Hence determine:

(a) The minimum input voltage V
IH
which is interpreted as HIGH
by the NAND gate.
(b) The maximum input voltage V
IL
which is interpreted as LOW by
the NAND gate.





Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

14















[3] Consider the arrangement shown in Figure 3 below:


Figure 3

Apply a PULSE waveform to one of the inputs and thus obtain the load
capacitor voltage and current.

Note: for pulse input:

Va 6 0 PULSE (0V 5V 10ns 10ns 1us 2us)


[4] Consider the 8 to 3 encoder needed by the flash ADC used in
tutorial 3 (Q2). The following partial truth table describes the logic
functions of the encoder:








Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

15
INPUTS OUTPUTS
VD1 VD2 VD3 VD4 VD5 VD6 VD7 Q0 Q1 Q2
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1 0 0
0 0 0 0 0 1 1 0 1 0
0 0 0 0 1 1 1 1 1 0
0 0 0 1 1 1 1 0 0 1
0 0 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 0 1 1
1 1 1 1 1 1 1 1 1 1

Other input combinations are DON’T CARE conditions and may be
ignored. Implement the encoder using 2-input NAND gates (you need not
fully minimise the logic functions involved). Hence define the as a sub-
circuit with external nodes:

VD1, VD2, VD3, VD4, VD5, VD6, VD7, Vdd, Gnd, Q0, Q1 and Q2.



























[5] Add the encoder to the comparator section of the flash ADC. Hence
using the same procedure described in tutorial 3 (Q2), verify the encoded
outputs Q0 to Q3.
Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

16
Assignment 5: Differential Amplifier – Design and
Analysis

[1] For the differential pair shown in Figure [1] deduce that the small
signal differential gain is given by:

( )
1
1
1
1
1
L
IWK
RRVV
L
W
K
V
V
A
P
TGSP
i
o
vd
=−==


where W
1
/L
1
= W
2
/L
2
are the dimensions of M
1
and M
2
. Assume that the
MOSFETS operate in the saturation region and neglect the channel
modulation effects.

Figure 1























Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

17
Hence design the differential pair assuming I = 100 µA and R = 50 kΩ in
order to obtain a differential gain of 50. Also determine the saturation
voltage V
DSsat
of M
1
and M
2
. The MOSFET parameters are given in the
table below:

Parameter N-Channel P-Channel
K
p
(µA/V
2
) 57 17
VTO (V) 1 1
λ (V
-1
) 0.05 0.04
L
mm
(µm) 1 1
C
gdo
(pF/m
2
) 180 280
C
gdo
(pF/m
2
) 180 280

Use simulation in order to determine:

(i) the D.C. operating point
(ii) the frequency response with regards to gain and phase



Figure 2

















Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

18
[2] The current source I is to be replaced by the current mirror shown
in Figure [2]. Calculate the W and L values of the mirror transistors M
3
and M
4
and the value of R
bias
. Assume that the mirror transistors should
operate with a gate overdrive (V
gs
–V
T
) of 0.3 V. Verify the circuit operation
with regards to D.C. bias conditions. How does V
DS4
affect the common-
mode rejection ratio (CMRR) of the differential pair?



































[3] A common-source output stage is to be cascaded after the
differential pair as shown in Figure [3]. The output stage quiescent
current should also be set to 100 µA. Estimate the W and L values of
the output stage transistors. Show that the small signal voltage gain
of the output stage is given by:

Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

19
65
5
2
dsds
m
v
gg
g
A
+
=


Assume that the MOSFETS operate in saturation but take into
account the output a.c. conductance g
ds
.


Figure 3





























Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

20
Starting from the MOSFET equation in saturation:

( )( )
2
1
2
TGSDS
P
D
VVV
L
WK
I −+= λ


deduce an expression for g
ds
and hence determine the theoretical
composite small signal on the above arrangement.








































Department of Microelectronics and Nanoelectronics
Integrated VLSI Systems I
Owen Casha 2008
©

21
[4] Use simulation analysis on the above arrangement in order to
determine:

(i) the D.C. operating point
(ii) the transfer function V
o
versus V
in
(hence also determine
the gain, linear region and d.c. offset).
(iii) Frequency response: Gain and phase.
(iv) Slew rate
(v) Common mode rejection ratio
(vi) Power supply rejection ratio