CMOS VLSI Design

connectionbuttsElectronics - Devices

Nov 26, 2013 (3 years and 6 months ago)

275 views


Fourth Edition

CMOS VLSI Design

A Circuits and Systems Perspective



Fourth Edition

N
e
i
l

H
.

E
.

W
e
s
t
e

M
a
c
q
u
a
r
i
e

U
n
i
v
e
r
s
i
t
y


a
n
d

T
h
e

U
n
i
v
e
r
s
i
t
y

o
f

A
d
e
l
a
i
d
e

D
a
v
i
d

M
o
n
e
y

H
a
r
r
i
s

H
a
r
v
e
y

M
u
d
d

C
o
l
l
e
g
e

CMOS VLSI Design

A Circuits and Systems Perspective
Addison-Wesley
Boston Columbus Indianapolis New York San Francisco Upper Saddle River
Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal Toronto
Delhi Mexico City Sao Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo


E
d
i
t
o
r

i
n

C
h
i
e
f
:


M
i
c
h
a
e
l

H
i
r
s
c
h
A
c
q
u
i
s
i
t
i
o
n
s

E
d
i
t
o
r
:


M
a
t
t

G
o
l
d
s
t
e
i
n
E
d
i
t
o
r
i
a
l

A
s
s
i
s
t
a
n
t
:


C
h
e
l
s
e
a

B
e
l
l
M
a
n
a
g
i
n
g

E
d
i
t
o
r
:


J
e
f
f
r
e
y

H
o
l
c
o
m
b
S
e
n
i
o
r

P
r
o
d
u
c
t
i
o
n

P
r
o
j
e
c
t

M
a
n
a
g
e
r
:


M
a
r
i
l
y
n

L
l
o
y
d
M
e
d
i
a

P
r
o
d
u
c
e
r
:


K
a
t
e
l
y
n

B
o
l
l
e
r
D
i
r
e
c
t
o
r

o
f

M
a
r
k
e
t
i
n
g
:


M
a
r
g
a
r
e
t

W
a
p
l
e
s
M
a
r
k
e
t
i
n
g

C
o
o
r
d
i
n
a
t
o
r
:


K
a
t
h
r
y
n

F
e
r
r
a
n
t
i

S
e
n
i
o
r

M
a
n
u
f
a
c
t
u
r
i
n
g

B
u
y
e
r
:


C
a
r
o
l

M
e
l
v
i
l
l
e
S
e
n
i
o
r

M
e
d
i
a

B
u
y
e
r
:


G
i
n
n
y

M
i
c
h
a
u
d
T
e
x
t

D
e
s
i
g
n
e
r
:


S
u
s
a
n

R
a
y
m
o
n
d
A
r
t

D
i
r
e
c
t
o
r
,

C
o
v
e
r
:


L
i
n
d
a

K
n
o
w
l
e
s
C
o
v
e
r

D
e
s
i
g
n
e
r
:


J
o
y
c
e

C
o
s
e
n
t
i
n
o

W
e
l
l
s
/
J

W
e
l
l
s

D
e
s
i
g
n
C
o
v
e
r

I
m
a
g
e
:


C
o
v
e
r

p
h
o
t
o
g
r
a
p
h

c
o
u
r
t
e
s
y

o
f

N
i
c
k

K
n
u
p
f
f
e
r

I
n
t
e
l

C
o
r
p
o
r
a
t
i
o
n
.

C
o
p
y
r
i
g
h
t

©

2
0
0
9

I
n
t
e
l

C
o
r
p
o
r
a
t
i
o
n
.

A
l
l

r
i
g
h
t
s

r
e
s
e
r
v
e
d
.
F
u
l
l

S
e
r
v
i
c
e

V
e
n
d
o
r
:


G
i
l
l
i
a
n

H
a
l
l
/
T
h
e

A
a
r
d
v
a
r
k

G
r
o
u
p

P
u
b
l
i
s
h
i
n
g

S
e
r
v
i
c
e
C
o
p
y
e
d
i
t
o
r
:


K
a
t
h
l
e
e
n

C
a
n
t
w
e
l
l
,

C
4

T
e
c
h
n
o
l
o
g
i
e
s
P
r
o
o
f
r
e
a
d
e
r
:


H
o
l
l
y

M
c
L
e
a
n
-
A
l
d
i
s
I
n
d
e
x
e
r
:


J
a
c
k

L
e
w
i
s
P
r
i
n
t
e
r
/
B
i
n
d
e
r
:


E
d
w
a
r
d
s

B
r
o
t
h
e
r
s
C
o
v
e
r

P
r
i
n
t
e
r
:


L
e
h
i
g
h
-
P
h
o
e
n
i
x

C
o
l
o
r
/
H
a
g
e
r
s
t
o
w
n
C
r
e
d
i
t
s

a
n
d

a
c
k
n
o
w
l
e
d
g
m
e
n
t
s

b
o
r
r
o
w
e
d

f
r
o
m

o
t
h
e
r

s
o
u
r
c
e
s

a
n
d

r
e
p
r
o
d
u
c
e
d

w
i
t
h

p
e
r
m
i
s
s
i
o
n

i
n

t
h
i
s
t
e
x
t
b
o
o
k

a
p
p
e
a
r

o
n

a
p
p
r
o
p
r
i
a
t
e

p
a
g
e

w
i
t
h
i
n

t
e
x
t

o
r

o
n

p
a
g
e

8
3
8
.
T
h
e

i
n
t
e
r
i
o
r

o
f

t
h
i
s

b
o
o
k

w
a
s

s
e
t

i
n

A
d
o
b
e

C
a
s
l
o
n

a
n
d

T
r
a
d
e

G
o
t
h
i
c
.
C
o
p
y
r
i
g
h
t

©

2
0
1
1
,

2
0
0
5
,

1
9
9
3
,

1
9
8
5

P
e
a
r
s
o
n

E
d
u
c
a
t
i
o
n
,

I
n
c
.
,

p
u
b
l
i
s
h
i
n
g

a
s

A
d
d
i
s
o
n
-
W
e
s
l
e
y
.

A
l
l
r
i
g
h
t
s

r
e
s
e
r
v
e
d
.

M
a
n
u
f
a
c
t
u
r
e
d

i
n

t
h
e

U
n
i
t
e
d

S
t
a
t
e
s

o
f

A
m
e
r
i
c
a
.

T
h
i
s

p
u
b
l
i
c
a
t
i
o
n

i
s

p
r
o
t
e
c
t
e
d

b
y
C
o
p
y
r
i
g
h
t
,

a
n
d

p
e
r
m
i
s
s
i
o
n

s
h
o
u
l
d

b
e

o
b
t
a
i
n
e
d

f
r
o
m

t
h
e

p
u
b
l
i
s
h
e
r

p
r
i
o
r

t
o

a
n
y

p
r
o
h
i
b
i
t
e
d

r
e
p
r
o
d
u
c
-
t
i
o
n
,

s
t
o
r
a
g
e

i
n

a

r
e
t
r
i
e
v
a
l

s
y
s
t
e
m
,

o
r

t
r
a
n
s
m
i
s
s
i
o
n

i
n

a
n
y

f
o
r
m

o
r

b
y

a
n
y

m
e
a
n
s
,

e
l
e
c
t
r
o
n
i
c
,

m
e
c
h
a
n
i
-
c
a
l
,

p
h
o
t
o
c
o
p
y
i
n
g
,

r
e
c
o
r
d
i
n
g
,

o
r

l
i
k
e
w
i
s
e
.

T
o

o
b
t
a
i
n

p
e
r
m
i
s
s
i
o
n
(
s
)

t
o

u
s
e

m
a
t
e
r
i
a
l

f
r
o
m

t
h
i
s

w
o
r
k
,
p
l
e
a
s
e

s
u
b
m
i
t

a

w
r
i
t
t
e
n

r
e
q
u
e
s
t

t
o

P
e
a
r
s
o
n

E
d
u
c
a
t
i
o
n
,

I
n
c
.
,

P
e
r
m
i
s
s
i
o
n
s

D
e
p
a
r
t
m
e
n
t
,

5
0
1

B
o
y
l
s
t
o
n
S
t
r
e
e
t
,

S
u
i
t
e

9
0
0
,

B
o
s
t
o
n
,

M
a
s
s
a
c
h
u
s
e
t
t
s

0
2
1
1
6
.
M
a
n
y

o
f

t
h
e

d
e
s
i
g
n
a
t
i
o
n
s

b
y

m
a
n
u
f
a
c
t
u
r
e
r
s

a
n
d

s
e
l
l
e
r
s

t
o

d
i
s
t
i
n
g
u
i
s
h

t
h
e
i
r

p
r
o
d
u
c
t
s

a
r
e

c
l
a
i
m
e
d

a
s
t
r
a
d
e
m
a
r
k
s
.

W
h
e
r
e

t
h
o
s
e

d
e
s
i
g
n
a
t
i
o
n
s

a
p
p
e
a
r

i
n

t
h
i
s

b
o
o
k
,

a
n
d

t
h
e

p
u
b
l
i
s
h
e
r

w
a
s

a
w
a
r
e

o
f

a

t
r
a
d
e
-
m
a
r
k

c
l
a
i
m
,

t
h
e

d
e
s
i
g
n
a
t
i
o
n
s

h
a
v
e

b
e
e
n

p
r
i
n
t
e
d

i
n

i
n
i
t
i
a
l

c
a
p
s

o
r

a
l
l

c
a
p
s
.
C
a
t
a
l
o
g
i
n
g
-
i
n
-
P
u
b
l
i
c
a
t
i
o
n

D
a
t
a

i
s

o
n


l
e

w
i
t
h

t
h
e

L
i
b
r
a
r
y

o
f

C
o
n
g
r
e
s
s
.

1
0


9


8


7


6


5


4


3


2


1

E
B

1
4

1
3

1
2

1
1

1
0
I
S
B
N

1
0
:

0
-
3
2
1
-
5
4
7
7
4
-
8
I
S
B
N

1
3
:

9
7
8
-
0
-
3
2
1
-
5
4
7
7
4
-
3
Addison-Wesley
is an imprint of


T
o

A
v
r
i
l
,

M
e
l
i
s
s
a
,

T
a
m
a
r
a
,

N
i
c
k
y
,

J
o
c
e
l
y
n
,
M
a
k
a
y
l
a
,

E
m
i
l
y
,

D
a
n
i
k
a
,

D
a
n

a
n
d

S
i
m
o
n

N
.

W
.

T
o

J
e
n
n
i
f
e
r
,

S
a
m
u
e
l
,

a
n
d

A
b
r
a
h
a
m

D
.

M
.

H
.



vii

Preface




x
x
v

Chapter 1

Introduction

1.1

A Brief History


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1

1.2

Preview

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6

1.3

MOS Transistors


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6

1.4

CMOS Logic

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

9

1.4.1

T
h
e

I
n
v
e
r
t
e
r




9

1.4.2

T
h
e

N
A
N
D

G
a
t
e




9

1.4.3

C
M
O
S

L
o
g
i
c

G
a
t
e
s




9

1.4.4

T
h
e

N
O
R

G
a
t
e




1
1

1.4.5

C
o
m
p
o
u
n
d

G
a
t
e
s




1
1

1.4.6


P
a
s
s

T
r
a
n
s
i
s
t
o
r
s

a
n
d

T
r
a
n
s
m
i
s
s
i
o
n

G
a
t
e
s



1
2

1.4.7

T
r
i
s
t
a
t
e
s




1
4

1.4.8


M
u
l
t
i
p
l
e
x
e
r
s




1
5

1.4.9

S
e
q
u
e
n
t
i
a
l

C
i
r
c
u
i
t
s




1
6

1.5

CMOS Fabrication and Layout

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
9

1.5.1

I
n
v
e
r
t
e
r

C
r
o
s
s
-
S
e
c
t
i
o
n




1
9

1.5.2

F
a
b
r
i
c
a
t
i
o
n

P
r
o
c
e
s
s




2
0

1.5.3

L
a
y
o
u
t

D
e
s
i
g
n

R
u
l
e
s




2
4

1.5.4


G
a
t
e

L
a
y
o
u
t
s




2
7

1.5.5


S
t
i
c
k

D
i
a
g
r
a
m
s




2
8

1.6

Design Partitioning



.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
9

1.6.1


D
e
s
i
g
n

A
b
s
t
r
a
c
t
i
o
n
s



3
0

1.6.2


S
t
r
u
c
t
u
r
e
d

D
e
s
i
g
n




3
1

1.6.3


B
e
h
a
v
i
o
r
a
l
,

S
t
r
u
c
t
u
r
a
l
,

a
n
d

P
h
y
s
i
c
a
l

D
o
m
a
i
n
s




3
1

1.7

Example: A Simple MIPS Microprocessor



.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
3

1.7.1

M
I
P
S

A
r
c
h
i
t
e
c
t
u
r
e




3
3

1.7.2

M
u
l
t
i
c
y
c
l
e

M
I
P
S

M
i
c
r
o
a
r
c
h
i
t
e
c
t
u
r
e
s




3
4

1.8

Logic Design


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
8

1.8.1


T
o
p
-
L
e
v
e
l

I
n
t
e
r
f
a
c
e
s



3
8

1.8.2


B
l
o
c
k

D
i
a
g
r
a
m
s




3
8

1.8.3


H
i
e
r
a
r
c
h
y




4
0

1.8.4

H
a
r
d
w
a
r
e

D
e
s
c
r
i
p
t
i
o
n

L
a
n
g
u
a
g
e
s




4
0

1.9

Circuit Design



.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
2

Contents


Contents

viii
1.10

Physical Design


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
5

1.10.1


F
l
o
o
r
p
l
a
n
n
i
n
g




4
5

1.10.2


S
t
a
n
d
a
r
d

C
e
l
l
s




4
8

1.10.3


P
i
t
c
h

M
a
t
c
h
i
n
g




5
0

1.10.4


S
l
i
c
e

P
l
a
n
s




5
0

1.10.5


A
r
r
a
y
s



5
1

1.10.6


A
r
e
a

E
s
t
i
m
a
t
i
o
n



5
1

1.11

Design Verification



.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
3

1.12

Fabrication, Packaging, and Testing

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
4

Summary and a Look Ahead





5
5

Exercises





5
7

Chapter 2

MOS Transistor Theory

2.1

Introduction


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
1

2.2

Long-Channel I-V Characteristics



.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
4

2.3

C-V Characteristics



.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
8

2.3.1


S
i
m
p
l
e

M
O
S

C
a
p
a
c
i
t
a
n
c
e

M
o
d
e
l
s




6
8

2.3.2

D
e
t
a
i
l
e
d

M
O
S

G
a
t
e

C
a
p
a
c
i
t
a
n
c
e

M
o
d
e
l




7
0


2.3.3

D
e
t
a
i
l
e
d

M
O
S

D
i
f
f
u
s
i
o
n

C
a
p
a
c
i
t
a
n
c
e

M
o
d
e
l




7
2

2.4

Nonideal I-V Effects



.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

7
4

2.4.1

M
o
b
i
l
i
t
y

D
e
g
r
a
d
a
t
i
o
n

a
n
d

V
e
l
o
c
i
t
y

S
a
t
u
r
a
t
i
o
n




7
5

2.4.2


C
h
a
n
n
e
l

L
e
n
g
t
h

M
o
d
u
l
a
t
i
o
n



7
8

2.4.3


T
h
r
e
s
h
o
l
d

V
o
l
t
a
g
e

E
f
f
e
c
t
s




7
9

2.4.4

L
e
a
k
a
g
e




8
0

2.4.5


T
e
m
p
e
r
a
t
u
r
e

D
e
p
e
n
d
e
n
c
e




8
5

2.4.6

G
e
o
m
e
t
r
y

D
e
p
e
n
d
e
n
c
e




8
6

2.4.7

S
u
m
m
a
r
y




8
6

2.5

DC Transfer Characteristics



.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

8
7

2.5.1


S
t
a
t
i
c

C
M
O
S

I
n
v
e
r
t
e
r

D
C

C
h
a
r
a
c
t
e
r
i
s
t
i
c
s




8
8

2.5.2

B
e
t
a

R
a
t
i
o

E
f
f
e
c
t
s




9
0

2.5.3


N
o
i
s
e

M
a
r
g
i
n




9
1

2.5.4

P
a
s
s

T
r
a
n
s
i
s
t
o
r

D
C

C
h
a
r
a
c
t
e
r
i
s
t
i
c
s




9
2

2.6

Pitfalls and Fallacies



.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

9
3

Summary

9
4

Exercises





9
5

Chapter 3

CMOS Processing Technology

3.1

Introduction


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

9
9

3.2

CMOS Technologies


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
0
0

3.2.1

W
a
f
e
r

F
o
r
m
a
t
i
o
n




1
0
0
3.2.2
P
h
o
t
o
l
i
t
h
o
g
r
a
p
h
y




1
0
1
Contents
ix
3.2.3

W
e
l
l

a
n
d

C
h
a
n
n
e
l

F
o
r
m
a
t
i
o
n




1
0
3
3.2.4
S
i
l
i
c
o
n

D
i
o
x
i
d
e

(
S
i
O
2
)




1
0
5
3.2.5
I
s
o
l
a
t
i
o
n




1
0
6
3.2.6
G
a
t
e

O
x
i
d
e




1
0
7
3.2.7

G
a
t
e

a
n
d

S
o
u
r
c
e
/
D
r
a
i
n

F
o
r
m
a
t
i
o
n
s




1
0
8
3.2.8

C
o
n
t
a
c
t
s

a
n
d

M
e
t
a
l
l
i
z
a
t
i
o
n




1
1
0
3.2.9

P
a
s
s
i
v
a
t
i
o
n




1
1
2
3.2.10
M
e
t
r
o
l
o
g
y




1
1
2
3.3
Layout Design Rules


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
1
3
3.3.1

D
e
s
i
g
n

R
u
l
e

B
a
c
k
g
r
o
u
n
d




1
1
3
3.3.2

S
c
r
i
b
e

L
i
n
e

a
n
d

O
t
h
e
r

S
t
r
u
c
t
u
r
e
s




1
1
6
3.3.3
M
O
S
I
S

S
c
a
l
a
b
l
e

C
M
O
S

D
e
s
i
g
n

R
u
l
e
s




1
1
7
3.3.4
M
i
c
r
o
n

D
e
s
i
g
n

R
u
l
e
s




1
1
8
3.4
CMOS Process Enhancements

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
1
9
3.4.1
T
r
a
n
s
i
s
t
o
r
s




1
1
9
3.4.2

I
n
t
e
r
c
o
n
n
e
c
t




1
2
2
3.4.3
C
i
r
c
u
i
t

E
l
e
m
e
n
t
s




1
2
4
3.4.4
B
e
y
o
n
d

C
o
n
v
e
n
t
i
o
n
a
l

C
M
O
S




1
2
9
3.5
Technology-Related CAD Issues

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
3
0
3.5.1
D
e
s
i
g
n

R
u
l
e

C
h
e
c
k
i
n
g

(
D
R
C
)




1
3
1
3.5.2
C
i
r
c
u
i
t

E
x
t
r
a
c
t
i
o
n





1
3
2
3.6
Manufacturing Issues


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
3
3
3.6.1
A
n
t
e
n
n
a

R
u
l
e
s




1
3
3
3.6.2
L
a
y
e
r

D
e
n
s
i
t
y

R
u
l
e
s




1
3
4
3.6.3
R
e
s
o
l
u
t
i
o
n

E
n
h
a
n
c
e
m
e
n
t

R
u
l
e
s



1
3
4
3.6.4
M
e
t
a
l

S
l
o
t
t
i
n
g

R
u
l
e
s



1
3
5
3.6.5

Y
i
e
l
d

E
n
h
a
n
c
e
m
e
n
t

G
u
i
d
e
l
i
n
e
s



1
3
5
3.7
Pitfalls and Fallacies



.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
3
6
3.8
Historical Perspective

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
3
7
Summary

1
3
9
Exercises

1
3
9
Chapter 4
Delay
4.1
Introduction


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
4
1
4.1.1

D
e

n
i
t
i
o
n
s




1
4
1
4.1.2

T
i
m
i
n
g

O
p
t
i
m
i
z
a
t
i
o
n




1
4
2
4.2
Transient Response

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
4
3
4.3
RC Delay Model

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
4
6
4.3.1
E
f
f
e
c
t
i
v
e

R
e
s
i
s
t
a
n
c
e




1
4
6
4.3.2

G
a
t
e

a
n
d

D
i
f
f
u
s
i
o
n

C
a
p
a
c
i
t
a
n
c
e




1
4
7
4.3.3
E
q
u
i
v
a
l
e
n
t

R
C

C
i
r
c
u
i
t
s




1
4
7
4.3.4
T
r
a
n
s
i
e
n
t

R
e
s
p
o
n
s
e




1
4
8
4.3.5

E
l
m
o
r
e

D
e
l
a
y




1
5
0
Contents
x
4.3.6

L
a
y
o
u
t

D
e
p
e
n
d
e
n
c
e

o
f

C
a
p
a
c
i
t
a
n
c
e




1
5
3
4.3.7
D
e
t
e
r
m
i
n
i
n
g

E
f
f
e
c
t
i
v
e

R
e
s
i
s
t
a
n
c
e




1
5
4
4.4
Linear Delay Model

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
5
5
4.4.1
L
o
g
i
c
a
l

E
f
f
o
r
t




1
5
6
4.4.2
P
a
r
a
s
i
t
i
c

D
e
l
a
y




1
5
6
4.4.3
D
e
l
a
y

i
n

a

L
o
g
i
c

G
a
t
e




1
5
8
4.4.4
D
r
i
v
e




1
5
9
4.4.5
E
x
t
r
a
c
t
i
n
g

L
o
g
i
c
a
l

E
f
f
o
r
t

f
r
o
m

D
a
t
a
s
h
e
e
t
s



1
5
9
4.4.6
L
i
m
i
t
a
t
i
o
n
s

t
o

t
h
e

L
i
n
e
a
r

D
e
l
a
y

M
o
d
e
l



1
6
0
4.5
Logical Effort of Paths


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
6
3
4.5.1
D
e
l
a
y

i
n

M
u
l
t
i
s
t
a
g
e

L
o
g
i
c

N
e
t
w
o
r
k
s




1
6
3
4.5.2

C
h
o
o
s
i
n
g

t
h
e

B
e
s
t

N
u
m
b
e
r

o
f

S
t
a
g
e
s




1
6
6
4.5.3

E
x
a
m
p
l
e




1
6
8
4.5.4

S
u
m
m
a
r
y

a
n
d

O
b
s
e
r
v
a
t
i
o
n
s




1
6
9
4.5.5

L
i
m
i
t
a
t
i
o
n
s

o
f

L
o
g
i
c
a
l

E
f
f
o
r
t




1
7
1
4.5.6

I
t
e
r
a
t
i
v
e

S
o
l
u
t
i
o
n
s

f
o
r

S
i
z
i
n
g




1
7
1
4.6
Timing Analysis Delay Models

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
7
3
4.6.1

S
l
o
p
e
-
B
a
s
e
d

L
i
n
e
a
r

M
o
d
e
l



1
7
3
4.6.2

N
o
n
l
i
n
e
a
r

D
e
l
a
y

M
o
d
e
l




1
7
4
4.6.3
C
u
r
r
e
n
t

S
o
u
r
c
e

M
o
d
e
l




1
7
4
4.7
Pitfalls and Fallacies

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
7
4
4.8
Historical Perspective

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
7
5
Summary

1
7
6
Exercises

1
7
6
Chapter 5
Power
5.1
Introduction

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
8
1
5.1.1

D
e

n
i
t
i
o
n
s




1
8
2
5.1.2
E
x
a
m
p
l
e
s




1
8
2
5.1.3
S
o
u
r
c
e
s

o
f

P
o
w
e
r

D
i
s
s
i
p
a
t
i
o
n




1
8
4
5.2
Dynamic Power


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
8
5
5.2.1

A
c
t
i
v
i
t
y

F
a
c
t
o
r




1
8
6
5.2.2
C
a
p
a
c
i
t
a
n
c
e




1
8
8
5.2.3

V
o
l
t
a
g
e




1
9
0
5.2.4
F
r
e
q
u
e
n
c
y




1
9
2
5.2.5
S
h
o
r
t
-
C
i
r
c
u
i
t

C
u
r
r
e
n
t




1
9
3
5.2.6
R
e
s
o
n
a
n
t

C
i
r
c
u
i
t
s




1
9
3
5.3
Static Power

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1
9
4
5.3.1

S
t
a
t
i
c

P
o
w
e
r

S
o
u
r
c
e
s




1
9
4
5.3.2
P
o
w
e
r

G
a
t
i
n
g




1
9
7
5.3.3

M
u
l
t
i
p
l
e

T
h
r
e
s
h
o
l
d

V
o
l
t
a
g
e
s

a
n
d

O
x
i
d
e

T
h
i
c
k
n
e
s
s
e
s




1
9
9
Contents
xi
5.3.4
V
a
r
i
a
b
l
e

T
h
r
e
s
h
o
l
d

V
o
l
t
a
g
e
s




1
9
9
5.3.5
I
n
p
u
t

V
e
c
t
o
r

C
o
n
t
r
o
l



2
0
0
5.4
Energy-Delay Optimization

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
0
0
5.4.1
M
i
n
i
m
u
m

E
n
e
r
g
y




2
0
0
5.4.2
M
i
n
i
m
u
m

E
n
e
r
g
y
-
D
e
l
a
y

P
r
o
d
u
c
t




2
0
3
5.4.3
M
i
n
i
m
u
m

E
n
e
r
g
y

U
n
d
e
r

a

D
e
l
a
y

C
o
n
s
t
r
a
i
n
t




2
0
3
5.5
Low Power Architectures


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
0
4
5.5.1
M
i
c
r
o
a
r
c
h
i
t
e
c
t
u
r
e




2
0
4
5.5.2
P
a
r
a
l
l
e
l
i
s
m

a
n
d

P
i
p
e
l
i
n
i
n
g




2
0
4
5.5.3
P
o
w
e
r

M
a
n
a
g
e
m
e
n
t

M
o
d
e
s




2
0
5
5.6
Pitfalls and Fallacies

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
0
6
5.7
Historical Perspective

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
0
7
Summary

2
0
9
Exercises


2
0
9
Chapter 6
Interconnect
6.1
Introduction


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
1
1
6.1.1

W
i
r
e

G
e
o
m
e
t
r
y




2
1
1
6.1.2

E
x
a
m
p
l
e
:

I
n
t
e
l

M
e
t
a
l

S
t
a
c
k
s




2
1
2
6.2
Interconnect Modeling

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
1
3
6.2.1
R
e
s
i
s
t
a
n
c
e




2
1
4
6.2.2
C
a
p
a
c
i
t
a
n
c
e




2
1
5
6.2.3
I
n
d
u
c
t
a
n
c
e




2
1
8
6.2.4
S
k
i
n

E
f
f
e
c
t




2
1
9
6.2.5
T
e
m
p
e
r
a
t
u
r
e

D
e
p
e
n
d
e
n
c
e




2
2
0
6.3
Interconnect Impact
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
2
0
6.3.1

D
e
l
a
y




2
2
0
6.3.2

E
n
e
r
g
y




2
2
2
6.3.3
C
r
o
s
s
t
a
l
k




2
2
2
6.3.4
I
n
d
u
c
t
i
v
e

E
f
f
e
c
t
s




2
2
4
6.3.5
A
n

A
s
i
d
e

o
n

E
f
f
e
c
t
i
v
e

R
e
s
i
s
t
a
n
c
e

a
n
d

E
l
m
o
r
e

D
e
l
a
y



2
2
7
6.4
Interconnect Engineering

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
2
9
6.4.1
W
i
d
t
h
,

S
p
a
c
i
n
g
,

a
n
d

L
a
y
e
r




2
2
9
6.4.2
R
e
p
e
a
t
e
r
s




2
3
0
6.4.3
C
r
o
s
s
t
a
l
k

C
o
n
t
r
o
l




2
3
2
6.4.4
L
o
w
-
S
w
i
n
g

S
i
g
n
a
l
i
n
g




2
3
4
6.4.5
R
e
g
e
n
e
r
a
t
o
r
s




2
3
6
6.5
Logical Effort with Wires


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
3
6
6.6
Pitfalls and Fallacies

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
3
7
Summary


2
3
8
Exercises

2
3
8
Contents
xii
Chapter 7
Robustness
7.1
Introduction

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
4
1
7.2
Variability

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
4
1
7.2.1

S
u
p
p
l
y

V
o
l
t
a
g
e




2
4
2
7.2.2

T
e
m
p
e
r
a
t
u
r
e




2
4
2
7.2.3

P
r
o
c
e
s
s

V
a
r
i
a
t
i
o
n




2
4
3
7.2.4

D
e
s
i
g
n

C
o
r
n
e
r
s




2
4
4
7.3
Reliability

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
4
6
7.3.1

R
e
l
i
a
b
i
l
i
t
y

T
e
r
m
i
n
o
l
o
g
y




2
4
6
7.3.2

O
x
i
d
e

W
e
a
r
o
u
t




2
4
7
7.3.3

I
n
t
e
r
c
o
n
n
e
c
t

W
e
a
r
o
u
t




2
4
9
7.3.4

S
o
f
t

E
r
r
o
r
s




2
5
1
7.3.5

O
v
e
r
v
o
l
t
a
g
e

F
a
i
l
u
r
e




2
5
2
7.3.6

L
a
t
c
h
u
p




2
5
3
7.4
Scaling

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
5
4
7.4.1

T
r
a
n
s
i
s
t
o
r

S
c
a
l
i
n
g




2
5
5
7.4.2

I
n
t
e
r
c
o
n
n
e
c
t

S
c
a
l
i
n
g




2
5
7
7.4.3

I
n
t
e
r
n
a
t
i
o
n
a
l

T
e
c
h
n
o
l
o
g
y

R
o
a
d
m
a
p

f
o
r

S
e
m
i
c
o
n
d
u
c
t
o
r
s




2
5
8
7.4.4

I
m
p
a
c
t
s

o
n

D
e
s
i
g
n




2
5
9
7.5
Statistical Analysis of Variability

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
6
3
7.5.1

P
r
o
p
e
r
t
i
e
s

o
f

R
a
n
d
o
m

V
a
r
i
a
b
l
e
s




2
6
3
7.5.2

V
a
r
i
a
t
i
o
n

S
o
u
r
c
e
s




2
6
6
7.5.3

V
a
r
i
a
t
i
o
n

I
m
p
a
c
t
s




2
6
9
7.6
Variation-Tolerant Design

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
7
4
7.6.1

A
d
a
p
t
i
v
e

C
o
n
t
r
o
l




2
7
5
7.6.2

F
a
u
l
t

T
o
l
e
r
a
n
c
e




2
7
5
7.7
Pitfalls and Fallacies


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
7
7
7.8
Historical Perspective

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
7
8
Summary

2
8
4
Exercises
2
8
4
Chapter 8
Circuit Simulation
8.1
Introduction

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
8
7
8.2
A SPICE Tutorial


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
8
8
8.2.1

S
o
u
r
c
e
s

a
n
d

P
a
s
s
i
v
e

C
o
m
p
o
n
e
n
t
s




2
8
8
8.2.2

T
r
a
n
s
i
s
t
o
r

D
C

A
n
a
l
y
s
i
s




2
9
2
8.2.3

I
n
v
e
r
t
e
r

T
r
a
n
s
i
e
n
t

A
n
a
l
y
s
i
s




2
9
2
8.2.4

S
u
b
c
i
r
c
u
i
t
s

a
n
d

M
e
a
s
u
r
e
m
e
n
t




2
9
4
8.2.5

O
p
t
i
m
i
z
a
t
i
o
n




2
9
6
8.2.6

O
t
h
e
r

H
S
P
I
C
E

C
o
m
m
a
n
d
s




2
9
8
Contents
xiii
8.3
Device Models


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2
9
8
8.3.1

L
e
v
e
l

1

M
o
d
e
l
s




2
9
9
8.3.2

L
e
v
e
l

2

a
n
d

3

M
o
d
e
l
s




3
0
0
8.3.3

B
S
I
M

M
o
d
e
l
s




3
0
0
8.3.4

D
i
f
f
u
s
i
o
n

C
a
p
a
c
i
t
a
n
c
e

M
o
d
e
l
s




3
0
0
8.3.5

D
e
s
i
g
n

C
o
r
n
e
r
s




3
0
2
8.4
Device Characterization


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
0
3
8.4.1

I
-
V

C
h
a
r
a
c
t
e
r
i
s
t
i
c
s




3
0
3
8.4.2

T
h
r
e
s
h
o
l
d

V
o
l
t
a
g
e




3
0
6
8.4.3

G
a
t
e

C
a
p
a
c
i
t
a
n
c
e




3
0
8
8.4.4

P
a
r
a
s
i
t
i
c

C
a
p
a
c
i
t
a
n
c
e




3
0
8
8.4.5

E
f
f
e
c
t
i
v
e

R
e
s
i
s
t
a
n
c
e




3
1
0
8.4.6

C
o
m
p
a
r
i
s
o
n

o
f

P
r
o
c
e
s
s
e
s




3
1
1
8.4.7

P
r
o
c
e
s
s

a
n
d

E
n
v
i
r
o
n
m
e
n
t
a
l

S
e
n
s
i
t
i
v
i
t
y




3
1
3
8.5
Circuit Characterization


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
1
3
8.5.1

P
a
t
h

S
i
m
u
l
a
t
i
o
n
s




3
1
3
8.5.2

D
C

T
r
a
n
s
f
e
r

C
h
a
r
a
c
t
e
r
i
s
t
i
c
s




3
1
5
8.5.3

L
o
g
i
c
a
l

E
f
f
o
r
t




3
1
5
8.5.4

P
o
w
e
r

a
n
d

E
n
e
r
g
y




3
1
8
8.5.5

S
i
m
u
l
a
t
i
n
g

M
i
s
m
a
t
c
h
e
s




3
1
9
8.5.6

M
o
n
t
e

C
a
r
l
o

S
i
m
u
l
a
t
i
o
n




3
1
9
8.6
Interconnect Simulation

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
1
9
8.7
Pitfalls and Fallacies

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
2
2
Summary

3
2
4
Exercises
3
2
4
Chapter 9
Combinational Circuit Design
9.1
Introduction


.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
2
7
9.2
Circuit Families
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
2
8
9.2.1

S
t
a
t
i
c

C
M
O
S




3
2
9
9.2.2

R
a
t
i
o
e
d

C
i
r
c
u
i
t
s




3
3
4
9.2.3

C
a
s
c
o
d
e

V
o
l
t
a
g
e

S
w
i
t
c
h

L
o
g
i
c




3
3
9
9.2.4

D
y
n
a
m
i
c

C
i
r
c
u
i
t
s




3
3
9
9.2.5

P
a
s
s
-
T
r
a
n
s
i
s
t
o
r

C
i
r
c
u
i
t
s




3
4
9
9.3
Circuit Pitfalls

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
5
4
9.3.1

T
h
r
e
s
h
o
l
d

D
r
o
p
s



3
5
5
9.3.2

R
a
t
i
o

F
a
i
l
u
r
e
s




3
5
5
9.3.3

L
e
a
k
a
g
e




3
5
6
9.3.4

C
h
a
r
g
e

S
h
a
r
i
n
g




3
5
6
9.3.5

P
o
w
e
r

S
u
p
p
l
y

N
o
i
s
e




3
5
6
9.3.6

H
o
t

S
p
o
t
s




3
5
7
Contents
xiv
9.3.7

M
i
n
o
r
i
t
y

C
a
r
r
i
e
r

I
n
j
e
c
t
i
o
n




3
5
7
9.3.8

B
a
c
k
-
G
a
t
e

C
o
u
p
l
i
n
g




3
5
8
9.3.9

D
i
f
f
u
s
i
o
n

I
n
p
u
t

N
o
i
s
e

S
e
n
s
i
t
i
v
i
t
y




3
5
8
9.3.10

P
r
o
c
e
s
s

S
e
n
s
i
t
i
v
i
t
y




3
5
8
9.3.11

E
x
a
m
p
l
e
:

D
o
m
i
n
o

N
o
i
s
e

B
u
d
g
e
t
s




3
5
9
9.4
More Circuit Families
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
6
0
9.5
Silicon-On-Insulator Circuit Design

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
6
0
9.5.1

F
l
o
a
t
i
n
g

B
o
d
y

V
o
l
t
a
g
e




3
6
1
9.5.2

S
O
I

A
d
v
a
n
t
a
g
e
s




3
6
2
9.5.3

S
O
I

D
i
s
a
d
v
a
n
t
a
g
e
s




3
6
2
9.5.4

I
m
p
l
i
c
a
t
i
o
n
s

f
o
r

C
i
r
c
u
i
t

S
t
y
l
e
s




3
6
3
9.5.5

S
u
m
m
a
r
y




3
6
4
9.6
Subthreshold Circuit Design

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
6
4
9.6.1

S
i
z
i
n
g




3
6
5
9.6.2

G
a
t
e

S
e
l
e
c
t
i
o
n




3
6
5
9.7
Pitfalls and Fallacies

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
6
6
9.8
Historical Perspective
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
6
7
Summary


3
6
9
Exercises


3
7
0
Chapter 10
Sequential Circuit Design
10.1
Introduction

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
7
5
10.2
Sequencing Static Circuits
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
7
6
10.2.1

S
e
q
u
e
n
c
i
n
g

M
e
t
h
o
d
s




3
7
6
10.2.2

M
a
x
-
D
e
l
a
y

C
o
n
s
t
r
a
i
n
t
s




3
7
9
10.2.3

M
i
n
-
D
e
l
a
y

C
o
n
s
t
r
a
i
n
t
s




3
8
3
10.2.4

T
i
m
e

B
o
r
r
o
w
i
n
g




3
8
6
10.2.5

C
l
o
c
k

S
k
e
w




3
8
9
10.3
Circuit Design of Latches and Flip-Flops
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3
9
1
10.3.1

C
o
n
v
e
n
t
i
o
n
a
l

C
M
O
S

L
a
t
c
h
e
s




3
9
2
10.3.2

C
o
n
v
e
n
t
i
o
n
a
l

C
M
O
S

F
l
i
p
-
F
l
o
p
s




3
9
3
10.3.3

P
u
l
s
e
d

L
a
t
c
h
e
s




3
9
5
10.3.4

R
e
s
e
t
t
a
b
l
e

L
a
t
c
h
e
s

a
n
d

F
l
i
p
-
F
l
o
p
s




3
9
6
10.3.5

E
n
a
b
l
e
d

L
a
t
c
h
e
s

a
n
d

F
l
i
p
-
F
l
o
p
s




3
9
7
10.3.6

I
n
c
o
r
p
o
r
a
t
i
n
g

L
o
g
i
c

i
n
t
o

L
a
t
c
h
e
s




3
9
8
10.3.7

K
l
a
s
s

S
e
m
i
d
y
n
a
m
i
c

F
l
i
p
-
F
l
o
p

(
S
D
F
F
)




3
9
9
10.3.8

D
i
f
f
e
r
e
n
t
i
a
l

F
l
i
p
-
F
l
o
p
s




3
9
9
10.3.9

D
u
a
l

E
d
g
e
-
T
r
i
g
g
e
r
e
d

F
l
i
p
-
F
l
o
p
s




4
0
0
10.3.10

R
a
d
i
a
t
i
o
n
-
H
a
r
d
e
n
e
d

F
l
i
p
-
F
l
o
p
s




4
0
1
10.3.11

T
r
u
e

S
i
n
g
l
e
-
P
h
a
s
e
-
C
l
o
c
k

(
T
S
P
C
)

L
a
t
c
h
e
s

a
n
d

F
l
i
p
-
F
l
o
p
s




4
0
2
10.4
Static Sequencing Element Methodology
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
0
2
10.4.1

C
h
o
i
c
e

o
f

E
l
e
m
e
n
t
s




4
0
3
10.4.2

C
h
a
r
a
c
t
e
r
i
z
i
n
g

S
e
q
u
e
n
c
i
n
g

E
l
e
m
e
n
t

D
e
l
a
y
s




4
0
5
WEB
ENHANCED
WEB
ENHANCED
Contents
xv
10.4.3

S
t
a
t
e

R
e
t
e
n
t
i
o
n

R
e
g
i
s
t
e
r
s




4
0
8
10.4.4

L
e
v
e
l
-
C
o
n
v
e
r
t
e
r

F
l
i
p
-
F
l
o
p
s



4
0
8
10.4.5

D
e
s
i
g
n

M
a
r
g
i
n

a
n
d

A
d
a
p
t
i
v
e

S
e
q
u
e
n
t
i
a
l

E
l
e
m
e
n
t
s




4
0
9
10.4.6

T
w
o
-
P
h
a
s
e

T
i
m
i
n
g

T
y
p
e
s



4
1
1
10.5
Sequencing Dynamic Circuits

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
1
1
10.6
Synchronizers

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
1
1
10.6.1

M
e
t
a
s
t
a
b
i
l
i
t
y



4
1
2
10.6.2

A

S
i
m
p
l
e

S
y
n
c
h
r
o
n
i
z
e
r



4
1
5
10.6.3

C
o
m
m
u
n
i
c
a
t
i
n
g

B
e
t
w
e
e
n

A
s
y
n
c
h
r
o
n
o
u
s

C
l
o
c
k

D
o
m
a
i
n
s



4
1
6
10.6.4

C
o
m
m
o
n

S
y
n
c
h
r
o
n
i
z
e
r

M
i
s
t
a
k
e
s



4
1
7
10.6.5

A
r
b
i
t
e
r
s



4
1
9
10.6.6

D
e
g
r
e
e
s

o
f

S
y
n
c
h
r
o
n
y



4
1
9
10.7
Wave Pipelining
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
2
0
10.8
Pitfalls and Fallacies

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
2
2
10.9
Case Study: Pentium 4 and Itanium 2 Sequencing Methodologies


.

.

.

.

.

4
2
3
Summary

4
2
3
Exercises

4
2
5
Chapter 11
Datapath Subsystems
11.1
Introduction
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
2
9
11.2
Addition/Subtraction
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
2
9
11.2.1

S
i
n
g
l
e
-
B
i
t

A
d
d
i
t
i
o
n




4
3
0
11.2.2

C
a
r
r
y
-
P
r
o
p
a
g
a
t
e

A
d
d
i
t
i
o
n




4
3
4
11.2.3

S
u
b
t
r
a
c
t
i
o
n




4
5
8
11.2.4

M
u
l
t
i
p
l
e
-
I
n
p
u
t

A
d
d
i
t
i
o
n




4
5
8
11.2.5

F
l
a
g
g
e
d

P
r
e

x

A
d
d
e
r
s




4
5
9
11.3
One/Zero Detectors

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
6
1
11.4
Comparators
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
6
2
11.4.1

M
a
g
n
i
t
u
d
e

C
o
m
p
a
r
a
t
o
r




4
6
2
11.4.2

E
q
u
a
l
i
t
y

C
o
m
p
a
r
a
t
o
r




4
6
2
11.4.3

K

=

A

+

B

C
o
m
p
a
r
a
t
o
r




4
6
3
11.5
Counters
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
6
3
11.5.1

B
i
n
a
r
y

C
o
u
n
t
e
r
s




4
6
4
11.5.2

F
a
s
t

B
i
n
a
r
y

C
o
u
n
t
e
r
s




4
6
5
11.5.3

R
i
n
g

a
n
d

J
o
h
n
s
o
n

C
o
u
n
t
e
r
s




4
6
6
11.5.4

L
i
n
e
a
r
-
F
e
e
d
b
a
c
k

S
h
i
f
t

R
e
g
i
s
t
e
r
s




4
6
6
11.6
Boolean Logical Operations
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
6
8
11.7
Coding

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
6
8
11.7.1

P
a
r
i
t
y




4
6
8
11.7.2

E
r
r
o
r
-
C
o
r
r
e
c
t
i
n
g

C
o
d
e
s




4
6
8
11.7.3

G
r
a
y

C
o
d
e
s




4
7
0
11.7.4

X
O
R
/
X
N
O
R

C
i
r
c
u
i
t

F
o
r
m
s




4
7
1
WEB
ENHANCED
WEB
ENHANCED
WEB
ENHANCED
Contents
xvi
11.8
Shifters
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
7
2
11.8.1

F
u
n
n
e
l

S
h
i
f
t
e
r




4
7
3
11.8.2

B
a
r
r
e
l

S
h
i
f
t
e
r




4
7
5
11.8.3

A
l
t
e
r
n
a
t
i
v
e

S
h
i
f
t

F
u
n
c
t
i
o
n
s




4
7
6
11.9
Multiplication

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
7
6
11.9.1

U
n
s
i
g
n
e
d

A
r
r
a
y

M
u
l
t
i
p
l
i
c
a
t
i
o
n




4
7
8
11.9.2

T
w
o

s

C
o
m
p
l
e
m
e
n
t

A
r
r
a
y

M
u
l
t
i
p
l
i
c
a
t
i
o
n




4
7
9
11.9.3

B
o
o
t
h

E
n
c
o
d
i
n
g




4
8
0
11.9.4

C
o
l
u
m
n

A
d
d
i
t
i
o
n




4
8
5
11.9.5

F
i
n
a
l

A
d
d
i
t
i
o
n




4
8
9
11.9.6

F
u
s
e
d

M
u
l
t
i
p
l
y
-
A
d
d




4
9
0
11.9.7

S
e
r
i
a
l

M
u
l
t
i
p
l
i
c
a
t
i
o
n




4
9
0
11.9.8

S
u
m
m
a
r
y




4
9
0
11.10
Parallel-Prefix Computations
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
9
1
11.11
Pitfalls and Fallacies

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
9
3
Summary
4
9
4
Exercises
4
9
4
Chapter 12
Array Subsystems
12.1
Introduction
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
9
7
12.2
SRAM
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

4
9
8
12.2.1

S
R
A
M

C
e
l
l
s




4
9
9
12.2.2

R
o
w

C
i
r
c
u
i
t
r
y




5
0
6
12.2.3

C
o
l
u
m
n

C
i
r
c
u
i
t
r
y




5
1
0
12.2.4

M
u
l
t
i
-
P
o
r
t
e
d

S
R
A
M

a
n
d

R
e
g
i
s
t
e
r

F
i
l
e
s




5
1
4
12.2.5

L
a
r
g
e

S
R
A
M
s




5
1
5
12.2.6

L
o
w
-
P
o
w
e
r

S
R
A
M
s




5
1
7
12.2.7

A
r
e
a
,

D
e
l
a
y
,

a
n
d

P
o
w
e
r

o
f

R
A
M
s

a
n
d

R
e
g
i
s
t
e
r

F
i
l
e
s




5
2
0
12.3
DRAM
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
2
2
12.3.1

S
u
b
a
r
r
a
y

A
r
c
h
i
t
e
c
t
u
r
e
s




5
2
3
12.3.2

C
o
l
u
m
n

C
i
r
c
u
i
t
r
y




5
2
5
12.3.3

E
m
b
e
d
d
e
d

D
R
A
M




5
2
6
12.4
Read-Only Memory
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
2
7
12.4.1

P
r
o
g
r
a
m
m
a
b
l
e

R
O
M
s




5
2
9
12.4.2

N
A
N
D

R
O
M
s




5
3
0
12.4.3

F
l
a
s
h




5
3
1
12.5
Serial Access Memories
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
3
3
12.5.1

S
h
i
f
t

R
e
g
i
s
t
e
r
s




5
3
3
12.5.2

Q
u
e
u
e
s

(
F
I
F
O
,

L
I
F
O
)




5
3
3
12.6
Content-Addressable Memory

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
3
5
12.7
Programmable Logic Arrays
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
3
7
WEB
ENHANCED
Contents
xvii
12.8
Robust Memory Design
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
4
1
12.8.1

R
e
d
u
n
d
a
n
c
y




5
4
1
12.8.2

E
r
r
o
r

C
o
r
r
e
c
t
i
n
g

C
o
d
e
s

(
E
C
C
)




5
4
3
12.8.3

R
a
d
i
a
t
i
o
n

H
a
r
d
e
n
i
n
g




5
4
3
12.9
Historical Perspective
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
4
4
Summary

5
4
5
Exercises


5
4
6
Chapter 13
Special-Purpose Subsystems
13.1
Introduction
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
4
9
13.2
Packaging and Cooling
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
4
9
13.2.1

P
a
c
k
a
g
e

O
p
t
i
o
n
s




5
4
9
13.2.2

C
h
i
p
-
t
o
-
P
a
c
k
a
g
e

C
o
n
n
e
c
t
i
o
n
s




5
5
1
13.2.3

P
a
c
k
a
g
e

P
a
r
a
s
i
t
i
c
s




5
5
2
13.2.4

H
e
a
t

D
i
s
s
i
p
a
t
i
o
n




5
5
2
13.2.5

T
e
m
p
e
r
a
t
u
r
e

S
e
n
s
o
r
s




5
5
3
13.3
Power Distribution
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
5
5
13.3.1

O
n
-
C
h
i
p

P
o
w
e
r

D
i
s
t
r
i
b
u
t
i
o
n

N
e
t
w
o
r
k




5
5
6
13.3.2

I
R

D
r
o
p
s




5
5
7
13.3.3

L

d
i
/
d
t

N
o
i
s
e




5
5
8
13.3.4

O
n
-
C
h
i
p

B
y
p
a
s
s

C
a
p
a
c
i
t
a
n
c
e




5
5
9
13.3.5

P
o
w
e
r

N
e
t
w
o
r
k

M
o
d
e
l
i
n
g




5
6
0
13.3.6

P
o
w
e
r

S
u
p
p
l
y

F
i
l
t
e
r
i
n
g




5
6
4
13.3.7

C
h
a
r
g
e

P
u
m
p
s




5
6
4
13.3.8

S
u
b
s
t
r
a
t
e

N
o
i
s
e



5
6
5
13.3.9

E
n
e
r
g
y

S
c
a
v
e
n
g
i
n
g




5
6
5
13.4
Clocks
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
6
6
13.4.1

D
e

n
i
t
i
o
n
s




5
6
6
13.4.2

C
l
o
c
k

S
y
s
t
e
m

A
r
c
h
i
t
e
c
t
u
r
e




5
6
8
13.4.3

G
l
o
b
a
l

C
l
o
c
k

G
e
n
e
r
a
t
i
o
n




5
6
9
13.4.4

G
l
o
b
a
l

C
l
o
c
k

D
i
s
t
r
i
b
u
t
i
o
n




5
7
1
13.4.5

L
o
c
a
l

C
l
o
c
k

G
a
t
e
r
s




5
7
5
13.4.6

C
l
o
c
k

S
k
e
w

B
u
d
g
e
t
s




5
7
7
13.4.7

A
d
a
p
t
i
v
e

D
e
s
k
e
w
i
n
g




5
7
9
13.5
PLLs and DLLs

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
8
0
13.5.1

P
L
L
s




5
8
0
13.5.2

D
L
L
s



5
8
7
13.5.3

P
i
t
f
a
l
l
s



5
8
9
13.6
I/0
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
9
0
13.6.1

B
a
s
i
c

I
/
O

P
a
d

C
i
r
c
u
i
t
s




5
9
1
13.6.2

E
l
e
c
t
r
o
s
t
a
t
i
c

D
i
s
c
h
a
r
g
e

P
r
o
t
e
c
t
i
o
n



5
9
3
13.6.3

E
x
a
m
p
l
e
:

M
O
S
I
S

I
/
O

P
a
d
s



5
9
4
13.6.4

M
i
x
e
d
-
V
o
l
t
a
g
e

I
/
O



5
9
6
Contents
xviii
13.7
High-Speed Links
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

5
9
7
13.7.1

H
i
g
h
-
S
p
e
e
d

I
/
O

C
h
a
n
n
e
l
s




5
9
7
13.7.2

C
h
a
n
n
e
l

N
o
i
s
e

a
n
d

I
n
t
e
r
f
e
r
e
n
c
e



6
0
0
13.7.3

H
i
g
h
-
S
p
e
e
d

T
r
a
n
s
m
i
t
t
e
r
s

a
n
d

R
e
c
e
i
v
e
r
s



6
0
1
13.7.4

S
y
n
c
h
r
o
n
o
u
s

D
a
t
a

T
r
a
n
s
m
i
s
s
i
o
n



6
0
6
13.7.5

C
l
o
c
k

R
e
c
o
v
e
r
y

i
n

S
o
u
r
c
e
-
S
y
n
c
h
r
o
n
o
u
s

S
y
s
t
e
m
s



6
0
6
13.7.6

C
l
o
c
k

R
e
c
o
v
e
r
y

i
n

M
e
s
o
c
h
r
o
n
o
u
s

S
y
s
t
e
m
s



6
0
8
13.7.7

C
l
o
c
k

R
e
c
o
v
e
r
y

i
n

P
l
e
i
s
o
c
h
r
o
n
o
u
s

S
y
s
t
e
m
s



6
1
0
13.8
Random Circuits
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
1
0
13.8.1

T
r
u
e

R
a
n
d
o
m

N
u
m
b
e
r

G
e
n
e
r
a
t
o
r
s




6
1
0
13.8.2

C
h
i
p

I
d
e
n
t
i

c
a
t
i
o
n



6
1
1
13.9
Pitfalls and Fallacies

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
1
2
Summary

6
1
3
Exercises


6
1
4
Chapter 14
Design Methodology and Tools
14.1
Introduction
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
1
5
14.2
Structured Design Strategies
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
1
7
14.2.1

A

S
o
f
t
w
a
r
e

R
a
d
i
o

A

S
y
s
t
e
m

E
x
a
m
p
l
e




6
1
8
14.2.2

H
i
e
r
a
r
c
h
y



6
2
0
14.2.3

R
e
g
u
l
a
r
i
t
y



6
2
3
14.2.4

M
o
d
u
l
a
r
i
t
y



6
2
5
14.2.5

L
o
c
a
l
i
t
y



6
2
6
14.2.6

S
u
m
m
a
r
y



6
2
7
14.3
Design Methods

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
2
7
14.3.1

M
i
c
r
o
p
r
o
c
e
s
s
o
r
/
D
S
P




6
2
7
14.3.2

P
r
o
g
r
a
m
m
a
b
l
e

L
o
g
i
c




6
2
8
14.3.3

G
a
t
e

A
r
r
a
y

a
n
d

S
e
a

o
f

G
a
t
e
s

D
e
s
i
g
n




6
3
1
14.3.4

C
e
l
l
-
B
a
s
e
d

D
e
s
i
g
n




6
3
2
14.3.5

F
u
l
l

C
u
s
t
o
m

D
e
s
i
g
n




6
3
4
14.3.6

P
l
a
t
f
o
r
m
-
B
a
s
e
d

D
e
s
i
g
n

S
y
s
t
e
m

o
n

a

C
h
i
p




6
3
5
14.3.7

S
u
m
m
a
r
y



6
3
6
14.4
Design Flows

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
3
6
14.4.1

B
e
h
a
v
i
o
r
a
l

S
y
n
t
h
e
s
i
s

D
e
s
i
g
n

F
l
o
w

(
A
S
I
C

D
e
s
i
g
n

F
l
o
w
)




6
3
7
14.4.2

A
u
t
o
m
a
t
e
d

L
a
y
o
u
t

G
e
n
e
r
a
t
i
o
n




6
4
1
14.4.3

M
i
x
e
d
-
S
i
g
n
a
l

o
r

C
u
s
t
o
m
-
D
e
s
i
g
n

F
l
o
w




6
4
5
14.5
Design Economics
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
4
6
14.5.1

N
o
n
-
R
e
c
u
r
r
i
n
g

E
n
g
i
n
e
e
r
i
n
g

C
o
s
t
s

(
N
R
E
s
)




6
4
7
14.5.2

R
e
c
u
r
r
i
n
g

C
o
s
t
s




6
4
9
14.5.3

F
i
x
e
d

C
o
s
t
s




6
5
0
14.5.4

S
c
h
e
d
u
l
e




6
5
1
14.5.5

P
e
r
s
o
n
p
o
w
e
r




6
5
3
14.5.6

P
r
o
j
e
c
t

M
a
n
a
g
e
m
e
n
t




6
5
3
14.5.7

D
e
s
i
g
n

R
e
u
s
e




6
5
4
Contents
xix
14.6
Data Sheets and Documentation
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
5
5
14.6.1

T
h
e

S
u
m
m
a
r
y




6
5
5
14.6.2

P
i
n
o
u
t




6
5
5
14.6.3

D
e
s
c
r
i
p
t
i
o
n

o
f

O
p
e
r
a
t
i
o
n




6
5
5
14.6.4

D
C

S
p
e
c
i

c
a
t
i
o
n
s




6
5
5
14.6.5

A
C

S
p
e
c
i

c
a
t
i
o
n
s




6
5
6
14.6.6

P
a
c
k
a
g
e

D
i
a
g
r
a
m




6
5
6
14.6.7

P
r
i
n
c
i
p
l
e
s

o
f

O
p
e
r
a
t
i
o
n

M
a
n
u
a
l




6
5
6
14.6.8

U
s
e
r

M
a
n
u
a
l




6
5
6
14.7
CMOS Physical Design Styles

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
5
6
14.8
Pitfalls and Fallacies

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
5
7
Exercises


6
5
7
Chapter 15
Testing, Debugging, and Verification
15.1
Introduction
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
5
9
15.1.1

L
o
g
i
c

V
e
r
i

c
a
t
i
o
n




6
6
0
15.1.2

D
e
b
u
g
g
i
n
g




6
6
2
15.1.3

M
a
n
u
f
a
c
t
u
r
i
n
g

T
e
s
t
s




6
6
4
15.2
Testers, Test Fixtures, and Test Programs

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
6
6
15.2.1

T
e
s
t
e
r
s

a
n
d

T
e
s
t

F
i
x
t
u
r
e
s




6
6
6
15.2.2

T
e
s
t

P
r
o
g
r
a
m
s




6
6
8
15.2.3

H
a
n
d
l
e
r
s




6
6
9
15.3
Logic Verification Principles
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
7
0
15.3.1

T
e
s
t

V
e
c
t
o
r
s




6
7
0
15.3.2

T
e
s
t
b
e
n
c
h
e
s

a
n
d

H
a
r
n
e
s
s
e
s




6
7
1
15.3.3

R
e
g
r
e
s
s
i
o
n

T
e
s
t
i
n
g




6
7
1
15.3.4

V
e
r
s
i
o
n

C
o
n
t
r
o
l




6
7
2
15.3.5

B
u
g

T
r
a
c
k
i
n
g




6
7
3
15.4
Silicon Debug Principles

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
7
3
15.5
Manufacturing Test Principles
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
7
6
15.5.1

F
a
u
l
t

M
o
d
e
l
s




6
7
7
15.5.2

O
b
s
e
r
v
a
b
i
l
i
t
y




6
7
9
15.5.3

C
o
n
t
r
o
l
l
a
b
i
l
i
t
y




6
7
9
15.5.4

R
e
p
e
a
t
a
b
i
l
i
t
y




6
7
9
15.5.5

S
u
r
v
i
v
a
b
i
l
i
t
y




6
7
9
15.5.6

F
a
u
l
t

C
o
v
e
r
a
g
e




6
8
0
15.5.7

A
u
t
o
m
a
t
i
c

T
e
s
t

P
a
t
t
e
r
n

G
e
n
e
r
a
t
i
o
n

(
A
T
P
G
)




6
8
0
15.5.8

D
e
l
a
y

F
a
u
l
t

T
e
s
t
i
n
g




6
8
0
15.6
Design for Testability

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
8
1
15.6.1

A
d

H
o
c

T
e
s
t
i
n
g




6
8
1
15.6.2

S
c
a
n

D
e
s
i
g
n




6
8
2
15.6.3

B
u
i
l
t
-
I
n

S
e
l
f
-
T
e
s
t

(
B
I
S
T
)




6
8
4
15.6.4

I
D
D
Q

T
e
s
t
i
n
g




6
8
7
15.6.5

D
e
s
i
g
n

f
o
r

M
a
n
u
f
a
c
t
u
r
a
b
i
l
i
t
y




6
8
7
WEB
ENHANCED
Contents
xx
15.7
Boundary Scan

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
8
8
15.8
Testing in a University Environment
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
8
9
15.9
Pitfalls and Fallacies

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
9
0
Summary

6
9
7
Exercises


6
9
7
Appendix A
Hardware Description Languages
A.1
Introduction
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

6
9
9
A.1.1

M
o
d
u
l
e
s




7
0
0
A.1.2

S
i
m
u
l
a
t
i
o
n

a
n
d

S
y
n
t
h
e
s
i
s




7
0
1
A.2
Combinational Logic
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

7
0
2
A.2.1

B
i
t
w
i
s
e

O
p
e
r
a
t
o
r
s




7
0
2
A.2.2

C
o
m
m
e
n
t
s

a
n
d

W
h
i
t
e

S
p
a
c
e




7
0
3
A.2.3

R
e
d
u
c
t
i
o
n

O
p
e
r
a
t
o
r
s




7
0
3
A.2.4

C
o
n
d
i
t
i
o
n
a
l

A
s
s
i
g
n
m
e
n
t



7
0
4
A.2.5

I
n
t
e
r
n
a
l

V
a
r
i
a
b
l
e
s



7
0
6
A.2.6

P
r
e
c
e
d
e
n
c
e

a
n
d

O
t
h
e
r

O
p
e
r
a
t
o
r
s



7
0
8
A.2.7

N
u
m
b
e
r
s



7
0
8
A.2.8

Z
s

a
n
d

X
s



7
0
9
A.2.9

B
i
t

S
w
i
z
z
l
i
n
g



7
1
1
A.2.10

D
e
l
a
y
s



7
1
2
A.3
Structural Modeling

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

7
1
3
A.4
Sequential Logic
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

7
1
7
A.4.1

R
e
g
i
s
t
e
r
s




7
1
7
A.4.2

R
e
s
e
t
t
a
b
l
e

R
e
g
i
s
t
e
r
s




7
1
8
A.4.3

E
n
a
b
l
e
d

R
e
g
i
s
t
e
r
s




7
1
9
A.4.4

M
u
l
t
i
p
l
e

R
e
g
i
s
t
e
r
s




7
2
0
A.4.5

L
a
t
c
h
e
s




7
2
1
A.4.6

C
o
u
n
t
e
r
s




7
2
2
A.4.7

S
h
i
f
t

R
e
g
i
s
t
e
r
s




7
2
4
A.5
Combinational Logic with Always / Process Statements

.

.

.

.

.

.

.

.

.

.

.

.

.

.

7
2
4
A.5.1

C
a
s
e

S
t
a
t
e
m
e
n
t
s




7
2
6
A.5.2

I
f

S
t
a
t
e
m
e
n
t
s




7
2
9
A.5.3

S
y
s
t
e
m
V
e
r
i
l
o
g

C
a
s
e
z




7
3
1
A.5.4

B
l
o
c
k
i
n
g

a
n
d

N
o
n
b
l
o
c
k
i
n
g

A
s
s
i
g
n
m
e
n
t
s




7
3
1
A.6
Finite State Machines

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

7
3
5
A.6.1

F
S
M

E
x
a
m
p
l
e




7
3
5
A.6.2

S
t
a
t
e

E
n
u
m
e
r
a
t
i
o
n




7
3
6
A.6.3

F
S
M

w
i
t
h

I
n
p
u
t
s




7
3
8
A.7
Type Idiosyncracies
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

7
4
0
WEB
ENHANCED
Contents
xxi
A.8
Parameterized Modules

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

7
4
2
A.9
Memory
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

7
4
5
A.9.1

R
A
M




7
4
5
A.9.2

M
u
l
t
i
p
o
r
t
e
d

R
e
g
i
s
t
e
r

F
i
l
e
s




7
4
7
A.9.3

R
O
M




7
4
8
A.10
Testbenches
.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

7
4
9
A.11
SystemVerilog Netlists

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

7
5
4
A.12
Example: MIPS Processor

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

7
5
5
A.12.1

T
e
s
t
b
e
n
c
h




7
5
6
A.12.2

S
y
s
t
e
m
V
e
r
i
l
o
g




7
5
7
A.12.3

V
H
D
L




7
6
6
Exercises


7
7
6
References



7
8
5
Index



8
1
7
Credits



8
3
8
xxiii
I
n

t
h
e

t
w
o
-
a
n
d
-
a
-
h
a
l
f

d
e
c
a
d
e
s

s
i
n
c
e

t
h
e


r
s
t

e
d
i
t
i
o
n

o
f

t
h
i
s

b
o
o
k

w
a
s

p
u
b
l
i
s
h
e
d
,

C
M
O
S
t
e
c
h
n
o
l
o
g
y

h
a
s

c
l
a
i
m
e
d

t
h
e

p
r
e
e
m
i
n
e
n
t

p
o
s
i
t
i
o
n

i
n

m
o
d
e
r
n

e
l
e
c
t
r
i
c
a
l

s
y
s
t
e
m

d
e
s
i
g
n
.

I
t

h
a
s
e
n
a
b
l
e
d

t
h
e

w
i
d
e
s
p
r
e
a
d

u
s
e

o
f

w
i
r
e
l
e
s
s

c
o
m
m
u
n
i
c
a
t
i
o
n
,

t
h
e

I
n
t
e
r
n
e
t
,

a
n
d

p
e
r
s
o
n
a
l

c
o
m
-
p
u
t
e
r
s
.

N
o

o
t
h
e
r

h
u
m
a
n

i
n
v
e
n
t
i
o
n

h
a
s

s
e
e
n

s
u
c
h

r
a
p
i
d

g
r
o
w
t
h

f
o
r

s
u
c
h

a

s
u
s
t
a
i
n
e
d

p
e
r
i
o
d
.
T
h
e

t
r
a
n
s
i
s
t
o
r

c
o
u
n
t
s

a
n
d

c
l
o
c
k

f
r
e
q
u
e
n
c
i
e
s

o
f

s
t
a
t
e
-
o
f
-
t
h
e
-
a
r
t

c
h
i
p
s

h
a
v
e

g
r
o
w
n

b
y

o
r
d
e
r
s
o
f

m
a
g
n
i
t
u
d
e
.
T
h
i
s

e
d
i
t
i
o
n

h
a
s

b
e
e
n

h
e
a
v
i
l
y

r
e
v
i
s
e
d

t
o

r
e

e
c
t

t
h
e

r
a
p
i
d

c
h
a
n
g
e
s

i
n

i
n
t
e
g
r
a
t
e
d

c
i
r
c
u
i
t
d
e
s
i
g
n

o
v
e
r

t
h
e

p
a
s
t

s
i
x

y
e
a
r
s
.

W
h
i
l
e

t
h
e

b
a
s
i
c

p
r
i
n
c
i
p
l
e
s

a
r
e

l
a
r
g
e
l
y

t
h
e

s
a
m
e
,

p
o
w
e
r

c
o
n
-
s
u
m
p
t
i
o
n

a
n
d

v
a
r
i
a
b
i
l
i
t
y

h
a
v
e

b
e
c
o
m
e

p
r
i
m
a
r
y

f
a
c
t
o
r
s

f
o
r

c
h
i
p

d
e
s
i
g
n
.

T
h
e

b
o
o
k

h
a
s

b
e
e
n
r
e
o
r
g
a
n
i
z
e
d

t
o

e
m
p
h
a
s
i
z
e

t
h
e

k
e
y

f
a
c
t
o
r
s
:

d
e
l
a
y
,

p
o
w
e
r
,

i
n
t
e
r
c
o
n
n
e
c
t
,

a
n
d

r
o
b
u
s
t
n
e
s
s
.
O
t
h
e
r

c
h
a
p
t
e
r
s

h
a
v
e

b
e
e
n

r
e
o
r
d
e
r
e
d

t
o

r
e

e
c
t

t
h
e

o
r
d
e
r

i
n

w
h
i
c
h

w
e

t
e
a
c
h

t
h
e

m
a
t
e
r
i
a
l
.


How to Use This Book
T
h
i
s

b
o
o
k

i
n
t
e
n
t
i
o
n
a
l
l
y

c
o
v
e
r
s

m
o
r
e

b
r
e
a
d
t
h

a
n
d

d
e
p
t
h

t
h
a
n

a
n
y

c
o
u
r
s
e

w
o
u
l
d

c
o
v
e
r

i
n

a
s
e
m
e
s
t
e
r
.

I
t

i
s

a
c
c
e
s
s
i
b
l
e

f
o
r

a


r
s
t

u
n
d
e
r
g
r
a
d
u
a
t
e

c
o
u
r
s
e

i
n

V
L
S
I
,

y
e
t

d
e
t
a
i
l
e
d

e
n
o
u
g
h

f
o
r
a
d
v
a
n
c
e
d

g
r
a
d
u
a
t
e

c
o
u
r
s
e
s

a
n
d

i
s

u
s
e
f
u
l

a
s

a

r
e
f
e
r
e
n
c
e

t
o

t
h
e

p
r
a
c
t
i
c
i
n
g

e
n
g
i
n
e
e
r
.

Y
o
u

a
r
e
e
n
c
o
u
r
a
g
e
d

t
o

p
i
c
k

a
n
d

c
h
o
o
s
e

t
o
p
i
c
s

a
c
c
o
r
d
i
n
g

t
o

y
o
u
r

i
n
t
e
r
e
s
t
.

C
h
a
p
t
e
r

1

p
r
e
v
i
e
w
s

t
h
e
e
n
t
i
r
e


e
l
d
,

w
h
i
l
e

s
u
b
s
e
q
u
e
n
t

c
h
a
p
t
e
r
s

e
l
a
b
o
r
a
t
e

o
n

s
p
e
c
i

c

t
o
p
i
c
s
.

S
e
c
t
i
o
n
s

a
r
e

m
a
r
k
e
d
w
i
t
h

t
h
e


O
p
t
i
o
n
a
l


i
c
o
n

(
s
h
o
w
n

h
e
r
e

i
n

t
h
e

m
a
r
g
i
n
)

i
f

t
h
e
y

a
r
e

n
o
t

n
e
e
d
e
d

t
o

u
n
d
e
r
s
t
a
n
d
s
u
b
s
e
q
u
e
n
t

s
e
c
t
i
o
n
s
.

Y
o
u

m
a
y

s
k
i
p

t
h
e
m

o
n

a


r
s
t

r
e
a
d
i
n
g

a
n
d

r
e
t
u
r
n

w
h
e
n

t
h
e
y

a
r
e

r
e
l
e
-
v
a
n
t

t
o

y
o
u
.
W
e

h
a
v
e

e
n
d
e
a
v
o
r
e
d

t
o

i
n
c
l
u
d
e


g
u
r
e
s

w
h
e
n
e
v
e
r

p
o
s
s
i
b
l
e

(

a

p
i
c
t
u
r
e

i
s

w
o
r
t
h

a

t
h
o
u
-
s
a
n
d

w
o
r
d
s

)

t
o

t
r
i
g
g
e
r

y
o
u
r

t
h
i
n
k
i
n
g
.

A
s

y
o
u

e
n
c
o
u
n
t
e
r

e
x
a
m
p
l
e
s

t
h
r
o
u
g
h
o
u
t

t
h
e

t
e
x
t
,

w
e
u
r
g
e

y
o
u

t
o

t
h
i
n
k

a
b
o
u
t

t
h
e
m

b
e
f
o
r
e

r
e
a
d
i
n
g

t
h
e

s
o
l
u
t
i
o
n
s
.

W
e

h
a
v
e

a
l
s
o

p
r
o
v
i
d
e
d

e
x
t
e
n
-
s
i
v
e

r
e
f
e
r
e
n
c
e
s

f
o
r

t
h
o
s
e

w
h
o

n
e
e
d

t
o

d
e
l
v
e

d
e
e
p
e
r

i
n
t
o

t
o
p
i
c
s

i
n
t
r
o
d
u
c
e
d

i
n

t
h
i
s

t
e
x
t
.

W
e
1st Edition
2nd Edition
3rd Edition
4th Edition
Year
1
9
8
5
1
9
9
3
2
0
0
4
2
0
1
0
Transistor Counts
1
0
5

1
0
6
1
0
6

1
0
7
1
0
8

1
0
9
1
0
9

1
0
1
0
Clock Frequencies
1
0
7
1
0
8
1
0
9
1
0
9
Worldwide Market
$
2
5
B
$
6
0
B
$
1
7
0
B
$
2
5
0
B
Preface
Contents
xxiv
h
a
v
e

e
m
p
h
a
s
i
z
e
d

t
h
e

b
e
s
t

p
r
a
c
t
i
c
e
s

t
h
a
t

a
r
e

u
s
e
d

i
n

i
n
d
u
s
t
r
y

a
n
d

w
a
r
n
e
d

o
f

p
i
t
f
a
l
l
s

a
n
d

f
a
l
-
l
a
c
i
e
s
.

O
u
r

j
u
d
g
m
e
n
t
s

a
b
o
u
t

t
h
e

m
e
r
i
t
s

o
f

c
i
r
c
u
i
t
s

m
a
y

b
e
c
o
m
e

i
n
c
o
r
r
e
c
t

a
s

t
e
c
h
n
o
l
o
g
y

a
n
d
a
p
p
l
i
c
a
t
i
o
n
s

c
h
a
n
g
e
,

b
u
t

w
e

b
e
l
i
e
v
e

i
t

i
s

t
h
e

r
e
s
p
o
n
s
i
b
i
l
i
t
y

o
f

a

w
r
i
t
e
r

t
o

a
t
t
e
m
p
t

t
o

c
a
l
l

o
u
t
t
h
e

m
o
s
t

r
e
l
e
v
a
n
t

i
n
f
o
r
m
a
t
i
o
n
.
Supplements
N
u
m
e
r
o
u
s

s
u
p
p
l
e
m
e
n
t
s

a
r
e

a
v
a
i
l
a
b
l
e

o
n

t
h
e

C
o
m
p
a
n
i
o
n

W
e
b

s
i
t
e

f
o
r

t
h
e

b
o
o
k
,
www.cmosvlsi.com
.

S
u
p
p
l
e
m
e
n
t
s

t
o

h
e
l
p

s
t
u
d
e
n
t
s

w
i
t
h

t
h
e

c
o
u
r
s
e

i
n
c
l
u
d
e
:
!
A

l
a
b

m
a
n
u
a
l

w
i
t
h

l
a
b
o
r
a
t
o
r
y

e
x
e
r
c
i
s
e
s

i
n
v
o
l
v
i
n
g

t
h
e

d
e
s
i
g
n

o
f

a
n

8
-
b
i
t

m
i
c
r
o
p
r
o
-
c
e
s
s
o
r

c
o
v
e
r
e
d

i
n

C
h
a
p
t
e
r

1
.
!
A

c
o
l
l
e
c
t
i
o
n

o
f

l
i
n
k
s

t
o

V
L
S
I

r
e
s
o
u
r
c
e
s

i
n
c
l
u
d
i
n
g

o
p
e
n
-
s
o
u
r
c
e

C
A
D

t
o
o
l
s

a
n
d

p
r
o
-
c
e
s
s

p
a
r
a
m
e
t
e
r
s
.
!
A

s
t
u
d
e
n
t

s
o
l
u
t
i
o
n
s

m
a
n
u
a
l

t
h
a
t

i
n
c
l
u
d
e
s

a
n
s
w
e
r
s

t
o

o
d
d
-
n
u
m
b
e
r
e
d

p
r
o
b
l
e
m
s
.
!
C
e
r
t
a
i
n

s
e
c
t
i
o
n
s

o
f

t
h
e

b
o
o
k

m
o
v
e
d

o
n
l
i
n
e

t
o

s
h
o
r
t
e
n

t
h
e

p
a
g
e

c
o
u
n
t
.

T
h
e
s
e

s
e
c
-
t
i
o
n
s

a
r
e

i
n
d
i
c
a
t
e
d

b
y

t
h
e


W
e
b

E
n
h
a
n
c
e
d


i
c
o
n

(
s
h
o
w
n

h
e
r
e

i
n

t
h
e

m
a
r
g
i
n
)
.
S
u
p
p
l
e
m
e
n
t
s

t
o

h
e
l
p

i
n
s
t
r
u
c
t
o
r
s

w
i
t
h

t
h
e

c
o
u
r
s
e

i
n
c
l
u
d
e
:
!
A

s
a
m
p
l
e

s
y
l
l
a
b
u
s
.
!
L
e
c
t
u
r
e

s
l
i
d
e
s

f
o
r

a
n

i
n
t
r
o
d
u
c
t
o
r
y

V
L
S
I

c
o
u
r
s
e
.

!
A
n

i
n
s
t
r
u
c
t
o
r

s

m
a
n
u
a
l

w
i
t
h

s
o
l
u
t
i
o
n
s
.
T
h
e
s
e

m
a
t
e
r
i
a
l
s

h
a
v
e

b
e
e
n

p
r
e
p
a
r
e
d

e
x
c
l
u
s
i
v
e
l
y

f
o
r

p
r
o
f
e
s
s
o
r
s

u
s
i
n
g

t
h
e

b
o
o
k

i
n

a
c
o
u
r
s
e
.

P
l
e
a
s
e

s
e
n
d

e
m
a
i
l

t
o

computing@aw.com

f
o
r

i
n
f
o
r
m
a
t
i
o
n

o
n

h
o
w

t
o

a
c
c
e
s
s

t
h
e
m
.
Acknowledgments
W
e

a
r
e

i
n
d
e
b
t
e
d

t
o

m
a
n
y

p
e
o
p
l
e

f
o
r

t
h
e
i
r

r
e
v
i
e
w
s
,

s
u
g
g
e
s
t
i
o
n
s
,

a
n
d

t
e
c
h
n
i
c
a
l

d
i
s
c
u
s
s
i
o
n
s
.
T
h
e
s
e

p
e
o
p
l
e

i
n
c
l
u
d
e
:

B
h
a
r
a
d
w
a
j


B
i
r
d
y


A
m
r
u
t
u
r
,

M
a
r
k

A
n
d
e
r
s
,

A
d
n
a
n

A
z
i
z
,

J
a
c
o
b
B
a
k
e
r
,

K
a
u
s
t
a
v

B
a
n
e
r
j
e
e
,

S
t
e
v
e

B
i
b
y
k
,

D
a
v
i
d

B
l
a
a
u
w
,

E
r
i
k

B
r
u
n
v
a
n
d
,

N
e
i
l

B
u
r
g
e
s
s
,
W
a
y
n
e

B
u
r
l
e
s
o
n
,

R
o
b
e
r
t

D
r
o
s
t
,

J
o

E
b
e
r
g
e
n
,

S
a
r
a
h

H
a
r
r
i
s
,

J
a
c
o
b

H
e
r
b
o
l
d
,

R
o
n

H
o
,

D
a
v
i
d
H
o
p
k
i
n
s
,

M
a
r
k

H
o
r
o
w
i
t
z
,

S
t
e
v
e
n

H
s
u
,

T
a
n
a
y

K
a
r
n
i
k
,

O
m
i
d

K
a
v
e
h
,

M
a
t
t
h
e
w

K
e
e
t
e
r
,
B
e
n

K
e
l
l
e
r
,

A
l
i

K
e
s
h
a
v
a
r
z
i
,

B
r
u
c
e
k

K
h
a
i
l
a
n
y
,

J
a
e
h
a

K
i
m
,

V
o
l
k
a
n

K
u
r
s
u
n
,

S
i
m
o
n

K
n
o
w
l
e
s
,
R
a
m

K
r
i
s
h
n
a
m
u
r
t
h
y
,

A
u
s
t
i
n

L
e
e
,

A
n
a

S
o
n
i
a

L
e
o
n
,

S
h
i
h
-
L
i
e
n

L
u
,

S
a
n
u

M
a
t
h
e
w
,

A
l
e
k
-
s
a
n
d
a
r

M
i
l
e
n
k
o
v
i
c
,

S
a
m

N
a
f
f
z
i
g
e
r
,

B
r
a
d
e
n

P
h
i
l
l
i
p
s
,

S
t
e
f
a
n

R
u
s
u
,

J
u
s
t
i
n

S
c
h
a
u
e
r
,

J
a
m
e
s
S
t
i
n
e
,

J
a
s
o
n

S
t
i
n
s
o
n
,

A
a
r
o
n

S
t
r
a
t
t
o
n
,

I
v
a
n

S
u
t
h
e
r
l
a
n
d
,

J
i
m

T
s
c
h
a
n
z
,

A
l
i
c
e

W
a
n
g
,

G
u
-
Y
e
o
n

W
e
i
,

a
n
d

P
e
i
y
i

Z
h
a
o
.

W
e

a
p
o
l
o
g
i
z
e

i
n

a
d
v
a
n
c
e

t
o

a
n
y
o
n
e

w
e

o
v
e
r
l
o
o
k
e
d
.
M
O
S
I
S

a
n
d

I
B
M

k
i
n
d
l
y

p
r
o
v
i
d
e
d

p
e
r
m
i
s
s
i
o
n

t
o

u
s
e

n
a
n
o
m
e
t
e
r

S
P
I
C
E

m
o
d
e
l
s

f
o
r
m
a
n
y

e
x
a
m
p
l
e
s
.

N
a
t
h
a
n
i
e
l

P
i
n
c
k
n
e
y

s
p
e
n
t

a

s
u
m
m
e
r

r
e
v
i
s
i
n
g

t
h
e

l
a
b
o
r
a
t
o
r
y

e
x
e
r
c
i
s
e
s

a
n
d
u
p
d
a
t
i
n
g

s
i
m
u
l
a
t
i
o
n
s
.

J
a
e
h
a

K
i
m

c
o
n
t
r
i
b
u
t
e
d

n
e
w

s
e
c
t
i
o
n
s

o
n

p
h
a
s
e
-
l
o
c
k
e
d

l
o
o
p
s

a
n
d
h
i
g
h
-
s
p
e
e
d

I
/
O

f
o
r

C
h
a
p
t
e
r

1
3
.

D
a
v
i
d

w
o
u
l
d

l
i
k
e

t
o

t
h
a
n
k

B
h
a
r
a
d
w
a
j

A
m
r
u
t
u
r

o
f

t
h
e
I
n
d
i
a
n

I
n
s
t
i
t
u
t
e

o
f

S
c
i
e
n
c
e

a
n
d

B
r
a
d
e
n

P
h
i
l
l
i
p
s

o
f

t
h
e

U
n
i
v
e
r
s
i
t
y

o
f

A
d
e
l
a
i
d
e

f
o
r

h
o
s
t
i
n
g
h
i
m

d
u
r
i
n
g

t
w
o

p
r
o
d
u
c
t
i
v
e

s
u
m
m
e
r
s

o
f

w
r
i
t
i
n
g
.
Preface
WEB
ENHANCED
Contents
xxv
A
d
d
i
s
o
n
-
W
e
s
l
e
y

h
a
s

d
o
n
e

a
n

a
d
m
i
r
a
b
l
e

j
o
b

w
i
t
h

t
h
e

g
r
u
e
l
i
n
g

e
d
i
t
o
r
i
a
l

a
n
d

p
r
o
d
u
c
-
t
i
o
n

p
r
o
c
e
s
s
.

W
e

w
o
u
l
d

p
a
r
t
i
c
u
l
a
r
l
y

l
i
k
e

t
o

t
h
a
n
k

o
u
r

e
d
i
t
o
r
,

M
a
t
t

G
o
l
d
s
t
e
i
n
,

a
n
d

o
u
r
c
o
m
p
o
s
i
t
o
r
,

G
i
l
l
i
a
n

H
a
l
l
.
S
a
l
l
y

H
a
r
r
i
s

h
a
s

b
e
e
n

e
d
i
t
i
n
g

f
a
m
i
l
y

b
o
o
k
s

s
i
n
c
e

D
a
v
i
d

w
a
s

a
n

i
n
f
a
n
t

o
n

h
e
r

l
a
p
.

S
h
e
r
e
a
d

t
h
e

p
a
g
e

p
r
o
o
f
s

w
i
t
h

a
m
a
z
i
n
g

a
t
t
e
n
t
i
o
n

t
o

d
e
t
a
i
l

a
n
d

u
n
e
a
r
t
h
e
d

h
u
n
d
r
e
d
s

o
f

e
r
r
o
r
s
.

T
h
i
s

b
o
o
k

w
o
u
l
d

n
o
t

h
a
v
e

e
x
i
s
t
e
d

w
i
t
h
o
u
t

t
h
e

s
u
p
p
o
r
t

o
f

o
u
r

f
a
m
i
l
i
e
s
.

D
a
v
i
d

w
o
u
l
d
p
a
r
t
i
c
u
l
a
r
l
y

l
i
k
e

t
o

t
h
a
n
k

h
i
s

w
i
f
e

J
e
n
n
i
f
e
r

a
n
d

s
o
n
s

A
b
r
a
h
a
m

a
n
d

S
a
m
u
e
l

f
o
r

e
n
d
u
r
i
n
g
t
w
o

s
u
m
m
e
r
s

o
f

a
b
s
e
n
c
e

w
h
i
l
e

w
r
i
t
i
n
g
,

a
n
d

t
o

o
u
r

e
x
t
e
n
d
e
d

f
a
m
i
l
y

f
o
r

t
h
e
i
r

t
r
e
m
e
n
d
o
u
s
a
s
s
i
s
t
a
n
c
e
.
W
e

h
a
v
e

b
e
c
o
m
e

p
a
i
n
f
u
l
l
y

a
w
a
r
e

o
f

t
h
e

e
a
s
e

w
i
t
h

w
h
i
c
h

m
i
s
t
a
k
e
s

c
r
e
e
p

i
n
t
o

a

b
o
o
k
.
S
c
o
r
e
s

o
f

3
r
d

e
d
i
t
i
o
n

r
e
a
d
e
r
s

h
a
v
e

r
e
p
o
r
t
e
d

b
u
g
s

t
h
a
t

a
r
e

n
o
w

c
o
r
r
e
c
t
e
d
.

D
e
s
p
i
t
e

o
u
r

b
e
s
t
e
f
f
o
r
t
s

a
t

v
a
l
i
d
a
t
i
o
n
,

w
e

a
r
e

c
o
n

d
e
n
t

t
h
a
t

w
e

h
a
v
e

i
n
t
r
o
d
u
c
e
d

a

s
i
m
i
l
a
r

n
u
m
b
e
r

o
f

n
e
w
e
r
r
o
r
s
.

P
l
e
a
s
e

c
h
e
c
k

t
h
e

e
r
r
a
t
a

s
h
e
e
t

a
t

www.cmosvlsi.com/errata.pdf

t
o

s
e
e

i
f

t
h
e
b
u
g

h
a
s

a
l
r
e
a
d
y

b
e
e
n

r
e
p
o
r
t
e
d
.

S
e
n
d

y
o
u
r

r
e
p
o
r
t
s

t
o

bugs@cmosvlsi.com
.

N
.

W
.
D
.

M
.

H
.
J
a
n
u
a
r
y

2
0
1
0
Preface