then - Betil Dedeoglu

coleslawokraSoftware and s/w Development

Dec 1, 2013 (3 years and 6 months ago)

136 views

DISTRIBUTED COMPUTER
SYSTEMS


prof. dr hab. Ludwik Czaja

UV 2011/2012 (
summer

semester
)




07
-
02,

14
-
02
,

21
-
02
,

28
-
02
,

06
-
03
,

13
-
03
,

14:30
-
16:25
room

310

20
-
03
,

27
-
03
,

03
-
04
,

17
-
04
,

24
-
04
,

08
-
05

Topics
:




Structure

and
activity

of computer
with

internal

control

(
main

parts and


instruction

execution

cycle
,
exemplary

instruction

list,
examples

of
simple


programs

run


animated

simulation
)




Idea of
process
.
Inter
-
process

mechanisms

of
synchronization

and


communication
.
Centralized

multiprocessor

systems


simulated



(
multiprogrammed
, time
sharing
,
interrupts
) and
real

(
with

a
collection

of


physical

processors
).
Examples

of
their

activity

(
synchronous
:
vector

and


array

systems
among

others
)


animated

simulation
.
Undesirable


(
pathological
)
behaviour
:
deadlocks
,
starvation
,
unfair

allocation

of resources




From

centralized

systems
simulating

some

functions

of
distributed

systems


to
real



physically

distributed

systems.
Survey

of
various

types

of systems


and
their

interrelations
. A
certain

classification



the

so
-
called

Flynn’s


taxonomy




Distributed

systems:
definitions

(
informal
),
objectives
,
features




Main

tasks

of
distributed

systems and
their

implementation
:




Resource

sharing




Problems

with

concurrency
:
synchronization
,
distributed

mutual
exclusion


(
supervisory

server

and
token

ring
arrangements
),
process

sequencing
,


deadlocks

and
starvation
,
distributed

transactions

(
e.g
.
in

banking)




Communication
,
protocols

in

the

standard
models

OSI, ATM




Remote

Procedure

Call




Events

and
their

orders

(tota
l and
partial
)




Clock

management,
phisical

and
logical

time,
algorithms

of
compensation
,


coordination

of
processes
, mutual
exclusion

with

logical

clock



(broadcasting
method
)




failure
:
detection

and
removal
,
algorithms

of
election




Models

of
distributed

systems:
client
/
server

model and
object

model




Structure

of
distributed

operating

system.
Usage

of
main

tasks

of
distributed


systems,
processes

and
threads





Distributed

Shared

Memory

(DSM)




Examples

of
specification

and
analysis

of
typical

problems

with

parallel


processing

on
distributed

systems (
like


Producers
/
Consumers
”,



Readers
/
Writers
”, „
Dining

Philosophers
”, „
Street
-
traffic

control
”, etc.).


Presentation

with

graphic

animated

simulator

of
Cause
-
Effect

structures


Literature
:

1.
Slides

presented

in

lectures

2.
G
.

Coulouris
, J.
Dollimore
, T.
Kindberg
:

Distributed

Systems
.

Concepts

and Design
.


Addison

Wesley,
Editions
: 1988, 1994, 1995, 1996, 2005.

3.
A.S.
Tanenbaum
:
Distributed

Operating

Systems
.
Prentice
-
Hall

1995

4.
M.
Ben
-
Ari
:
Principles

of
Concurrent

and
Distributed

Programming
.

Prentice
-
Hall

1990

5.
L.
Czaja
:
Elementary Cause
-
Effect Structures
, Warsaw University, 2002

6. C. Cachin, R.
Guerraoui
, L. Rodrigues:
Introduction

to
Reliable

and
Secure


Distributed

Programming
.
Second

Edition
, Springer 2011

7.
D.W.Davies
,
E.Holler
,
E.D.Jensen
, S.R.
Kimbleton
, B.W.
Lampson
, G.
LeLann
,


K.J.
Thurber
, R.W. Watson:
Distributed

Systems


Architecture

and
Implementation
,


An
Advanced

Course
,
Springer 1983

Exercises

(lab.):

Application

of
familiar

programming

languages

to
constructing

of
programs

on
distributed

systems

Lecture

1

1.
Principle

of
internal

control

(von
Neumann)
vs
.
external

control
,
universality



programmability

2.

Functional

schema

of computer
with

internal

control

and
with

a
few

typical

(
exemplary
)
instructions

(
commands
),
example

of
activity



simulation

(a program
in

an
assembler
-
like

language
)

3.
Types

of computer systems,
Flynn’s

taxonomy

4.

Processes
,
their

parallel
/
concurrent

execution

on
centralized

and
distributed

architectures
,
synchronization

and
communication

mechanisms
,
examples

of
activity



simulation

of
simple

programs
.
Deadlocks

and
starvation
.







Why

do we start
from

the

structure

and
activity

(
instruction

cycle
) of
sequential

machine


of von Neumann?

Because
:



multiprocessor

and
multicomputer

distributed

system
is

a
collecion

of
such


machines
:



multiprocessor

-

a
collection

of
CPUs

with

common

memory



multicomputer



a
collection

of
autonomous

computers

(
possibly

with



diverse

architecture
)
connected

by a
network

of
transmission

channels



and
endowed

with

a
distributed

operating

system




the

objective

of a
multiprocessor

and
multicomputer

architecture

is

to
provide


the

users

an
impression

of
work

with

a
sequential

machine

with

enormously



enhanced

capabilities
:
speeding

up

algoritms

(
multiprocessors
), resources


sharing

and
communication



a
tool

of
social

communication

(
distributed


multicomputer

systems


networks)




basic

functions

of
distributed

systems
are

analogous

to
those

in

a
classical


sequential

machine
,
e.g
.
communication

mechanisms

in

a
network

of
computers


are

significantly

extended

input
/
output

mechanisms

in

sequential


machines




showing

of
simple

programs

execution

on an
abstract

(model) von
Neumann’s


machine

and (
concurrently
) on a
connected

collection

of
such

machines


exhibits

many
problems

occurring

in

real

distributed

systems

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25

20

IC:

I
R
:

A:

other

registers
:

main

(
operation

store
,
internal

store
)
memory

(RAM


Random Access
Memory
)


procesor
(CPU = ALU +
control
)

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

external

memory


(
e.g
.
disc
)



Input
/
Output

devices

Functional

schema

of a computer
with

internal

control



IC


Instruction

Counter
, IR


Instruction

Register, A
-

Accumulator




operation

address

meaning

of
operation


part
part


LA n
load

accumulator

with

the

content

of a
cell

addressed

n


(
A:=n
) and go to
the

next

instruction

in

the

program (IC:=IC+1)



S
A n
store

the

content

of
accumulator

in

the

cell

addressed

n



(
n:=A
) and go to
the

next

instruction

in

the

program (IC:=IC+1)



AD n
add

to
the

accumulator

the

content

of a
cell

addressed

n


(
A:=A+n
) and go to
the

next

instruction

in

the

program (IC:=IC+1)


SU n
subtract

from

the

accumulator

the

content

of a
cell

addressed

n


(
A:=A
-
n
) and go to
the

next

instruction

in

the

program (IC:=IC+1)


MU n
multiply

accumulator

by
the

content

of a
cell

addressed

n


(
A:=A*n
) and go to
the

next

instruction

in

the

program (IC:=IC+1)


DI n
divide

accumulator

by
the

content

of a
cell

addressed

n


(
A:=A
/n) and go to
the

next

instruction

in

the

program (IC:=IC+1)


JU n
unconditional

jump

(transfer of
control
) to
address

n
in



the

program (
IC:=IC+<n
>)
(
got
o

n)


JZ n
conditional

jump

(transfer of
control
) to
address

n
in

the


program
if

A=0;
otherwise

go to
the

next

instruction

in

the


program (
if

A=0
then

JU n
else

IC:=IC+1)


J
W

n
conditional

jump

(transfer of
control
) to
address

n
in

the


program
if

communication

register
is

empty

(
contains

W);


otherwise

go to
the

next

instruction

in

the

program


(
if

chan=

W

then

JU n
else

IC:=IC+1)


ST n stop


transfer
control

to
address

n
in

the

program and


terminate

its

run

Exemplary

instruction

set (
simplified
)





P2!

n
If

program P2
is

ready

to
receive

a
value

from

the

program
in

which



this

instruction

is

being

executed

then

send

the

content

of a
cell



addressed

n to P2 (
through

a
communication

channel) and go to
the



next

instruction

in

the

program;
otherwise

wait

until

it

happens


P1
?

n
If

program P1
is

ready

to
send

a
value

to
the

program
in

which

this


instruction

is

being

executed

then

receive

it

from

P1,
store

it


in

the

cell

addressed

n and go to
the

next

instruction

in

the

program;


otherwise

wait

until

it

happens

Synchronous

communication





S(P2)

n

send

the

content

of a
cell

addressed

n to program P2 and go to


the

next

instruction

(
transmission

through

a
message

queue
)


R(P1)

n
If

the

program P1
has

sent

a
value

to
the

program
in

which

this


instruction

is

being

executed

then

receive

it
,
store

it

in

a
cell


addressed

n and go to
the

next

instruction

in

the

program;


otherwise

wait

until

it

happens



Asynchronous

communication

Simulation

of a program run on
the

functional

schema

of computer
with

internal

control


IC


Instruction

Counter
, IR


Instruction

Register, A
-

Accumulator





Example

of
computing
:


x
:=y*z+u/v

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


0

Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


0

Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

L
A

20

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


1

Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

L
A

20

3.14

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


1

Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

MU

21

3.14

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


2

Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

MU

20

6.28

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


2

Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

SA

25

6.28

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


3

Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

SA

25

6.28

6.28

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


3

Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

LA

22

6.28

6.28

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


4

Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

LA

22

6.28

15.9

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


4

Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

DI

23

6.28

15.9

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


5

Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

DI

23

6.28

5.3

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


5

Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

AD

25

6.28

5.3

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

AD

25

6.28

6

11.58

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

SA

24

6.28

6

11.58

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


Example
:
computation

of x
:=y*z+u/v

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

SA

24

6.28

7

11.58

11.58

ST 0

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


Example
:
computation

of x
:=y*z+u/v

ST 0

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

ST

0

6.28

7

11.58

11.58

Prześlij do


0 1 2 3 4 5 6 7 … 20 21 22 23
24 25



y z u v x temp

20

IC:

I
R
:

A:

other

registers
:

RAM


CPU

allocation

(
addressing
) of
variables
:


LA
20
MU
21
SA
25
LA
22

DI 23 AD
25
SA
24


Example
:
computation

of x
:=y*z+u/v

ST 0

3.14

2.0

15.9

3.0

Copy

to IR
the

content

of
address

indicated

by IC

If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then



IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then



execute

it

and IC:=IC+1

instruction

execution

cycle

ST

0

6.28

0

11.58

11.58

Types

of computer systems.
Flynn’s

taxonomy


computer systems

centralized

distributed


uniprocessor


multiprocessor

(
shared

memory
)

uniaccessed

(single

workplace
)

multiaccessed

(
more

than


one
workplace
)

multiprogrammed

(
time
-
sharing
,

simulated

parallelism
)

synchronous

asynchronous

vector

array

systolic

Global Networks

Local

Area

Networks (LAN)

Personal

Networks (PAN)

Corporate

Networks

multicomputer

(
disconnected
)

multicomputer

(
connected
)

uniaccessed

(single

workplace
)

multiaccessed

(
more

than


one
workplace
)

Wide

Area

Networks (WAN)

Metropolitan

Networks (MAN)

single
program

single
program

multipro
-
grammed

Flynn’s

taxonomy

of computer systems (1972
)




SISD
(
S
ingle
I
nstruction

[
stream
]
S
ingle
D
ata [
stream
])


traditional


computers

with

one
instruction

stream





SIMD

(
S
ingle
I
nstruction

[
stream
]
M
ultiple

D
ata [
stream
])

systems
with


one
instruction

stream

and
more

than

one
stream

of data




MISD

(
M
ultiple

I
nstruction

[
stream
]
S
ingle
D
ata [
stream
])

systems
with


more

than

one
instruction

stream

and one data
stream

(do not
exist
)




MIMD

(
M
ultiple

I
nstruction

[
stream
]
M
ultiple

D
ata [
stream
])


systems
with


more

than

one
instruction

and
more

than

one data
stream







Computer networks




Global





SAGE

(
Semi

Automatic
Ground

Environment,
USA,
the

50
th

of XX
century
)



ARPANET
(
USA,
the

70
th

of XX
century

),



BITNET
(
USA,
in

use

since

1981 to 2000
),



EARN

(
European Academic and Research Network

1984),



INTERNET
(1984,

beginnings



end

of 60
th

of
XXcentury
;
originated

from



ARPANET)




Wide

Area

(WAN)




Local

(
LAN; most popular ETHERNET)




Corporate

(Intranet
)




Metropolitan

(MAN)




Personal

(PAN)


Beginnings

of
large

networks
in

Poland




PLEARN

(
Polish

branch

of EARN
),
connected

to EARN
w
1999,


server

in

CIUW [Centrum
Informatyczne Uniwersytetu Warszawskiego];


first
version

in

operation
:
the

mid

eighties





NASK

(Naukowa i Akademicka Sieć Komputerowa
established

in

1991


in

the

University

of Warsaw;
initiated

by a team of
physicists

of


the

UW
,
played

essential

part
in

connecting

Poland to INTERNET)




Process
:




informal
:
execution

of a program
with

data




slightly

more

formal
: a
sequence

of global
states

of a system (hardware)
executing

a
program
or



concurrently



a
collection

of
programs
; global state:
instantaneous

set
of
values

of
the

system’s

resources,
e.g
.
variables

or

other

objects

in

a program
written

in

a
certain

programming

language
,
instantaneous

content

of
the

memory

of a
computer
or

a set of
computers
, time(s) of
clocks

in

processors
, etc.




still

more

formal
: a
function

assigning

values

to resources (
e.g
.
memory

cells

and


registers
)




in

theories

of
concurrency
:
activity

of a system
expressed

(
reported
) as a
mathematical

object

(
function
,
relation
,
graph
,
transition

system,
Petri

net,
Mazurkiewicz’s

trace
, etc.)

It

is

possible

to run many
processes

on a single
sequential

computer


if

it

is

equipped

with

suitable

instructions

of
interrupt

and restart of
processes
.
This

is

a
simulation

of
multiprocessor

or

multicomputer

system.
Such

computer
is

a
multiprogrammed

(
time
-
sharing
) system.


Activity

of a
multiprogrammed

one
-
processor

system
schema

(
with

time
-
sharing
).
The

computer
is

equipped

with

instructions

of
interrupt

and restart of
processes

and
handling

with

queue

MIMD
simulation

Prześlij do

memory


processor

P1:
program

before

run

P2:
program

before

run

P3:
program

before

run

P4:
program

before

run

queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

Prześlij do

memory


processor

P1:
program

before

run

P2:
program

before

run

P4:
program

before

run

queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program


run

Prześlij do

memory


processor

P1:
program


run

P2:
program

before

run

P4:
program

before

run

queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program


interrupted

Prześlij do

memory


processor

P1:
program


interrupted

P2:
program

before

run

P4:
program


run

queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program


interrupted

Prześlij do

memory


processor

P1:
program


interrupted

P2:
program


run

P4:
program


interrupted

queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program


interrupted

Prześlij do

memory


processor

P1:
program


interrupted

P2:
program


interrupted

P4:
program


interrupted

queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program


run

Prześlij do

memory


processor

P1:
program


run

P2:
program


interrupted

P4:
program


interrupted

queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program


interrupted

Prześlij do

memory


processor

P1:
program


interrupted

P2:
program


interrupted

P4:
program


run

queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program


interrupted

tail

Prześlij do

memory


processor

P1:
program


interrupted

P2:
program


run

P4:
program


interrupted

queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program


interrupted

Prześlij do

memory


processor

P1:
program


interrupted

P2:
program


interrupted

P4:
program


interrupted

queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program


run

Prześlij do

memory


processor

P1:
program


run

P2:
program


interrupted

P4:
program


interrupted

queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program


interrupted

Prześlij do

memory


processor

P1:
program


interrupted

P2:
program


interrupted

P4:
program


run

queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program


interrupted

Prześlij do

memory


processor

P1:
program


interrupted

P2:
program


run

P4:
program


terminated


queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program


interrupted

Prześlij do

memory


processor

P1:
program


interrupted

P2:
program


interrupted

P4:
program


terminated


queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program


run

Prześlij do

memory


processor

P1:
program


run

P2:
program


interrupted

P4:
program


terminated


queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program

terminated

Prześlij do

memory


processor

P1:
program

terminated

P2:
program


run

P4:
program


terminated


queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program

terminated

Prześlij do

memory


processor

P1:
program

terminated

P2:
program

terminated

P4:
program


terminated


queue

of
interrupted

programs

state of
programs
:



before

run



interrupted



run



terminated

P3:
program

terminated

Why

synchronization

of
parallel

processes

is

necessary
?

Example

of
incorrect

activity


(
without

synchronization
)


Remind

the

instruction
:


J
W

n
conditional

jump

(transfer of
control
) to
address

n
in

the


program
if

communication

register
is

empty

(
contains

W);


othervise

go to
the

next

instruction

in

the

program


(
if

chan=

W

then

JU n
else

IC:=IC+1)


Note
:
this

instruction

can

be
simulated

by
instruction

JZ n


2
-
processor
centralized

schema

with

shared

memory

for data and
identical

pace (
speed
) of
clocks



IC


instruction

counter

IR


instruction

register
A
-
accumulator

INCORRECT SOLUTION!

MIMD

Example

of
computing
:


x
:=y*z+u/v

Prześlij do

20

IC:

A
:


other


registers
:


processor

1


LA 20 MU 21 J
W

6 AD
ch

SA 24 ST 0 SA
ch

ST 0

0


0 1

2
3 4 5 6 7

Prześlij do


0
1 2 3 4 5 6
7

processor

2

ch
:

W

20

21
22 23 24


y

z u v x

allocation

(
addressing
) of
variables
:

3.14

2.0

15.9

3.0

shared

memory

for data:


LA 22 DI 23 J
W

6 AD
ch

SA 24 ST
0

SA
ch

ST
0

IR:

20

IC:

A
:

0

IR:


other


registers
:

Copy

to IR
the

content

of
address

indicated

by IC


If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then




IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then

execute

it

and IC:=IC+1

Copy

to IR
the

content

of
address

indicated

by IC


If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then




IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then

execute

it

and IC:=IC+1

Prześlij do

20

IC:

A
:


other


registers
:


processor

1


LA 20 MU 21 J
W

6 AD
ch

SA 24 ST 0 SA
ch

ST 0

0


0 1

2
3 4 5 6 7

Prześlij do


0
1 2 3 4 5 6
7

processor

2

ch
:

W

20

21
22 23 24


y

z u v x

allocation

(
addressing
) of
variables
:

3.14

2.0

15.9

3.0

shared

memory

for data:


LA 22 DI 23 J
W

6 AD
ch

SA 24 ST
0

SA
ch

ST
0

IR:

20

IC:

A
:

0

IR:


other


registers
:

Copy

to IR
the

content

of
address

indicated

by IC


If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then




IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then

execute

it

and IC:=IC+1

Copy

to IR
the

content

of
address

indicated

by IC


If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then




IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then

execute

it

and IC:=IC+1

L
A
20

L
A
22

Prześlij do

20

IC:

A
:


other


registers
:


processor

1


LA 20 MU 21 J
W

6 AD
ch

SA 24 ST 0 SA
ch

ST 0

1


0 1

2
3 4 5 6 7

Prześlij do


0
1 2 3 4 5 6
7

processor

2

ch
:

W

20

21
22 23 24


y

z u v x

allocation

(
addressing
) of
variables
:

3.14

2.0

15.9

3.0

shared

memory

for data:


LA 22 DI 23 J
W

6 AD
ch

SA 24 ST
0

SA
ch

ST
0

IR:

20

IC:

A
:

1

IR:


other


registers
:

Copy

to IR
the

content

of
address

indicated

by IC


If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then




IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then

execute

it

and IC:=IC+1

Copy

to IR
the

content

of
address

indicated

by IC


If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then




IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then

execute

it

and IC:=IC+1

L
A
20

L
A
22

3.14

15.9

Prześlij do

20

IC:

A
:


other


registers
:


processor

1


LA 20 MU 21 J
W

6 AD
ch

SA 24 ST 0 SA
ch

ST 0

1


0 1

2
3 4 5 6 7

Prześlij do


0
1 2 3 4 5 6
7

processor

2

ch
:

W

20

21
22 23 24


y

z u v x

allocation

(
addressing
) of
variables
:

3.14

2.0

15.9

3.0

shared

memory

for data:


LA 22 DI 23 J
W

6 AD
ch

SA 24 ST
0

SA
ch

ST
0

IR:

20

IC:

A
:

1

IR:


other


registers
:

Copy

to IR
the

content

of
address

indicated

by IC


If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then




IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then

execute

it

and IC:=IC+1

Copy

to IR
the

content

of
address

indicated

by IC


If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then




IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then

execute

it

and IC:=IC+1

MU 21

DI 23

3.14

15.9

Prześlij do

20

IC:

A
:


other


registers
:


processor

1


LA 20 MU 21 J
W

6 AD
ch

SA 24 ST 0 SA
ch

ST 0

1


0 1

2
3 4 5 6 7

Prześlij do


0
1 2 3 4 5 6
7

processor

2

ch
:

W

20

21
22 23 24


y

z u v x

allocation

(
addressing
) of
variables
:

3.14

2.0

15.9

3.0

shared

memory

for data:


LA 22 DI 23 J
W

6 AD
ch

SA 24 ST
0

SA
ch

ST
0

IR:

20

IC:

A
:

1

IR:


other


registers
:

Copy

to IR
the

content

of
address

indicated

by IC


If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then




IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then

execute

it

and IC:=IC+1

Copy

to IR
the

content

of
address

indicated

by IC


If

IR
contains

instruction

of:



unconditional

jump

then

IC:=address

part



conditional

jump

with

condition

satisfied

then




IC:=address

part
else


(
with

condition

unsatisfied
) IC:=IC+1



stop
then

IC:=address

part and


terminate

run



another

then

execute

it

and IC:=IC+1

MU 21

DI 23

6.28

5.3

Prześlij do

20

IC:

A
:


other


registers
:


processor

1


LA 20 MU 21 J
W

6 AD
ch

SA 24 ST 0 SA
ch

ST 0

2


0 1

2
3 4 5 6 7

Prześlij do


0
1 2 3 4 5 6
7

processor

2

ch
:

W

20

21
22 23 24


y