Chapter 3 : Fabrication of CMOS Integrated Circuits - PSNA CET ...

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Oct 7, 2013 (5 years and 6 months ago)


Chapter 3

: Fabrication of CMOS Integrated Circuits

This section gives an overview of the integrated circuit technology. Semiconductor devices and circuits are formed in
thin slices of a material (called a wafer) that servers as the substrate. For pro
per operation of the device/circuit, the
substrate material must have crystalline structure where all the atoms are aligned in a specific pattern. In the first
section of this chapter, the structure and growth of crystals are discussed. The next section de
als with the cleaning of
wafers which is an important step in the fabrication of integrated circuits. One of the basic building blocks in integrated
circuit processing is the ability to deposit thin films of material. A large number of deposited films by w
ide variety of
techniques are used in integrated circuits. These films can either be grown on semiconductor or deposited by various
techniques. Most films can be formed by more than one method. Thermal Oxidation of Silicon is taken up first because it
is a
n important step which is often repeated throughout the IC fabrication. This is followed by other principal film
deposition techniques such as vacuum evaporation, sputtering and chemical vapor deposition. The properties of the
films or substrate can be mod
ified by process like diffusion and ion implantation and they enables to form a variety of
devices in integrated circuits. A brief description of diffusion and implantation process and systems are given in section
4. In the subsequent section the lithograp
hy process is treated. The basic approaches to CMOS fabrication such as the
well, the n
well, the twin tub and silicon on insulator processes are discussed in section 6. Very brief discussion on the
fabrication of passive components also included. This c
hapter ends with a discussion on latch up and technology related
CAD issues. In summary, an integrated circuit process is usually a structured sequence of operations such as the ability
to deposit/modify thin films on the substrate, to apply a patterned ma
sk on the films by photolithographic process, and to
etch the films selectively to form actual devices.

3.1 Crystals and Growth

The basic semiconductor materials used in chips are crystalline silicon. This section briefly discuss about the properties

semiconductor crystals and how silicon crystals are grown.

3.1.1 Crystals

Solid materials are classified by the way the atoms are arranged within the solid. Materials in which atoms are placed at
random are called amorphous. Materials in which atoms a
re placed in a high ordered structure are called crystalline.
crystalline materials are materials with a high degree of short
range order and no long
range order. These
materials consist of small crystalline regions with random orientation called grai
ns, separated by grain boundaries.
There three arrangements are summarized in Fig.3.1.

Fig.3.1: Arrangements o
f atoms in solids

The crystal can be thought of as consisting of two separate parts: the lattice and the basis. The lattice is an ordered
arrangement of points in space, while the basis consists of the simplest arrangement of atoms which is repeated at
ery point in the lattice to build up the crystal structure. Fig.3.2 illustrates the basis and lattice in a crystal.

Fig.3.2 : Illustration of basis and lattice in a crystal

A crystal structure is composed of a unit cell, a set of atoms arranged in a particular way and is periodically repeated in
three dimensions on a lattice. The unit cell is given by its lattic
e parameters, the length of the cell edges and the angles
between them. In 1848, Auguste Bravais demonstrated that there are in fact only fourteen possible point lattices and no
more. In a cubic system, the lattice parameter is the side length of a cube an
d angles between the edges are 90. The
cubic lattices are an important subset of these fourteen Bravais lattices since a large number of semiconductors are
cubic. The three cubic lattices are the simple cubic lattice, the body
centered cubic lattice and th
e face
centered cubic
lattice as shown in Fig.3.3. The positions of the atoms inside the unit cell are described by the set of atomic positions (x,

y, z) measured from a lattice point.

Fig.3.3 : Atomic arrangements in a basic cubic cell

In Simple Cubic (SC) structure, atoms lie on the corners of a cube as shown in Fig. 3.3a. Very few crystals exhibit this
. For example polonium exhibits this structure over a narrow range of temperatures. In this structure each atom
has six equidistant nearest neighbors.

In Body centered Cubic (BCC) structure, structure atoms lie on the corners of a cube with an additional
atom at the
centre of the cube as shown in Fig. 3.3b. Its atomic positions are (000), (100), (010), (001), (101), (110), (011), (111)
and (

). Metals like Molybdenum, tantalum (Ta) and tungsten (T), iron (Fe), Platinum (Pt), Sodium (Na)
and Potassium (K) have this structure. In this structure each atom has eight nearest neighbours. By p
lacement of an
atom at the center of the cube, the body
centered cubic structure has twice the atom density of the simple cubic lattice.

In Face centered Cubic (FCC) structure, atoms lie on the corners of a cube with additional atoms at the centers of eac
cube face as shown in Fig. 3.3c. Its atomic positions are (000), (100), (010), (001), (101), (110), (011), (111), (
0), (
, 0,
), ( 0,
, 0), (
, 1,
, 0) and (1,
). In this structure each atom has
twelve equidistant nearest neighbours. Due to its low energy, FCC is extremely common and the examples are lead
(Pb), aluminum (Al), cop
per (Cu), and gold (Au).

Metals which are BCC (like chromium) usually harder and less malleable than close
packed metals such as gold. When
the metal is deformed, the planes of atoms must slip over each other, and this is more difficult in the BCC structur

Fig.3.4 : Diamond Structure

The most common crystal structure among frequently used semiconductors such as

silicon and germanium is the
diamond lattice, shown in Fig.3.4. Each atom in the diamond lattice has a covalent bond with four adjacent atoms, which
together form a tetrahedron as given in Fig.3.4b. The tetrahedral radius of the silicon atom is 1.18 Å. Th
e misfit factor of
an impurity atom shows whether it is smaller or larger than the silicon atom. The diamond lattice can also be formed
from two face
cubic lattices, which are displaced along the body diagonal of the cube by one quarter of that
dy diagonal as shown in Fig.3.4c. The violet color atoms are from the second FCC lattice.

Fig.3.5 : Zincblende
(ZnS) Structure

Compound semiconductors such as GaAs and InP have a crystal structure that is similar to that of diamond. However,
the lattice contains two different types of atoms. This structure is referred to as the zinc
blende lattice, named after zinc
blende (ZnS) and is shown in Fig.3.5, where the two different colors are showing different elements.

Another important geometric feature of a crystal structure is the nearest distance between atom centers (often called the
neighbor distance). Th
is distance is

for the SC lattice,
(half of a body diagonal) in the BCC lattice,

(half of a face diagonal) for the FCC lattice.

Example 1:

Calculate the maximum fraction of the volume in a simple cubic crystal occupied by th
e atoms. Assume that
the atoms are closely packed and that they can be treated as hard spheres. This fraction is also called the packing

The atoms in a simple cubic crystal are located at the corners of the units cell, a cube with side
. Adjacen
t atoms touch
each other so that the radius of each atom equals
. There are eight atoms occupying the corners of t
he cube, but only
one eighth of each is within the unit cell so that the number of atoms equals one per unit cell. The packing density is
then obtained as follows:

Note that in the case of a SC, about half the volume of the unit cell is occupied by the atoms. The packing density of
four cubic crystals is listed in the Table 1.

Table1 : The packing density of four cu
bic crystals


Atoms/unit cell

Packaging density

Simple Cubic


Body centered Cubic


Face centered Cubic




All latt
ice planes and lattice directions are described by a mathematical description known as a Miller Index. In the cubic
lattice system, the direction [hkl] defines a vector direction normal to surface of a particular plane (hkl). Miller indices
to the crystallographic axes of a crystal. Cubic lattices need only three axes and they correspond to the x, y,
z, axes in cubic lattice structures.

Fig.3.6 Intersections of a plane on the

Intersections of a plane and the
axes, as shown in figure 3.6, are used to determine the Miller indices of the
plane. The Miller Indices h, k, l ar
e obtained as follows:

Determine the points at which a given crystal plane intersects the three axes, for example at (a, 0, 0), (0, b, 0), (0, 0, c)
If the plane is parallel an axis, it is said to intersect the axis at infinity.

The Miller index for the

face is then specified by (1/a, 1/b, 1/c), where the three numbers are expressed as the smallest
integers (common factors are removed). Negative quantities are indicated with an over bar.

Example 2:

A plane intersects the crystallographic axes at (2, 0,
0), (0, 3, 0), (0, 0, 4).

Step 1:
(1/2, 1/3, 1/4); multiply by 12 to express as smallest integers.

Step 2:

(6, 4, 3) are the Miller indices. This is a (643) plane.

The (110) is the plane intersects the crystallographic axes at (1,0,0), (0,1,0) and (0, 0,

). z=infinity means that this
plane does not intersect the z axis.

Use the [ ] notation to identify a specific d
irection (i.e. [101]).

Use the < > notation to identify a family of equivalent directions (i.e. <110>).

Use the ( ) notation to identify a specific plane (i.e. (113)). Use the { } notation to identify a family of equivalent plane
(i.e. {311}).

A bar ab
ove a index is equivalent to a minus sign.

Fig.3.7: Different crystallographic planes in a cubic system

.7 shows the different crystallographic planes in a cubic system. The separation between adjacent planes in a
cubic crystal is given by

The separation between set of (111) planes is the smallest compared to {110} and {100}.

For cubic crystals, the angle,
between two planes, ( h



) and ( h



) is given by:

Example 3:

the angle between the (111) and (200) planes.

From the above equation,

which produces the result,
= 54.75

In a similar way one can find the angle between any planes and the values of most common planes are summarized in
the Table 2.

Table 2 : The angle between planes in cubic crystals

























Linear density of atoms can be defined as number of atoms centered on a direction vector / length of direction vector.
Similarly planar density of atoms is number of atoms c
entered on a plane / area of plane. Linear density and planar
density are important considerations during deformation and "slip"; planes tend to slip or slide along planes with high
planar density along directions with high linear density. Based on these v
alues {111} planes have the following unique

The crystal growth is easiest

The chemical etching is slowest

Tensile strength is highest

Modulus of elasticity is highest

It is the typical cleavage plane

Cross sectional view

Top View

Fig. 3.8 : V
groove etching in (100) silicon showing the exposed {111} sidewal

An anisotropic wet etch on a silicon wafer creates a cavity with a trapezoidal cross
section as shown in Fig. 3.8. The
bottom of the cavity is a <100> plane, and the sides are <111> planes. The white material is an etch mask, and the grey
material is s
ilicon. The angle between (111) planes and (100) surface is 54.7° as calculated before and the etching
stops at (111) planes at this angle resulting a V

Example 4


Calculate the density of Si from the lattice constant, atomic weight, and Avogadro
's number. Recall:
Avogadro's number (6.02 × 10

) is the number of molecules/atoms in a gram molecular weight of a substance. Lattice
constant = a = 5.43 x 10


How many Si atoms in the diamond cell?

8 corner atoms x (1/8) = 1

6 face atoms x (1/2)
= 3

+ 4 interior atoms = 4

Total 8 atoms/unit cell

The number of atoms/cm

= 8/a

= 8 / (5.43 X 10


= 4.996 x 10


If 6.02 x 10

silicon atoms make 28.1g; then 4.996 x 10

atoms should weigh 2.332 g. Thus the density of silicon is
2.332 g/cm

Up to the 150 mm wafer diameter era, wafers had flats, and the flats indicate the following information:


The doping type of the wafer (n

or p


The orientation of the wafer: {100} or {111}

And wafers with diameters larger than 200 mm
generally will have no flat at all, but just a small "notch" as shown
in Fig. 3.9.

Fig. 3.9 Identification of w

By measuring the sign of the thermo voltage between a hot tip (a soldering iron) and a room
temperature tip pressed on
the wafer can indicate whether the wafer is n

or p

The breaking (cleaving) of wafer indicate the orientation of a wafer; e
.g. {100} wafer pieces will be rectangular.

In this section we have studied about different types of cubic crystal structures, packing densities, various crystal planes
and directions, miller indices etc. In the next section we will study how the crystals
are made.

3.1.2 Crystal Growth

Integrated circuits are built on single
crystal silicon substrates that possess a high degree of chemical purity, a high
degree of crystalline perfection, and high structure uniformity. Such silicon crystal preparation invol
ves two major steps:
(1) refinement of raw material (such as quartzite, a type of sand) into electronic grade polycrystalline silicon (EGS) and
(2) growing of single
crystal silicon from this EGS either by Czochralski or Float Zone process.

Fortunately, t
he raw Si is abundantly available from steel industry and only a small part of it only required for the
semiconductor industry. Since it is a byproduct from steel industry, it is commonly called Metallurgical Grade Silicon
(MGS). MGS is poly crystalline ma
terial with a purity of about 99%. It is made by the reduction of SiO

(quartz sand) with
carbon (coal) in huge furnaces lined with carbon, with big graphite electrodes inside (carrying huge amounts of current)
at about 2000°C. The reaction is

C (s) + SiO


Si (l) + CO (g)

But care should be taken to suppress the other reaction occurring simultaneously (Si + C
SiC), which will not only
reduce the yield of Si, but clog up the furnace by SiC.

The 9N purity (99.9999999) silicon i
s made essentially in three steps:

Liquid Si reacts with all substances and is a universal solvent. This makes crystal growth from liquid Si somewhat
difficult. Si is converted to SiHCl

via the reaction at around 300°C

Si (s) + 3HCl (g)

(g) + H

(g) + heat

The resulting Trichlorosilane is already much purer than the raw Si; it is a liquid with a boiling poin
t of 31.8°C.

The SiHCl

is further distilled, resulting in extremely pure Trichlorosilane.

Finally, high
purity Si is produced by a "Chemical Vapor Deposition" (CVD) process (discussed in later sections) .

Often very small but precisely measured amounts of As, P or B can also be incorporated into the growing polysilicon.

The next step is to convert this poly

to a single crystal. There are two methods for crystal growth used in this case;
Czochralski or crucible grown crystals (CZ crystals) and Float zone (FZ) crystals. The FZ method produces crystals with
the highest purity, but is not easily used at large di

Czochralski or crucible (CZ) method of crystals growth

The Czochralski method, invented by the Polish scientist J. Czochralski in 1916, is the method of choice for high volume
production of Si single crystals. A schematic drawing of a crysta
l growth by Czochralski method is given in Fig.3.10.

Fig.3.10 Czochralski method of crystal growth

, a crystal is "pulled" out of a vessel containing liquid Si as shown in Fig 3.10. A seed crystal is dipped into
the liquid and is subsequently slowly withdrawn from the melt. The pulling rate (usually a few mm/min) and the
temperature profile determines t
he crystal diameter that can achieved. The solubility of impurity atoms in the melt is
larger than in the solid. As a result, the crystal will be cleaner than the liquid and crystal growing is simultaneously a
purification method. However the distribution
of impurities vary along the length of a crystal and a homogeneous doping
is difficult to achieve.

Practically only As, P, and B is used for doping because of their segregation coefficient is close to 1. The segregation
coefficient in thermodynamic equil
ibrium gives the relation between the concentration of impurity atoms in the growing
crystal and that of the melt. It is usually much lower than 1 because impurity atoms prefer to stay in the melt.

Oxygen is the most important impurity found in silicon a
nd is from the quartz crucible in which the molten silicon is
contained. The oxygen is typically at a level of about 5x10


in CZ silicon. Oxygen has three principal
effects in the silicon crystal. In an as
grown crystal, the oxygen generally
occupies interstitial positions in the silicon
lattice and improves the yield strength by 25%. A small amount of the oxygen in the crystal forms SiO

complexes and
act as donors. Even 10


donors can be formed, which is significant to increase the res
istivity of lightly doped P
type wafers. During the CZ growth process, the crystal cools slowly through ~500°C temperature and oxygen donors

Typically annealing of the grown crystal is carried at temperatures above 500°C and to remove these oxygen
mplexes. The oxygen can precipitate under normal device processing conditions, forming SiO

regions inside the
wafer. The precipitation arises because the oxygen was incorporated at the melt temperature.

Carbon is another impurity normally present in CZ
grown silicon crystals. The carbon comes from the graphite
components in the crystal pulling machine. For some applications, it is important to have even lower concentrations of
impurity atoms like Oxygen and the Float Zone Crystal Growth is used.

Float Z
one Crystal Growth

The basic idea in float zone (FZ) crystal growth is to move a liquid zone through the material as shown in Fig.3.11. In
this process the end of a long polysilicon rod is locally melted and brought in contact with a single crystalline S
seed. The melted zone slowly migrates through the poly rod leaving behind the final perfect crystal. In the float zone
process, dopants and other impurities are rejected by the growing silicon crystal. Impurities tend to stay in the liquid and
ing can be accomplished, especially with multiple passes. Since the melt never comes into contact with anything
but vacuum (or inert gases), there is no incorporation of impurities by dissolving the crucible material as in the CZ
crystal growth method. FZ
crystals therefore are always used when very low oxygen concentrations are required. One
needs to keep the liquid Si from just collapsing by surface tension and this limit the maximum diameter of crystals. A
summary of the CZ and FZ growth methods are give
n in Table 3.

Fig.3.11: Float Zone (FZ) method of crystal growth

Table 3 : Comparison of the CZ and FZ Growth




Growth Speed (mm/min)

1 to 2

3 to 5




Consumable Material Cost



Down Times



Axial Resistivity Uniformity



Oxygen Content (atoms/cm




Carbon Content (atoms/cm




Metallic Impurity Content



Bulk Minority Charge Carrier Lifetime (s




Production Diameter (mm)



Conversion of silicon ingots into polished
wafer is carried out by shaping, slicing, lapping and edge grind, etching,
polishing and cleaning operations. For many applications, the quality of a polished wafer is not sufficient mainly due to
defects generated during crystal growth in the bulk of the
wafer. The best solution to this problem is to deposit an
additional layer of high purity Silicon on the top of a polished wafer substrate. This process is known as epitaxy. This
has the additional advantage in that the electrical resistivity of the surfac
e layer can be different than that of the

Silicon Epitaxial Growth Process

Silicon epitaxial deposition (epitaxy) refers to the process of growing a thin layer of single
crystal silicon over a single
crystal silicon substrate. Epitaxy is diffe
rent from the Czochralski process in that the crystal can be grown below the
melting point. In semiconductors, the deposited film is often the same material as the substrate, and the process is
known as homo
epitaxy. An example of this is silicon depositio
n over a silicon substrate. If the layer and substrate are of
different materials such as Al

As on GaAs, the process is termed as hetero
epitaxy. Epitaxy can be achieved by
molecular beam epitaxy (MBE) method where the physical transport of material
is carried out to a heated substrate. In
chemical vapor deposition (CVD), materials such as Si, Ga, As, dopants etc. are transported in the form of volatile
compounds to the substrate, where they react to form the epitaxial layer.

There are four major chem
ical sources of silicon for commercial epitaxial deposition: (1) silicon tetrachloride (SiCl
), (2)
trichlorosilane (SiHCl
), (3) dichlorosilane (SiH

) and (4) silane (SiH
). The over
all reaction for silicon epitaxy by
silane reaction may be written a
s follows:

The growth of an epitaxial layer over the substrate offers some advantages. By growing a lightly doped
epi layer over a
doped silicon substrate, a higher breakdown voltage across the collector
substrate junction is achieved while
maintaining low collector resistance. Lower collector resistance allows a higher operating speed. By fabricating the

device on a very thin (3
7 µm) lightly doped epi layer grown over a heavily
doped substrate, latch
up occurrence
is minimized. Aside from improving the performance of devices, epitaxy also allows better control of doping
concentrations of the devices. The

layer can also be made oxygen

and carbon
free. The disadvantages of epitaxy
include higher cost of wafer fabrication, additional process complexities, and problems associated with defects in the epi

In this section we have studied about the cryst
al structure, how it was grown and converted to wafers. The next section
discusses the importance of wafer cleaning and different methods used to remove contaminations.

3.2 Cleaning and Etching of wafers

Surface of semiconductor wafer gets contaminated
during device processing. The source of contaminants are ambient
air, storage ambient, process gases, chemicals, materials, water etc which are used in the fabrication processes.
Processing tools as well as personnel operating in the clean

rooms are also
sources of contamination. The most
prevalent contaminants are particles and they may cause a catastrophic failure during device manufacturing process.
The measure of the air quality of a clean room is described in Federal Standard 209. Clean rooms are rate
d as Class
10K, where there exist no more than 10,000 particles larger than 0.5 microns in any given cubic foot of air; Class 1K,
where there exists no more than 1000 particles; and Class 100, where there exist no more than 100 particles. These
small parti
cles are controlled in a clean
room by using High Efficiency Particulate Air (HEPA) filters.

Another type of contaminants which degrade the devices are metallic contaminants originate primarily from liquid
chemicals, water and process tools. The most comm
on metallic contaminants are iron (Fe), aluminum (Al), copper (Cu),
nickel (Ni) as well as ionic metals such as sodium (Na) and calcium (Ca). Organic contaminants are present in ambient
air, storage containers and can arise from photoresists. Organic compo
unds readily adsorb surfaces adversely affect
device properties. Native oxides as well as moisture from the ambient air or wet processes adversely affect the devices
and can be considered as a contaminant and its removal is a part of cleaning process.

total elimination of contaminants is not possible, methods of semiconductor surface cleaning are employed
throughout the device manufacturing sequence. The cleaning can be achieved by a chemical reaction with a reactant
and contaminant on the surface, by t
he physical interaction between cleaning ambient and the surface, the momentum
transfer between high kinetic energy particles directed toward the contaminant etc. In Wet Cleaning, contaminant is
removed via selective chemical reaction in the liquid
phase b
y its dissolution in the solvent, or its conversion into the
soluble compound. Typically, process is enhanced ultrasonic agitation. In Dry Cleaning, contaminant is removed via
chemical reaction in the gas phase converting it into a volatile compound. Wet c
leaning is the dominant cleaning
technology in semiconductor device manufacturing. Wet cleans use combinations of acids and solvents, oxidize, etch,
and scrub contaminants from the wafer surface. An integral part of every wet cleaning scheme is rinses in u
deionized (DI) water which stops chemical reaction on the wafer surface and washes off reactants and reaction
products. Wet cleaning is always completed with a wafer drying process.

RCA clean Wet cleaning recipes were first proposed over 30 yea
rs ago presents a complete cleaning process to
remove from the surface heavy organics, particles, and metallic contaminants as well as native/chemical oxide.
Typically the first step is to remove organic contamination remaining on the surface. The H


solution at
130°C, also known as SPM (Sulfuric Peroxide Mixture), or "piranha" clean. NH
OH : H

: H
O mixture 1:1:50,
at temperature ~ 70°C with ultrasonic agitation is used to remove particles.

This Ammonium hydroxide
hydrogen Peroxide Mixtu
re (APM) is also known as Standard Clean 1 (SC1 or RCA 1). To
remove metallic contamination, HCl: H

: H
O mixture is used. This Hydrochloric acid

hydrogen Peroxide
Mixture (HPM) is also known as Standard Clean 2 (SC2 or RCA 2). Dilution and bath

temperature are similar to APM.
Native/chemical oxide etch is carried out in diluted HF:H
O solution at the ratio of 1:100 or weaker. Thin films are very
fragile and material loss also can result by such very resourceful and time consuming cleaning proces
ses. In practice it
is simplified by less aggressive cleans. In many applications a sequence involving just one cleaning step followed with
D.I. water rinse and dry is enough.

In a dry cleaning technology, removal of contaminant fro m the surface takes pla
ce via chemical reaction in the gas

phase converting it into a volatile compound. Gas sources like O
, H
, CO
, Ozone, SiCl
, HCl, are used for dry
cleaning. Methods like Laser, Sputtering etc are based momentum transfer between specie impinging on the su
phase cleaning methods lack a shear chemical and physical strength of liquid cleaning ambient. However gas
phase surface processing methods are fully capable of controlling organic contamination.


Etch is a process that removes unwanted
materials from the surface of a substrate by various dry and wet techniques.
These techniques are used to remove silicon dioxide, silicon nitride, polysilicon, aluminum, tungsten, contamination
particles, and other layer materials. This process step create
s the layer definition that is based on the outcome of a
previous photolithography process step. These etch processes transform a single layer of semiconductor material into
the patterns, features, lines, and interconnects.

Fig. 3.12 :Etching profiles before and after the pro

A typical etching profile is given in Fig. 3.12. In this case the red region is the mask
(protective layer) used, blue layer is
to be removed selectively from regions not protected by mask and grey layer is the substrate which should not be
etched. The profile after the etching indicates that there is a horizontal etching as well etching of un
derlying substrate.
Selectivity is the characteristic of etch whereby the desired layer is etched without damaging the underlying or masking
layers. The etching system's ability to do this depends on the ratio of etch rates in the two materials. The select
ivity can
be quantified as:

Anisotropy is the characteristic of etch whereby the desired layer is etched in one
direction only. The degree of
anisotropy can be quantified as:

In the above figure dimension 'x' shows the degre
e of anisotropy, 'y' shows the lack of selectivity with respect to the
underlying layer and 'z' shows the lack of selectivity with respect to the masking layer.

A poorly selective etch removes the desired layer, but also attacks the underlying material.

A highly selective etch leaves the underlying material unharmed.

A perfectly isotropic etch produces round sidewalls.

A perfectly anisotropic etch produces vertical sidewalls

The wet etching processes used liquid
phase ("wet") etchants. The wafer is imme
rsed in a bath of etchant, which must
be agitated to achieve good process control. For instance, buffered hydrofluoric acid (HF) was used commonly to etch
silicon dioxide over a silicon substrate. Wet etchants are usually isotropic, which leads to undercut
s when etching thick
films. They also require the disposal of large amounts of toxic waste. For these reasons, they are seldom used in state
art processes.

Modern VLSI processes avoid wet etching, and use plasma etching instead. The plasma produces

energetic radicals,
neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this
process is isotropic. The source gas for the plasma usually contains small molecules rich in chlorine or fluorine
. For
instance, carbon tetrachloride (CCl
) etches silicon and aluminium, and trifluoromethane etches silicon dioxide and
silicon nitride. A plasma containing oxygen is used to oxidize ("ash") photoresist and facilitate its removal.

In Ion milling, or spu
tter etching, lower pressures, energetic ions of noble gases, often Ar+, bombards the wafer with
which knock atoms from the substrate by transferring momentum. Because the etching is performed by ions, which
approach the wafer approximately from one direct
ion, this process is highly anisotropic. On the other hand, it tends to
display poor selectivity. Reactive
ion etching (RIE) operates under conditions intermediate between sputter and plasma.
Deep reactive
ion etching (DRIE) modifies the RIE technique to p
roduce deep, narrow features.

The fabrication of an integrated circuit involves a sequence of processes that may be repeated many times before a
circuit is complete. In this section, we have discussed about the first step involved in semiconductor device

i.e. the cleaning of wafers. Briefly we also have studied about the etching of thin films. Generally, the next step involved
is oxidation of the wafer surface and is discussed in the next section.

3.3 Thermal Oxidation of Silicon

The oxide o
f silicon, or silicon dioxide (SiO
), is one of the most important ingredients in integrated circuits. Thermal

is amorphous. It has a density of 2.2 gm/cm

and molecular Density of 2.3x10


. The crystalline

is also possible and kno
wn as Quartz has a density of 2.65 gm/cm
. SiO

has excellent properties which makes
them necessary in every part of the integrated circuits. It is an excellent electrical insulator having energy gap ~ 9 eV
with a resistivity greater than 10 20 ohm
cm and
breakdown electric field greater than 10MV/cm. Si technology became
popular because of the stable and reproducible Si/SiO

interface. Conformal oxide growth on exposed Si surface is
easily possible. SiO

is a good diffusion mask for common dopants such as.

B, P, As, Sb. In addition there exists good
etching selectivity between Si and SiO

The formation of SiO

on a silicon surface is most often accomplished through a process called thermal oxidation. As its
name implies, is a technique that uses extremely

high temperatures (usually between 700
1200°C) to promote the
growth rate of oxide layers whose thicknesses range from 20 to 10000 angstroms. During the process, silicon substrate
is exposed to a high purity oxidizing species like oxygen gas (dry oxidatio
n) or water vapour (wet oxidation).

The chemical reaction at the silicon surface for dry and wet oxidation is given as

Oxidation of silicon is not difficult, since silicon has a natural inclination to form a stable oxide even at room temperatur
as long as an oxidizing ambient is present. In both cases the oxidizing species diffuses through the growing oxide and
acts with the silicon surface. These oxidation reactions occur at the Si

interface, i.e., silicon at the interface is
consumed as oxidation takes place. As the oxide grows the Si

interface moves into the silicon substrate. As a
result, the Si

interface will always be below the original Si wafer surface. The SiO

surface, on the other hand, is
always above the original Si surface. SiO

formation therefore proceeds in two directions relative to the original wafer
surface as shown in Fig.3.12.

Fig. 3.13 : The silicon
silicon dioxide interface in thermal oxides

The amount of silicon consumed by the f
ormation of silicon dioxide is also fairly predictable from the relative densities
and molecular weights of Si and SiO
, i.e., the thickness of silicon consumed is 44% of the final thickness of the oxide
formed. Thus, an oxide that is 1000 angstroms thick
will consume about 440 angstroms of silicon from the substrate. In
another words, 1µm thick Si oxidizes to 2.17 µm thick SiO

Thermal oxidation is accomplished using an oxidation furnace which provides the heat needed to elevate the oxidizing
ambient tem
perature. A furnace typically consists of a temperature controlled heating system, fused quartz process
tubes, arrange for controlled flow of various gases. The heating system usually consists of several heating coils that
control the temperature around th
e furnace tubes. The wafers are placed in quartz glassware known as boats. A boat
can contain many wafers. The oxidizing agent (oxygen or steam) then enters the process tube through its source end,
subsequently diffusing to the wafers where the oxidation o

During dry oxidation, the silicon wafer reacts with the ambient oxygen, forming a layer of silicon dioxide on its surface. In

wet oxidation, the water is heated in the 40
80°C range and oxygen or nitrogen carrier gases are used for the flow of
er vapors to the chamber. Alternatively hydrogen and oxygen gases are introduced into a torch chamber where they
react to form water molecules, which are then made to enter the reactor where they diffuse toward the wafers. The
water molecules react with th
e silicon to produce the oxide and another byproduct, i.e., hydrogen gas.

Kinetics of SiO

The Linear and Parabolic growth laws were developed by Deal and Grove, and are known as the Linear Parabolic
Model. This oxide growth model has been empiri
cally proven to be accurate over a wide range of temperatures (700
1300°C), oxide thicknesses (300
20,000 angstroms), and oxidant partial pressures (0.2
25 atmospheres).

Fig.3.14 and 3.15 pictures various diffusions possible and the concentration of speci
es during thermal oxidation and is
the basis for Deal and Grove model.

Fig. 3.14 : A Model for thermal oxidat
ion of silicon indicating various diffusions possible

Fig. 3.15 : A Model for thermal oxidation of silicon i
ndicating the concentration of species

The gas
phase flux F

is proportional to the difference between the oxidant concentration in the bulk of the gas (C
) and
the oxidant concentration adjacent to the oxide surface (C

The Fick's law of solid sate diffusion states that


is the mass transfer constant (cm/s),D is the diffusion coef
ficient (cm

is the surface reaction transfer constant
(cm/s), Using
PV = NkT
, Henry's law to relate C

nd C


is the Henry's constant and P

is the partial pressure of oxidant gases at surface

If the equilibrium concentration of oxidizing species in oxide is

, at steady state

Solving these two equations for two unknowns

To convert
into oxide thickness growth rate

Where N

is the oxidant molecules per unit volume required to form a unit volume of SiO
. N

is 2.3 x 10


for dry
oxidation and 4.6 x10


for wet oxidation. Taking boundary conditions as

= x

. The oxide thickness grown
at any point of time

is modeled as
where A and B constants.

The time displacement
is included to account for the oxide layer (at
t = 0
) formed by the accelerated growth in the
initial phase of oxidation.

Fig.3.16 : oxide thickness ver
ses time

Typical oxide thickness verses time dependency is shown in Fig.3.16. For small values of

, the oxide growth equation
can be approximated as

and thus
is known as linear rate constant. For large values of

, the above eq
can be approximated as

and thus B is known as parabolic rate constant. That is oxide thickness growth slows
down with increase in oxide thickness and can be readily seen from:

Fig.3.17 Wet and Dry oxide growth rate for Silicon

Dry oxidation of silicon is typically used to grow a thin, high quality oxide that is used in transistor

gates and capacitors.
Oxide grown in dry oxygen ambient has excellent insulating properties and is denser, free of defects. Wet oxidation of
silicon is typically used to grow thick oxides that are used as diffusion barriers. Silicon dioxide acts as an eff
ective mask
against many impurities, allowing dopants into silicon only in regions that are not covered with oxide.

The oxide thickness grown on silicon is dependent on the oxidation time and temperature. Wet oxidation method offers
faster growth rate comp
ared to dry oxidation. The linear and parabolic rate constants have larger values in wet oxidation
case than in case of dry oxidation. This is because equilibrium concentration of oxidizing species in oxide (
) is
approximately three orders of magnitude greater for water than in dry oxygen. Therefore, for growing thick oxide within a
realistic time, wet oxidation is a
better choice.

The linear and parabolic rate constants increase with temperature in both dry and wet oxidation methods.

increases in
both cases through the diffusion coefficient (
) increase due to temperature. The reason for increase in
is through

It can be seen that for small duration, the oxidation is a reaction controlled process and longer duration it is a diffusion
controlled process.

From the Deal and grove model, we have seen that
the oxide growth rate is affected by time, temperature, and
pressure. Thickness of oxide is raised by an increase in oxidation time, oxidation temperature, or oxidation pressure.
Other factors that affect thermal oxidation growth rate for SiO

include: the

crystallographic orientation of the wafer; the
wafer's doping level; the presence of halogen impurities in the gas phase and the presence of plasma during growth.

Example 5 :
A <100> silicon wafer has 400nm of oxide on its surface. In a subsequent proces
s, a portion of the oxide
was etched and the resulting cross section is shown below. How long will it take to grow an additional 1um of oxide over
the 400 nm existing layer in wet oxygen at 1100°C? The parabolic and linear rate constants at this temperatur
e are
0.5289 µm
/hr and 2.8952 µm/hr respectively. Plot the resulting cross section after the wet oxidation indicating the
silicon interface.

Given that

= 0.1827

From the equation

For an initial oxide thickness of 0.4
m, the corresponding
= 0.4407 hr

Now for an oxide thickness of 1.4
m, the corresponding
= 4.1893 hr

That is the time taken to grow an additional 1um of oxide over the 400 nm existing layer = 3.1893 hr

To calculate the oxide thickness in the region 2

= 1.3197

The resulting cross section after the wet oxidation is shown in Fig. 3.18 clearly indicating the oxide
silicon interfaces.

Fig. 3.18 : The Si

interface changes before and after thermal oxide growth


The anodic oxidation processes is usually carried out at room temperatu
re. Thus, impurity concentrations present in the
semiconductor are not altered during this process. As a result, anodic oxidation is a useful means for the controlled
removal of layers of silicon and gallium arsenide at room temperature, and is often used
as a diagnostic tool. This
technique can also be used to grow reasonably high quality oxides on gallium arsenide.

Anodic oxidation or anodization, is carried out by placing the semiconductor in an electrolytic cell, as shown in Fig.3.18,
where it is conne
cted to the positive terminal of a power supply so that it serves as the anode. A noble metal such as
platinum is connected to the negative terminal of the supply, and serves as a cathode. A large variety of electrolytic
formulations can be used. The prima
ry oxidizing component of all of these is water, which dissociates into H

and (OH)


Fig. 3.19 : Schemati
c diagram of Anodic oxidation set up

Often a conductivity/pH modifier is added to this system to vary the resistance of the electrolyte as well as the
dissolution rate of oxide in it. It is also possible to carry out an anodisation process in a nonaqueous

solution. However,
the requirement of this electrolyte is that one of its dissociation products be the (OH)


ion. Reactions leading to anodic
oxidation of silicon are as follows:

Water in the electrolyte medium dissociates into H


and (OH)


The difference in electrochemical potentials between silicon and the electrolyte results in charge transfer from silicon

until equilibrium is established. This leaves the surface layer partially depleted of electrons. During anodisation, holes
are supplied from the bulk of semiconductor to the semiconductor
electrolyte interface, thus promoting the silicon
surface atoms to
a higher oxidation state :

The Si

combines with (OH)

to form the hydroxide.


subsequently forms SiO

liberating hydrogen in the process,

The overall reaction is given by

In the absence

of an external battery (or illumination), the continuous supply of holes to the reaction interface ceases.
The concentration of the thermally generated holes is insufficient for the formation of SiO

beyond a few monolayers.
However, the battery provides
the necessary holes for this anode reaction that sustains the process of oxide growth.
The H
drifts to the cathode, where it is evolved as molecular hydrogen by the addition of electrons

The anodic oxidation of p
type material is relatively straightforward since there is no problem with delivering holes to the
semiconductor surface by means of a battery. The situati
on is somewhat complex for n
type semiconductor. Here the
initial charge transfer from the semiconductor into the electrolyte creates a depletion layer in semiconductor, and a
barrier to the flow of holes. In effect, then, the electrolytic
semiconductor sy
stem behaves much like a Schottky diode
with the electrolyte serving the role of the metal. In order to sustain the process of oxide growth, provision is to be made
to supply holes to the semiconductor surface. One approach is to illuminate the sample to p
rovide these holes by photo
generation. Alternately, the anodisation cell can be operated at a voltage, which exceeds the Schottky diode breakdown
voltage, so that avalanche generated holes can allow the oxidation to proceed.

Anodisation can be carried ou
t using either a constant voltage source or a constant current source. In the case of
constant voltage source anodisation, the oxide thickness builds up towards a final value. The final thickness is
proportional to the applied voltage and typically the val
ue is about 0.3 nm/V for silicon. When the anodisation is carried
out from a constant current source, the oxide thickness varies linearly with time. In this case, the electric field across th
oxide is constant and the voltage drop across it increases with

time. The linear increase of voltage can be monitored
and the process can be stopped when the desired oxide thickness is reached.

Oxides formed by anodisation are generally porous in character, and have water incorporated in them. During the
anodic oxid
ation process, semiconductor material is transferred through the oxide to the electrolyte
oxide interface.
Thus, anodised oxide has an interface charge density about one order of magnitude larger than that of the conventional
thermal oxide. From the above
discussions on thermal oxidation and anodic oxidation of silicon, it is clear that thermal
oxidation results in better quality SiO

as well as a better Si

interface compared to anodic oxidation.

In this section we have studied thermal oxidation of si
licon and basic model which describes the oxidation process of
silicon. Briefly we have discussed about the anodic oxidation process also. In the next section we will take up the
methods by which films of various materials are deposited on silicon.

3.4 Th
in Film Deposition

Thin films play a vital role in virtually every micro

and nanostructure. The thin films consists of wide range of materials
systems such as conductors, insulators and semiconductors. Conductors such as metals and metal compounds are
sed for connecting transistors, for contacts and for device structures. It can be found that interconnection is much
harder than making transistors. Insulators are required for electrical isolation, as dielectrics for MOS structures and for
mask applicatio
ns etc. Semiconductors are essential to make transistors, diodes, resistors, capacitors and are used in
amorphous and polycrystalline forms for variety of applications such as solar cells, epitaxial layers and electrical
contacts etc.

Thin films made by
a variety of means. Deposition technology can be classified in two groups i.e. depositions that
happen because of a chemical reaction and that happen because of a physical reaction. Chemical Vapor Deposition,
Electrodeposition, Epitaxy, and Thermal oxidati
on exploit the creation of solid materials directly from chemical reactions
in gas and/or liquid compositions with the substrate material. In physical deposition technologies material is released
from a source and transferred to the substrate. The most com
mon examples are evaporation and sputtering.

Atomic separation in a solid is about 0.3nm. The thin film thickness can range from nanometers (monolayers) to
microns. Monolayers has high surface to volume ratio. Thin film properties are different from the b
ulk; however when
hundreds of atomic layers forms micron layers, their properties are similar to that of “bulk”. Typically there is a critical
thickness above which it behaves essentially as a bulk material. Variety of forms of thin films are possible base
d on their
crystal structure, grain size, composition, defects, electro

optical properties, adhesion, stress
resulted etc.

Gas Kinetics and Vacuum Technology

In order to understand deposition techniques, we must first know some basi
cs of gas kinetics and vacuum physics. The
vacuum ranges can be broadly defined as follows:


~ 0.1

760 torr (atmospheric pressure is 760 torr)


~ 0.1 to 10



~ 10

to 10



< 10


Table 4 : Pressure conversion table


Pascals (N/m



Torr (mm Hg)

psi (lb/in




1mbar =








1Pa =








1atm =








1Torr =








1psi =


























Fig. 3.20(a) : C
ross sectional diagrams of gas molecules enclosed in a cube and their kinetics (b) the volume
swept by one molecule between the collisions

To understand the kinetics of gas, let us consider a volume V of nitrogen gas in a cube of side L as shown in Fig. 3
Gasses are composed of a very large number of very small particles. They are very small compared to the distance
between particles. Particles are always moving rapidly in a straight line. Particles exert no forces except during

The distr
ibutions of their velocities obey Maxwell's distribution. Their r.m.s. velocity

is given by
where k = Boltzm
ann's constant, T = temperature of the gas (K) and m = mass of the molecule. For example hydrogen
molecule at room temperature has

of 1700m/sec.

The volume swept by one molecule between collisions can be expressed as
. How far does a molecule travel
between collisions?

Actually, we need to consider that
the molecules are moving. Clearly, what really counts in the collision rate is the
velocity of the molecules.

Defining the average velocity as the root mean

square velocity, if one molecule has

and another has
, then the square of the relative velocity
, s

average to zero, the relative directions being random.

So the average
of the relative velocity
is twice the
average square of the velocity, and therefore the average root
square velocity is up by a factor v2, and the
collision rate is increased by this factor.

Consequently, the mean free path is
by a factor of

= mean free path

d = diameter of a molecule

n = number per unit volume

For air at room temperature, the

mean free path can be expressed as:

P, the pressure is in torr and
will be in cm. Table 5 shows the mean free paths for various pressures.

Table 5 : Mean free paths at various Pressures


Mean Free Path

1 atm

x 10


1 torr

5 x 10


1 millitorr

5 cm


50 m



50 km

There are mainly two regimes gas flows, viscous and molecular flow regimes. In the case of viscous flow regime, the
mean free paths of particles are much less than t
he size of the system (D). In this regime, gas density (pressure) is high
enough gas
gas collisions dominate and molecules "drag" one another along in the flow. Collisions with walls will play a
secondary role only in limiting the gas flow. This regime typ
ically occurs when D (cm) P (Torr) > 0.5 for air at room

In the case of molecular flow gas density (pressure) is very low and typically occurs when D (cm) P (Torr) > 0.005 for air
at room temperature. The mean free paths of particles are muc
h larger than the size of the system (D). Only few
molecule collisions occur and molecule
chamber wall collisions dominate the flow process. The molecules
move independently of one another and are held back by walls.

In between these two regimes

when the mean free paths are comparable to size of system (D), a complicated
intermediate (transition) flow occurs. Sometimes the Knudsen number (K
) is used to distinguish between regimes. K

(dimensionless number) is ratio of the mean free path to the c
haracteristic dimension of the chamber (can be diameter
of a pipe, or vacuum chamber). When K
> 1 then it is the molecular flow regime. When K
< 0.01 it is the viscous flow
regime. In between, the flow characteristics are indeterminate.

The number of gas
molecules colliding with a surface each second is given by
= 0.25 n v

, where
is the collision
rate of gas molecules, n is the number of molecules per unit volume and v

is the average velocity of a gas molecule.
Expressing t
his equation in terms of things one can directly measure:


is in molecules/cm

sec, P is the pressure in torr, M is the molecular weight of the gas molecule and T is the
temperature in K. As an example, Nitrogen (N
) has a

molecular weight M = 28. In a chamber with nitrogen at room
temperature (293 K) and a pressure of 1 x 10

3.88 x 10

The time taken to form a single complete layer of gas on a surface is given by

here t

is the time to form a monolayer (in seconds), n = number of molecules per unit volume, v

is the average
velocity of the molecules and d is the diameter of a molecule. In case of air at room temperature, the expression
becomes: t

= 1.86 x 10
P, when P is the pressure expressed in torr.

Thin film depositions are carried out in high vacuum environment for achieving quality films. Vacuum pumps are used to
create vacuum in a sealed chamber where the film deposition takes place. A partial vacuum,

rough vacuum
, can be
created using a rotary pump. The vacuum pumps could be classified into two based on how the molecules are removed
from the chamber. In case of mechanical, turbo molecular and oil diffusion pumps, the molecules are physically
d from the chamber. However in case of cryo pumps and sputter/ion pump with Ti sublimation, the molecules are
adsorbed on a surface or buried in a layer. The mechanical pumps have moving parts and oil. They are used to pump
down from 1 atm pressure to roug
hing (medium) vacuum. Examples are Piston pumps (not used much due to particle
problems), Rotary vane pumps (majority of cheap applications) and Dry pumps. Turbo molecular pumps pump down
from 1 atm and are clean pumps. They also have moving parts and pump

speeds are low. Oil diffusion pumps have no
moving parts but based on oil in vacuum. Sputter/ion as well as cryo pumps are clean with no moving parts and are
used to pump down from 10


The deposition chambers for standard vacuum requirements 10

Torr use glass or stainless steel chambers. They
are usually diffusion pumped. The CVD , thermal evaporation, sputter deposition films have typically polycrystalline
quality. For ultrahigh vacuum (10

Torr) chamber requirements bakeable stainles
s steel is used. They are usually
ion and/or turbo pumped. The thermal evaporated and sputter deposited films have epitaxial (better) quality films.

Physical Vapor Deposition

As discussed previously, Physical vapor deposition ( PVD ) is a technique used
to deposit thin films of various materials
onto of semiconductor wafers by physical means, as compared to chemical vapor deposition. Evaporation, Sputter
Deposition and Pulsed laser deposition are examples of this method.

An evaporator uses a thermal or
beam heating to melt the material and raise its vapor pressure to a useful range as
shown in Fig. 3.21. This is done in a high vacuum, both to allow the vapor to reach the substrate without reacting with or
scattering against other gas
phase atoms in the

chamber. Only materials with a much higher vapor pressure than the
heating element can be deposited without contamination of the film.

Fig. 3.21 : Different methods used for melting the source in an evaporation system

Sputtering relies on a plasma (usually a noble gas, such as Argon) to knock material from a "target" a few atoms at a
time. Since the process is

not one of evaporation, the target can be kept at a relatively low temperature, making this one
of the most flexible deposition techniques. It is especially useful for compounds or mixtures, where different components
would otherwise tend to evaporate at
different rates. Pulsed laser deposition systems work by an ablation process.
Pulses of focused laser light vaporize the surface of the target material and convert it to plasma; this plasma usually
reverts to a gas before it reaches the substrate.


There are three basic types of kinetics in an evaporation process. The conversion of source material to gaseous state,
then the transport source atoms to substrate which is away at a distance h and finally the deposition atoms on
substrate. The detai
ls of each of these steps are described below:

Fig. 3.22: Conversion of source material to gaseous form


the first stage, as shown in Fig. 3.22 the gaseous state is achieved by heating the source so that its vapor pressure
) is greater than 10

torr. The evaporation is carried out in standard base vacuum pressures and the evaporation
rate (flux) can
be estimated from kinetic theory described in previous section. Some sources sublime from solid while
others evaporate from liquid. When source compounds are changed to vapor, it may break apart and produce films with
different stoichiometry. For example i
nstead of SiO
, one may end up with SiO
, where x < 2. Similarly, metal alloy
sources do not give same alloy in film; its components evaporate independently based on each separate vapor pressure
and the composition of alloy source also changes with time.

The source vapor transport to surface is a line of sight deposition. In a good vacuum environment, long mean free path
is achieved and thus collisions in gas can be avoided. For longer source to substrate distance, one needs higher
vacuums. Typically, for
a separation of 10 to 100 cm, a vacuum of 10

torr and lower are required. The particles have
energies (~kT) comparable to evaporation temperature and at 1000°C, it is about 0.2 eV.

The distribution of evaporant depends on geometry of source and on posi
tion of target. Point source and planar source
(surface Source) are considered in this section. The distribution of evaporant in the case of point source case is given in
Fig. 3.23. If the target of area dA

is tilted of from radial direction by an angle

projection of dA

onto sphere of radius r
is dA

as shown.

Fig. 3.23 : The distri
bution of evaporant in the case of point source

Consider a mass hitting dA

is dM

and M
, is the total evaporated mass,

From the equations, it can be seen that the distribution depends on
. However, planar sources are more pr

Fig. 3.24 : The distribution of evaporant in the case of planar source

Consider a source atoms encl
osed cell with an opening
as shown in Fig. 3.24. How many atoms reach the opening
travelling in the direction

If directions are random, volume of possible atoms coming out is
. The number of atoms headed in right
direction is given by

Integrating over time and source area we get

The last part of kinetics in an evaporation process is the deposition onto substrate and the film thickness (d) depends on

through dM/dA


Consider flat substrate perpendicular to source as shown in Fig. 3.25,

Fig. 3
.25 : The deposition of evaporant to a flat surface perpendicular to source

For this geometry:
, cos

= h/r , r = (h



and in general :

For a point source, the equation becomes


is the maximum thickness.

For a surface source, the equation becomes


When compared to a point source the surface source has slightly poorer thickness uniformity. For better uniformity, one
needs to decrease sample size (l) and increase distance to substrate (h). This situation calls for a possible in a bigger
amber and with better vacuum and it means that lot of evaporant is wasted. Better uniformity can also be improved by
the use of multiple sources, moving substrate during deposition and using rotating crucible to reduce evaporant near
center. If source and
substrate are kept on same sphere surface as given in Fig. 3.26, then the equations become

and the dependency on
or r on
is avoided.

Fig. 3.26 : Placement of source and substrate on a spherical surface

There are several sources of contamination in an evaporation scheme. Contamination occurs from source mater
source/substrate heaters and residual gas in chamber. One can have good film purity by using high purity source
materials, using low diffusion materials as source/substrate heaters, with better vacuum and higher deposition rate
materials . The e

process though expensive, is usually "better" than thermal evaporation because of less
contamination from the source holder. Only the desired material is heated and sustains high quality vacuum
environment. They are especially suitable for higher melting
point materials (T~3000°C). Higher deposition rates and
better control of deposition rates also makes e
beam an attractive choice. As shown in Fig. 3.27, the step coverage is
poor in evaporation methods because of shadow effects. By contrast, the CVD and s
puttering offer better step

Fig. 3.27 : Step coverage in an evaporation and CVD process


Sputtering is used in industry as a means of depositing both metals and insulators. During ion bombardment, energy
can be transferred from incoming ions to a surface at an appropriate rate such that atoms are physically removed from
the surface.
This section starts with an introduction to plasma. Sputter deposited film properties depend on the
parameters of the sputtering system, such as pressure and substrate bias. We will discuss the cause and effect of
sputtering parameters on deposition proces
ses and their relationship to film properties. The different sputtering systems
such as DC, RF and magnetron are also covered.

Sputtering is carried out in a plasma chamber. Plasma is the fourth state of matter. As we increase the heat added to a
it will eventually make phase transitions to the liquid state, become gaseous and then finally the bonds binding
electrons and ions are broken and the gas becomes electrically conducting plasma. Plasma is a gaseous collection of
ions, electrons, energetica
lly excited molecules, and a large number of neutral gas species, normally created by the
application of electromagnetic fields. Plasmas can be used to drive reactions that would otherwise be thermally
prohibited. Plasmas are used to deposit, chemically et
ch or sputter materials.

In the simplest case, plasma is formed by applying a potential difference (of a few 100 V to a few kV) between two
electrodes that are inserted in a cell (or that form the walls of the cell). The cell is filled with a gas (an iner
t gas or a
reactive gas) at a pressure ranging from a few mTorr to atmospheric pressure. Due to the potential difference, electrons
that are emitted from the cathode, are accelerated away from the cathode, and give rise to collisions with the gas atoms
molecules. If e* is an excited electron in plasma, the following types of reactions can occur in plasma:

The exci
tation collisions give rise to excited species, which can decay to lower levels by the emission of light. This
process is responsible for the characteristic name of the "glow" discharge. The ionization collisions create ion
pairs. The ions are acc
elerated toward the cathode, where they release secondary electrons. These electrons are
accelerated away from the cathode and can give rise to more ionization collisions. In its simplest way, the combination
of secondary electron emission at the cathode a
nd ionization in the gas, gives rise to a self
sustained plasma. Most
modern plasmas are generated by either a DC current flowing through the gas or a radio frequency (RF) field exposed
to the gas. RF plasmas do not require DC current flow, and thus, can b
e used to process insulating and conducting

In the direct current (DC) glow discharge, a continuous potential difference is applied between cathode and anode,
giving rise to a constant current. A schematic representation of a chamber, plasma g
low and plot of potential is given in
Fig. 3.28. The ionization breakdown of a heavy inert gas such as argon occurs when a spark voltage (V
) is applied
which is greater than the breakdown voltage (V
). The number of ions resulting (Ar

plus electrons e
) will be much
lower; typically less than 1% of the atoms in the chamber. Plasma maintains almost perfect charge balance. To maintain
a self sustaining plasma, the V

has to to much higher compared to V
. The plasma is highly conductive at low
s due to electrons. The conductivity of ions compared to electrons is much lower because ions are heavy and
have much lower velocities. However, this set
up gives problems, due to the constant current; the electrodes will be
charged up, leading to burn

of the glow discharge.

Fig. 3.28: A schematic representations of a chamber, plasma glow and plot of potential

One important characteristic of plasma is their capability to shield out electrical potentials applied to them

redistributing their charged constituents. When an object is placed in plasma, it acquires a net negative charge because
the electron thermal speed is much greater than the ion thermal speed, which causes more electrons to hit the object
than ions. As
the object charges negatively, the electrons start to be repelled. Equilibrium occurs when the electron
current collected by the object balances the incident ion current. An electrically polarized region is thereby formed
around the object. This polarized
region is called a plasma sheath, or sometimes a positive ion sheath, because the
electrons are largely excluded from the sheath. The exact form of the electrostatic potential distribution is complicated
however in specific cases the potential decays expon
entially with a characteristic length scale given by the Debye

Similar to the above discussed evaporation kinetics; there are three processes in sputtering also as shown in Fig. 3.29.
The source material is to be change to gaseous state, then the
transport source atoms to substrate and finally the
deposition atoms on substrate.

Fig. 3.29 : Kinetics of a
Sputtering Process

First we want see how the target atoms going into the gas phase. Sputtering is a momentum transfer process.
Approximately 95 % of incident energy goes into the target top 10 Å layers and the target need to be cooled. This
process can be

modeled using hard sphere collisions. 5% of incident energy is carried off by target atoms and
approximately 1 to 2% of the atoms in the target are ejected as ions and electrons (T and T
). These electrons are
useful in keeping the plasma going. Target at
oms come off with a non
uniform distribution. The process can be
characterized by sputter yield (S) and it is the number ejected / number incident ions. S depends on mass and binding
energy of the target material, mass and energy of the sputtering gas, and

the angle of incident. The sputter yield is
found maximum at about 20
30 degrees from glancing. Usually there exists a threshold energy exists and typical values
of S about 1
10. In sputtering, unlike in evaporation, the composition of alloy in deposited
film is approximately the same
as alloy in target. This is because of the slow diffusion mixing of solids in case sputtering compared to rapid mixing in

During the transport of atoms of to substrate, they pass through Ar gas and plasma enviro
nment. Typically one Ar

for every 10,000 Ar neutrals results and the electrons in plasma collide with Ar neutrals to form ions and additional
electrons. Target atoms collide with Ar atoms, Ar

ions and electrons and typically lose 1
10 eV energy. The
can be considered as random walk "diffusion" through gas. This is not a line of sight process and one can coat around
corners. During the deposition, not only target atoms, but also the ions/electron can impinge on substrate. The growth of
ed films is enhanced by these energetic particles as well as by substrate heating to100


Sputter Deposition Techniques

There are three basic sputtering techniques; DC (diode), RF (radio frequency) and magnetron. As discussed above, the
DC sputte
ring is simple and is shown in Fig. 3.30. When the Argon gas pressure is increased the scattering of Ar ions
with neutral Ar atoms also increases. If the gas pressure is decreased, the number of Ar/ Ar

is also decreased. As a
result, the optimum depositio
n rate is around 100 mTorr which is a compromise between the available number of Ar ions
and their scattering. If one can increase the number of ions without increasing the number of neutrals, one can operate
at lower pressures.

Fig. 3.30 : DC plasma system

Increasing the sputter voltage increases the sputter yield and typically voltages are from
2 to

5 kV. The deposition rate
is increased by means of sputter yield and is found decreased with increasing Ar pressure. Usually a substrate bias
voltage is applied to avoid electrons hitting the substrate while neutral atoms being deposited independently. S
temperature increases with increasing sputter voltage and decreases with increasing substrate bias. The deposition rate
also usually decreases with increasing substrate bias.

RF Sputter Deposition

In DC systems, positive charge builds up on the

cathode (target) and typically one requires 10

volts to sputter
insulators. To avoid this charge build up, an RF potential is used and can be used for depositing insulating materials.
Sputter deposition occurs when target is negative. The schematic diag
ram of an RF plasma system is shown in Fig.
3.31. The substrate and chamber make a very large electrode and so not much sputtering of substrate occurs.

Fig. 3.31 : Radio Frequency (RF) plasma system

When the frequencies are less than about 50 kHz, electrons and ions in plasma are mobile and both follow the switching
of the anode and cathode. This is equivalent to

DC sputtering of both surfaces. At frequencies above about 50 kHz,
since ions (heavy) can no longer follow the switching and electrons can neutralize positive charge build up sputter
deposition occurs as shown in figure. And it is easy to keep plasma goin
g under these conditions. RF sputter can
operate at lower Ar pressures (1
15 mTorr) and the fewer gas collisions lead to more line of sight deposition.

The Magnetron Sputter Deposition

The Magnetron Sputter Deposition can be used with DC or RF. The goal

is to increase ionization of Ar. This leads to
higher sputter rates at lower Ar pressures (down to 0.5 mTorr) and more line of sight depositions. The probability of
electrons striking Ar is increased by increasing electron path length using a crossed elec
tric and magnetic fields. This is
achieved by placing magnets (200 Gauss) behind target. The basics electromagnetic interactions are shown in Fig.
3.32. This leads to traps electrons near cathode resulting more ionization near cathode (10 times) and fewer
reach substrate (less heating).

Fig. 3.32: Direction of Electric field Magnetic field lines during
their interactions

Table 6 : Comparison of evaporation and sputtering



low energy atoms

higher energy atoms

high vacuum path

few collisions

line of sight deposition

little gas in film

low vacuum, plasma path

many coll

less line of sight deposition

gas in film

larger grain size

smaller grain size

fewer grain orientations

many grain orientations

poorer adhesion

better adhesion

So far we have discussed two important physical vapor deposition techniques,

evaporation and sputtering and the
important features of these two are compared in Table 6. In the next section we will study Chemical Vapour deposition
(CVD) process that involves depositing a solid material from a gaseous phase. It is similar in some re
spects to PVD.
PVD differs in that the sources are solid, with the material to be deposited being vaporized from a solid target and
deposited onto the substrate. The formerly discussed sputtering or chemical vapor deposition systems can be combined
with io
n assisted and reactive ions deposition schemes. In case of ion assisted deposition, the surface is bombarded
with relatively low voltages (50

300 eV) ions not necessarily same type as in film. The goal is not typically to
incorporate ions in film but fo
r physical rearrangement and local heating. It can change film properties. Similarly in
Reactive Sputter deposition, reactive gases like oxygen, nitrogen etc is added to chamber during deposition to facilitate
chemical reaction on substrate and target.

mical Vapor Deposition

CVD is an extremely versatile process that can be used to process almost any metallic or ceramic compound. Some of
these include elements, metals and alloys, carbides, nitrides, oxides and intermetallic compounds. Materials are
sited from the gaseous state during CVD and there p recursor gases are often diluted in carrier gases and
delivered into the reaction chamber. As they pass over or come into contact with a heated substrate, they react or
decompose forming a solid phase whi
ch and are deposited onto the substrate. The substrate temperature is critical and
can influence what reactions will take place. In this section we will discuss the basic steps involved in a CVD process,
typical precursor materials used, different types of

CVD processes and systems.

Fig. 3.33 : Schematic diagram of a horizontal CVD system

The basic steps in CVD f
ilm growth are production of appropriate source gas, transport of gas to substrate, adsorption
of gas on substrate, reaction on substrate and the transport of "waste" products away from substrate. The growth of
films depends on all these kinetics. CVD can
be carried out in a horizontal reactor as shown in Fig. 3.33. A CVD
apparatus will consist of several basic components:

Gas delivery system

For the supply of precursors to the reactor chamber

Reactor chamber

Chamber within which deposition takes plac

Substrate loading mechanism

A system for introducing and removing substrates

Energy source

Provide the energy/heat that is required to get the precursors to react/decompose

Vacuum system

A system for removal of all other gaseous species other th
an those required for the

Exhaust system

System for removal of volatile by
products from the reaction chamber.

Exhaust treatment systems

In some instances, exhaust gases may not be suitable for release into the
atmosphere and may

require treatment or conversion to safe/harmless compounds.

Process control equipment

Gauges, controls etc to monitor process parameters such as pressure,
temperature and time. Alarms and safety devices would also be included in this category.

The flo
w of gases is parallel to the surface of the wafers. The drop in growth rate with distance can be reduced by tilting
the susceptor by about 5°. The goals of m ass transport in gas are to deliver gas uniformly to substrate (uniform films)
and to optimize fl
ow for maximum deposition rate. From kinetic theory of gasses, we have seen in previous sections that
the dimensions of the system (D) is proportional to
. In a CVD system, the pressure is reduced for higher D and
higher deposition rate. And the low flow rates produces laminar flow which desirable compared to turbulent flow at high
flow rates.

Fig. 3.34 : A laminar flow passing over plate

A simple case of laminar flow passing a plate is shown in Fig. 3.34. The velocity of fl
ow near plate is very small and this
results in a stagnant layer. The gas can diffuse through stagnant layer to surface. The mass transport depends
fundamentally on reactant concentration, diffusivity and on boundary layer thickness. In terms of experiment
parameters it depends on pressure, gas velocity, temperature distribution, reactor geometry and gas properties like
viscosity etc.

Fig. 3.35 : Basic model of CVD kinetics


has developed a simple model in 1967. Consider a gas AB decomposed to solid A and gas B. Let F
= flux to
surface, F
= flux consumed in film, C
= concentration of AB in gas, C
= concentr
ation of AB at surface.

where h
= gas diffusion rate constant and where k
= surface rate constant. In steady state
: F
= F
= F leading

The growth rate of film is proportional to F and there are rate
limiting cases. In the case o
f small h
, it is mass transfer
limited and growth controlled by transfer to substrate; h

is not very temperature dependent the common limit is at
higher temperatures. For small k
, it is surface reaction limited and the growth controlled by processes on
surface like
adsorption, decomposition, surface migration, chemical reaction, desorption of products. The k

is highly temperature
dependent (increases with T), common limit at lower temperatures. This is often preferred scheme.

The gas sources are therma
lly, optically, or electrically (plasma) reacted with a surface. There are four different types of
CVDs are popular; Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD at ~0.2 to 20 torr), Metal Organic
CVD (MOCVD) and Plasma Enhance CVD where plasm
as are used to force reactions that would not be possible at low

Low Pressure Chemical Vapor Deposition (LPCVD)

Low Pressure Chemical Vapor Deposition (LPCVD) can be used for a variety of materials such as polysilicon for gate
contacts, very

short interconnect lines and resistors in analog technologies; thick oxides used for isolation between
metal interconnects; doped oxides useful for global planarization; nitrides and other dielectrics for isolation or capacitors

(higher K materials for la
rger capacitance) and metals for seed layers for vias and interconnect lines (not typically used